Semiconductor structure and preparation method thereof, integrated circuit and electronic equipment

Abstract

The embodiment of the invention discloses a semiconductor structure and a preparation method thereof, an integrated circuit and electronic equipment, and relates to the technical field of semiconductors. The semiconductor structure comprises a substrate, a signal line and a transistor. The substrate has a first surface. The signal line is located on the first surface. The signal line comprises a wiring layer and a first ohmic contact layer which are sequentially stacked in the direction perpendicular to and away from the first surface. The transistor is on the first ohmic contact layer. The transistor comprises a semiconductor layer, and the semiconductor layer comprises a first electrode, a channel part and a second electrode which are sequentially stacked in the direction perpendicular to and away from a first surface. The signal line is of a structure independent of the substrate, and the signal line is located below the transistor, so that the process difficulty of the semiconductor structure can be reduced, the signal line is prevented from occupying an extra area, and the area utilization rate of the semiconductor structure is improved; the resistance of the signal line can be reduced, and the electrical performance of the integrated circuit is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same, an integrated circuit, and an electronic device. Background Art

[0002] As Moore's Law continues to advance, the feature size of complementary metal-oxide-semiconductor field-effect transistors (CMOSFET, hereinafter referred to as transistors) in chips continues to shrink and has reached its physical limit, resulting in contradictions in power consumption, performance, and cost of chips. In order to improve the PPAC (performance, power, area, cost) of chips, the architecture of transistors has gradually evolved from a two-dimensional (2D) planar structure to a three-dimensional (3D) structure, and the arrangement, spacing, and routing area of ​​transistors have also been gradually compressed and optimized.

[0003] In transistors of different architectures, the semiconductor source and / or the semiconductor drain need to form a metal-semiconductor contact (also called an ohmic contact) with the wiring. For a three-dimensional vertical channel transistor, one of the semiconductor source and the semiconductor drain is arranged at the bottom of the three-dimensional structure, and the other is arranged at the top of the three-dimensional structure. Taking the semiconductor source arranged at the bottom of the three-dimensional structure as an example, since the three-dimensional structure has a certain aspect ratio, the process of forming an ohmic contact between the semiconductor source and the wiring is relatively difficult and easily affects the area utilization of the chip. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, an integrated circuit, and an electronic device, which are used to reduce the process difficulty of the semiconductor structure and improve the area utilization of the semiconductor structure.

[0005] In order to achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a semiconductor structure is provided. The semiconductor structure includes: a substrate, a signal line, and a transistor. The substrate has a first surface. The signal line is located on the first surface. The signal line includes a routing layer and a first ohmic contact layer stacked in sequence in a direction perpendicular to and away from the first surface. The transistor is located on the first ohmic contact layer. The transistor includes a semiconductor layer, and the semiconductor layer includes a first pole, a channel portion, and a second pole stacked in sequence in a direction perpendicular to and away from the first surface.

[0007] The semiconductor structure provided in the embodiment of the present application, by connecting the semiconductor layer of the transistor to the first ohmic contact layer of the signal line, and arranging the signal line below the semiconductor layer, can first prepare and form the signal line in the process of preparing and forming the semiconductor structure, and then form the semiconductor layer, so that the first ohmic contact layer in the signal line and the first electrode form an ohmic contact. This process idea is different from the process idea of ​​first forming a semiconductor layer and then forming a signal line to make an ohmic contact, and can avoid the technical problems caused by this process idea. On the one hand, the signal line and the transistor can share part of the space, effectively reducing the area occupied by the signal line, and improving the area utilization of the semiconductor structure and the integrated circuit. On the other hand, there is no need to etch to form a deep hole with a large depth-to-width ratio, and there is no need to etch the bottom of the semiconductor layer, which can reduce the process difficulty and process cost of the semiconductor structure and improve the reliability of the semiconductor structure. On the other hand, the signal line is a structure independent of the substrate, rather than a signal line that is an integral structure with the substrate and formed of heavily doped semiconductor materials. This can effectively reduce the resistance of the signal line. When the semiconductor structure is applied to logic devices, the parasitic impedance of the overall circuit can be reduced; when the semiconductor structure is applied to storage devices, the impact on the read window of the storage device can be reduced, greatly improving the performance of the integrated circuit to which the semiconductor structure is applied.

[0008] In a possible implementation of the first aspect, the semiconductor structure further includes: an anti-oxidation conductive layer located between the first ohmic contact layer and the first pole. The first pole is in contact with the anti-oxidation conductive layer. The anti-oxidation conductive layer has pores, the size of which is larger than the atomic diameter of the material of the first ohmic contact layer. The anti-oxidation conductive layer can serve as a diffusion layer, and the atoms of the material of the first ohmic contact layer can diffuse through the anti-oxidation conductive layer to the lower surface of the first pole, so that the first ohmic contact layer can form a good ohmic contact with the first pole. Moreover, the anti-oxidation conductive layer has good anti-oxidation properties, and the anti-oxidation conductive layer can be used to protect the first ohmic contact layer from oxidation, so as to avoid affecting the contact resistance between the first ohmic contact layer and the second pole.

[0009] In a possible implementation of the first aspect, the orthographic projection of the first electrode on the first surface is located within the orthographic projection range of the anti-oxidation conductive layer on the first surface. In this way, the anti-oxidation conductive layer can be used to cover the portion of the first ohmic contact layer opposite to the first electrode, thereby protecting the portion of the first ohmic contact layer and preventing the portion of the first ohmic contact layer from being oxidized, thereby affecting the ohmic contact between the portion of the first ohmic contact layer and the first electrode.

[0010] In a possible implementation of the first aspect, the orthographic projection of the anti-oxidation conductive layer on the first surface coincides with the orthographic projection of the first ohmic contact layer on the first surface. This can increase the area of ​​the first ohmic contact layer covered by the anti-oxidation conductive layer, enhance the protective effect of the anti-oxidation conductive layer on the first ohmic contact layer, greatly reduce the area of ​​the first ohmic contact layer exposed outside the anti-oxidation conductive layer, and greatly reduce the probability of the first ohmic contact layer being oxidized.

[0011] In a possible implementation of the first aspect, along a direction perpendicular to the first surface, the thickness of the anti-oxidation conductive layer is less than the thickness of the routing layer. In this way, on the basis of using the anti-oxidation conductive layer to provide anti-oxidation protection for the first ohmic contact layer, the influence of the anti-oxidation conductive layer on the contact resistance between the first ohmic contact layer and the first electrode can be reduced or even eliminated.

[0012] In a possible implementation of the first aspect, the orthographic projection of the first ohmic contact layer on the first surface coincides with the orthographic projection of the wiring layer on the first surface. In this way, in the process of preparing the signal line, the conductive film where the wiring layer is located and the conductive film where the first ohmic contact layer is located can be synchronously etched in the same etching process to form the first ohmic contact layer and the wiring layer at the same time, which is conducive to simplifying the preparation process of the semiconductor structure and improving the preparation efficiency of the semiconductor structure.

[0013] In a possible implementation of the first aspect, the semiconductor structure further includes: a second ohmic contact layer. The second ohmic contact layer is located on the second electrode and contacts the second electrode. The second ohmic contact layer is provided to improve the contact performance between the second electrode and other metal structures, thereby improving the electrical performance of the semiconductor structure.

[0014] In a possible implementation of the first aspect, the transistor further includes: a gate dielectric layer and a gate. The gate dielectric layer surrounds the side of the channel portion. The gate is located on the side of the gate dielectric layer away from the channel portion. In a direction perpendicular to the first surface, the gate dielectric layer and the gate are both located between the first pole and the second pole. The maximum size of the positive projection of the transistor on the first surface in the first direction is greater than the width of the signal line. In this way, the signal line does not occupy additional area, which is conducive to further improving the area utilization of the semiconductor structure and the integrated circuit, and improving the integration of the semiconductor structure and the integrated circuit.

[0015] In a second aspect, a method for preparing a semiconductor structure is provided. The method comprises: providing a substrate; the substrate has a first surface; forming a signal line on the first surface; the signal line comprises a routing layer and a first ohmic contact layer sequentially stacked in a direction perpendicular to and away from the first surface; forming a semiconductor layer on the first ohmic contact layer; the semiconductor layer comprises a first pole, a channel portion, and a second pole sequentially stacked in a direction perpendicular to and away from the first surface.

[0016] In a possible implementation of the second aspect, before forming the semiconductor layer on the first ohmic contact layer, the preparation method further includes: forming an anti-oxidation conductive layer on the first ohmic contact layer. The anti-oxidation conductive layer has pores, and the size of the pores is larger than the atomic diameter of the material of the first ohmic contact layer; and the anti-oxidation conductive layer is in contact with the first electrode.

[0017] In a possible implementation of the second aspect, forming a signal line and an anti-oxidation conductive layer includes: sequentially forming a routing film, a first ohmic contact film, and an anti-oxidation conductive film on the first surface in a direction perpendicular to and away from the first surface. Synchronously etching the anti-oxidation conductive film, the first ohmic contact film, and the routing film to form an anti-oxidation conductive layer, a first ohmic contact layer, and a routing layer. The orthographic projection of the anti-oxidation conductive layer on the first surface, the orthographic projection of the first ohmic contact layer on the first surface, and the orthographic projection of the routing layer on the first surface overlap.

[0018] In a third aspect, an integrated circuit is provided. The integrated circuit comprises: a packaging structure, and at least one semiconductor structure packaged inside the packaging structure. The semiconductor structure is the semiconductor structure as described in any embodiment of the first aspect.

[0019] In a fourth aspect, an electronic device is provided. The electronic device comprises: a circuit board, and an integrated circuit electrically connected to the circuit board. The integrated circuit is the integrated circuit as described in any embodiment of the third aspect.

[0020] The technical effects brought about by any one of the second to fourth aspects can refer to the technical effects brought about by different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A structural diagram of an electronic device provided in an embodiment of the present application;

[0022] Figure 2 A partial structural diagram of an electronic device provided in an embodiment of the present application;

[0023] Figure 3 A structural diagram of an integrated circuit provided in an embodiment of the present application;

[0024] Figure 4 A structural diagram of another integrated circuit provided in an embodiment of the present application;

[0025] Figure 5 A structural diagram of a semiconductor structure in a possible implementation manner;

[0026] Figure 6 is a structural diagram of another semiconductor structure in a possible implementation manner;

[0027] Figure 7a to Figure 7e A structural diagram corresponding to each step in a method for preparing a semiconductor structure in a possible implementation manner;

[0028] Figure 8a to Figure 8d A structural diagram corresponding to each step in another method for preparing a semiconductor structure in a possible implementation manner;

[0029] Fig. 9 A structural diagram of a semiconductor structure provided in an embodiment of the present application;

[0030] Fig.10 A structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0031] Fig.11 An equivalent circuit diagram of a semiconductor structure provided in an embodiment of the present application;

[0032] Fig.12 A partial structural diagram of a semiconductor structure provided in an embodiment of the present application;

[0033] Fig.13 A partial structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0034] Fig.14 A partial structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0035] Fig.15 A structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0036] Fig.16 A structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0037] Fig.17 A top view of a semiconductor structure provided in an embodiment of the present application;

[0038] Fig.18 A flowchart of a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0039] Figure 19a to Figure 19f A structural diagram corresponding to each step in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0040] Figure 20a to Figure 20c A structural diagram corresponding to each step in another method for preparing a transistor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] The following will describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0042] In the description of the embodiments of the present application, unless otherwise specified, "multiple" refers to two or more than two. "At least one item" or similar expressions refer to any combination of these items, including any combination of single items or plural items. For example, at least one item of a, b, and c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0043] In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second" and the like are used to distinguish the same items or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not necessarily limit the differences. At the same time, in the embodiments of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design solutions. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0044] When describing some embodiments, the expression "connected" and its derivatives are used. The term "connected" should be understood in a broad sense. For example, "connected" can be fixedly connected, detachably connected, or integrated; it can be directly connected or indirectly connected through an intermediate medium. In addition, the use of "based on" means openness and inclusiveness, because the process, step, calculation or other action "based on" one or more of the conditions or values ​​can be based on additional conditions or values ​​beyond the described values ​​in practice.

[0045] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0046] In the embodiments of the present application, "upper" and "lower" are not limited to being defined relative to the orientation of the schematic placement of the components in the drawings. It should be understood that these directional terms can be relative concepts, which are used for description and clarification relative to the components, and can change accordingly according to the change in the orientation of the components in the drawings. In the drawings, for the sake of clarity, the thickness of the layers and regions is exaggerated, and the dimensional ratio relationship between the parts in the drawings does not reflect the actual dimensional ratio relationship. Therefore, changes in the shape relative to the drawings due to, for example, manufacturing technology and / or tolerances can be envisioned. Therefore, the exemplary embodiments should not be interpreted as being limited to the shape of the areas shown in the present application, but include shape deviations caused by, for example, manufacturing. For example, an etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the areas of the device, and are not intended to limit the scope of the exemplary embodiments.

[0047] In addition, the architecture and scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. A person of ordinary skill in the art can appreciate that with the evolution of the architecture and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0048] The embodiment of the present application provides an electronic device. The electronic device may be a mobile phone, a tablet computer (pad), a television, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a smart wearable device (e.g., a smart watch, a smart bracelet), an in-vehicle device, a smart home device and / or a smart city device, etc. The embodiment of the present application does not impose any special restrictions on the specific type of the electronic device.

[0049] Figure 1 The following is a schematic diagram of the architecture of an electronic device provided in an embodiment of the present application. Figure 1 As shown, the electronic device 1000 includes: a memory 100, a processor 200, an input device 300, an output device 400 and other components. Those skilled in the art can understand that Figure 1 The structure of the electronic device shown in the figure does not constitute a limitation on the electronic device 1000. The electronic device 1000 may include, for example Figure 1 More or fewer components may be shown, or they may be combined as shown. Figure 1 Some of the components shown may be combined with Figure 1 The components shown are arranged differently.

[0050] The memory 100 is used to store software programs and modules. The memory 100 mainly includes a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the electronic device (such as audio data, image data, phone book, etc.), etc. In addition, the memory 100 includes an external memory 110 and an internal memory 120. The data stored in the external memory 110 and the internal memory 120 can be transmitted to each other. The external memory 110 includes, for example, a hard disk, a USB flash drive, a floppy disk, etc. The internal memory 120 includes, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a read-only memory, etc.

[0051] The processor 200 is the control center of the electronic device 1000. It uses various interfaces and lines to connect various parts of the entire electronic device 1000. By running or executing software programs and / or modules stored in the memory 100, and calling data stored in the memory 100, it performs various functions of the electronic device 1000 and processes data, thereby monitoring the electronic device 1000 as a whole. Optionally, the processor 200 may include one or more processing units. For example, the processor 200 may include a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor (DSP), and a neural network processor, and may also be other specific integrated circuits (application specific integrated circuits, ASICs), etc. Figure 1 In the example, the processor 200 is a CPU, and the CPU may include an operator 210 and a controller 220. The operator 210 obtains data stored in the internal memory 120, processes the data stored in the internal memory 120, and generally sends the processed result back to the internal memory 120. The controller 220 may control the operator 210 to process the data, and the controller 220 may also control the external memory 110 and the internal memory 120 to store data or read data. The memory 100 may store data generated by the processor 200.

[0052] The input device 300 is used to receive input digital or character information, and to generate key signal input related to the user settings and function control of the electronic device 1000. For example, the input device 300 may include a touch screen and other input devices. The touch screen, also known as a touch panel, can collect the user's touch operation on or near the touch screen (such as the user's operation on or near the touch screen using any suitable object or accessory such as a finger, a stylus, etc.), and drive the corresponding connection device according to a pre-set program. Optionally, the touch screen may include two parts: a touch detection device and a touch controller. Among them, the touch detection device detects the user's touch direction, detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into the touch point coordinates, and then sends it to the processor 200, and can receive and execute the command sent by the processor 200. In addition, the touch screen can be implemented using multiple types such as resistive, capacitive, infrared and surface acoustic waves. Other input devices may include but are not limited to one or more of a physical keyboard, function keys (such as volume control keys, power switch keys, etc.), a trackball, a mouse, a joystick, etc. The controller 220 in the processor 200 can also control the input device 300 to receive input signals or not receive input signals. In addition, the input digital or character information received by the input device 300, and the key signal input related to the user settings and function control of the electronic device can be stored in the internal memory 120.

[0053] The output device 400 is used to output a signal corresponding to the data input by the input device 300 and stored in the internal memory 120. For example, the output device 400 outputs a sound signal or a video signal. The controller 220 in the processor 200 can also control the output device 400 to output a signal or not output a signal.

[0054] It should be noted that Figure 1 The thick arrows in the figure are used to indicate data transmission, and the direction of the thick arrows indicates the direction of data transmission. For example, the one-way arrow between the input device 300 and the internal memory 120 indicates that the data received by the input device 300 is transmitted to the internal memory 120. For another example, the two-way arrow between the operator 210 and the internal memory 120 indicates that the data stored in the internal memory 120 can be transmitted to the operator 210, and the data processed by the operator 210 can be transmitted to the internal memory 120. Figure 1 The thin arrows in the figure represent components that can be controlled by the controller 220. For example, the controller 220 can control the external memory 110, the internal memory 120, the operator 210, the input device 300, the output device 400, and the like.

[0055] Optional, such as Figure 1The electronic device 1000 shown may also include various sensors, such as a gyroscope sensor, a hygrometer sensor, an infrared sensor, a magnetometer sensor, etc., which are not described in detail here. Optionally, the electronic device 1000 may also include a wireless fidelity (WiFi) module, a Bluetooth module, etc., which are not described in detail here.

[0056] Figure 2 FIG. 1 schematically shows a partial structure of the electronic device 1000. Figure 2 As shown, the electronic device 1000 may further include a circuit board 500 and an integrated circuit 600 . The integrated circuit 600 is disposed on the circuit board 500 and is electrically connected to the circuit board 500 .

[0057] like Figure 2 As shown, the electronic device 1000 further includes a connector disposed between the circuit board 500 and the integrated circuit 600, and the integrated circuit 600 is electrically connected to the circuit board 500 via the connector. The connector may be, for example, a ball grid array (BGA).

[0058] Optionally, other structures, such as a packaging substrate, may be provided between the connector and the circuit board 500. That is, the integrated circuit 600 may be packaged on the packaging substrate and then connected to the circuit board 500 via the packaging substrate.

[0059] The number of the integrated circuit 600 may be one or more. When the number of the integrated circuit 600 is more than one, the integrated circuits 600 may be arranged in a flat pattern or in a stacked pattern.

[0060] The above-mentioned integrated circuit 600 can be a wafer or a chip. When the integrated circuit 600 is a chip, the chip can be a bare chip (also called a grain or particle) obtained by cutting the wafer, or it can be a packaged chip obtained by packaging the bare chip. Optionally, the above-mentioned integrated circuit 600 has a logic calculation function. In this case, the integrated circuit 600 can be applied to a logic device (such as the above-mentioned operator 210, controller 220, sensor, etc.); or, the above-mentioned integrated circuit 600 has a storage function. In this case, the integrated circuit 600 can also be applied to a storage device (such as the above-mentioned external memory 110, internal memory 120, etc.), which is not limited in this embodiment of the present application.

[0061] Figure 3 and Figure 4 The structure of an integrated circuit 600 is shown respectively, wherein: Figure 3 Taking the application of the integrated circuit 600 to a logic device as an example, Figure 4 Take the application of the integrated circuit 600 to a memory device as an example.

[0062] like Figure 3 and Figure 4 As shown, the integrated circuit 600 may include a semiconductor structure 610 and a packaging structure 620 ( Figure 4 The semiconductor structure 610 is packaged inside the packaging structure 620. The number of the semiconductor structure 610 can be one or more. Figure 3 A semiconductor structure 610 is shown schematically, Figure 4 Four semiconductor structures 610 are illustrated.

[0063] It is understandable that the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the integrated circuit 600. In other embodiments of the present application, the integrated circuit 600 may include more or fewer components than shown, or combine some components, or separate some components, or arrange the components differently.

[0064] For some examples, see Figure 3 The semiconductor structure 610 may include one or more transistors 1, which are packaged inside a packaging structure 620. The packaging structure 620 may include a substrate 621 and a packaging shell 622, and the packaging shell 622 is bonded to the substrate 621 by an insulating adhesive.

[0065] Exemplarily, the substrate 621 has high heat dissipation and electrical conductivity. The material of the substrate 621 may include a composite material, and the structure of the substrate 621 may be a laminated structure. Optionally, the material of the substrate 621 may include copper and molybdenum, and the substrate 621 is composed of a copper layer / molybdenum layer / copper layer stacked in sequence.

[0066] Exemplarily, the transistor 1 can be bonded to the substrate 621 and packaged in the space formed by the package shell 622 and the substrate 621. Some electrodes (such as the semiconductor source) of the transistor 1 can be connected to the substrate 621, and some electrodes (such as the semiconductor drain and the gate) of the transistor 1 can be connected to the pin through conductive wire bonding, and the pin is provided on the insulating layer (such as insulating ceramic), and the insulating layer is bonded to the substrate 621 through an insulating adhesive. In addition, one end of the pin is exposed from the package structure 620 to connect other circuits.

[0067] For example, the semiconductor structure 610 further includes a plurality of signal lines (also referred to as metal wirings), and some electrodes of the transistor 1 (eg, semiconductor source) may also be electrically connected to the signal lines and conduct electricity with the substrate 621 through the signal lines.

[0068] In other examples, such as Figure 4As shown, the integrated circuit 600 may further include a controller 630. The packaging structure covers the controller 630 and the semiconductor structure 610. The semiconductor structure 610 includes one or more transistors and a storage structure electrically connected to the transistors. The storage structure is used to store data.

[0069] The controller 630 may be coupled to the semiconductor structure 610 and used to control the semiconductor structure 610 to store data. For example, the controller 630 may manage the data stored in the semiconductor structure 610 and communicate with an external device (e.g., a host). For another example, the controller 630 may also control the operation of the semiconductor structure 610, such as a read operation or a write operation. Of course, the controller 630 may also perform any other suitable functions, and is not limited to the two examples.

[0070] Optionally, continue to Figure 4 The controller 630 and the semiconductor structure 610 can be independent of each other and arranged in a flat pattern. Of course, the controller 630 can also be integrated on the substrate through the front end of line (FEOL) process, and the semiconductor structure 610 can be integrated on the controller 630 through the back end process.

[0071] For example, the semiconductor structure 610 further includes a plurality of signal lines, and part of the electrodes of the transistor (eg, the semiconductor source) may also be electrically connected to the signal lines and coupled to the controller 630 through the signal lines.

[0072] It is understandable that, whether the integrated circuit 600 is applied to a logic device or a memory device, the transistor included in the semiconductor structure 610 in the integrated circuit 600 needs to be electrically connected to the signal line so that the semiconductor source and / or semiconductor drain of the transistor forms an ohmic contact with the signal line to receive the electrical signal from the signal line. The contact resistance has a very important influence on the performance of the transistor and the performance of the integrated circuit 600.

[0073] As the architecture of the above transistor changes, the manner in which the semiconductor source and / or semiconductor drain forms ohmic contact with the signal line also changes accordingly, which is schematically described below with reference to the accompanying drawings.

[0074] In the first possible implementation, Figure 5 As shown, the architecture of the transistor is a two-dimensional planar structure, and the electrical connection between the signal line 2 and the first electrode 11b is taken as an example. The transistor includes a semiconductor layer 11, and the semiconductor layer 11 includes a channel portion 11a, and a first electrode 11b and a second electrode 11c located on the left and right sides of the channel portion 11a. The signal line 2 is connected above the first electrode 11b.

[0075] In this implementation, the first electrode 11b and the second electrode 11c can be heavily doped first; then the signal line 2 is formed so that the signal line 2 and the first electrode 11b are in contact; thereafter, through a multi-step thermal process, the metal ions in the signal line 2 are diffused into the first electrode 11b to form metal silicide or other compounds, thereby achieving ohmic contact with lower contact resistance.

[0076] However, transistors with two-dimensional planar structures occupy a large area, and the area utilization rate of semiconductor structures and integrated circuits is low.

[0077] In the second possible implementation, Figure 6 As shown, the architecture of the transistor is a three-dimensional structure, and the electrical connection between the signal line 2 and the first electrode 11b is taken as an example. The transistor includes a semiconductor layer 11, and the semiconductor layer 11 includes a channel portion 11a, and a first electrode 11b and a second electrode 11c located on the upper and lower sides of the channel portion 11a. The signal line 2 passes through the dielectric layer covering the second electrode 11c and is electrically connected to the second electrode 11c.

[0078] In this implementation, a portion of the second electrode 11c extends out of the channel portion 11a. Then, a portion of the dielectric layer covering the second electrode 11c can be etched to form a deep hole exposing the second electrode 11c; then, a signal line 2 can be formed in the deep hole; and then, through a multi-step thermal process, the metal ions in the signal line 2 diffuse into the first electrode 11b to form a metal silicide or other compound, thereby achieving an ohmic contact with a lower contact resistance.

[0079] However, the portion of the second electrode 11c extending out of the channel portion 11a needs to occupy a certain area, which easily increases the area occupied by the transistor, affecting the area utilization of the semiconductor structure and the integrated circuit. Moreover, the deep hole has a large aspect ratio, which increases the process difficulty of the semiconductor structure.

[0080] In a third possible implementation, if Figure 7e As shown, the architecture of the transistor is a three-dimensional structure, and the electrical connection between the signal line 2 and the first electrode 11b is taken as an example. The transistor includes a semiconductor layer 11, and the semiconductor layer 11 includes a channel portion 11a, and a first electrode 11b and a second electrode 11c located at the upper and lower sides of the channel portion 11a. The signal line 2 is located below the second electrode 11c and is electrically connected to the second electrode 11c.

[0081] In this implementation, if Figure 7a and Figure 7b As shown in FIG. 1 , after forming the semiconductor layer 11, the bottom of the semiconductor layer 11 may be etched to expose the second electrode 11c; then, as shown in FIG. Figure 7c As shown, a metal material is filled in the gap between two adjacent semiconductor layers 11 to form a metal film; then, as shown in FIG. Figure 7d As shown, the metal film is selectively removed, and a portion of the metal film located at the bottom of the second pole 11c is retained to obtain a signal line 2 connected to the second pole 11c; then, through a multi-step thermal process, the metal ions in the signal line 2 diffuse into the first pole 11b to form metal silicide or other compounds, thereby achieving ohmic contact with lower contact resistance.

[0082] However, the signal line 2 needs to occupy a certain area, which easily affects the area utilization of the semiconductor structure and the integrated circuit. Moreover, it is difficult to etch the bottom of the semiconductor layer 11, and an additional mask is required, which not only increases the process difficulty of the semiconductor structure, but also increases the process cost. Figure 7e As shown, the signal line 2 is easily short-circuited with the gate 12 (also called word line) of the transistor, which reduces the reliability of the semiconductor structure.

[0083] Based on this, the present application also provides a fourth possible implementation method, such as Figure 8d As shown, the architecture of the transistor is a three-dimensional structure, and the electrical connection between the signal line 2 and the first electrode 11b is taken as an example. The transistor includes a semiconductor layer 11, and the semiconductor layer 11 includes a channel portion 11a, and a first electrode 11b and a second electrode 11c located on the upper and lower sides of the channel portion 11a. The signal line 2 is located below the second electrode 11c and is an integral structure with the second electrode 11c.

[0084] In this implementation, if Figure 8a As shown, after forming the semiconductor layer 11, the second electrode 11c is heavily doped; then, as shown in Figure 8b As shown, the semiconductor substrate is etched to separate the second electrodes 11c of different adjacent transistors, and a portion of the semiconductor substrate at the bottom of the second electrode 11c is heavily doped to form a signal line 2; then, as shown Figure 8c As shown, a dielectric material is filled between two adjacent signal lines 2; then, as shown Figure 8d As shown, a gate 12 of each transistor is formed.

[0085] Using heavily doped semiconductors as signal lines 2 can reduce the difficulty of the process and improve the area utilization of the semiconductor structure. However, the resistance of the signal line 2 will be very high, which will affect the parasitic impedance and signal transmission rate of the overall circuit; when the semiconductor structure is applied to a memory device, it will affect the read window of the memory device. This greatly affects the performance of the integrated circuit.

[0086] Based on this, some embodiments of the present application also provide a new semiconductor structure. Fig. 9 and Fig.10 The structure of a semiconductor structure is respectively shown.

[0087] like Fig. 9 and Fig.10 As shown, the semiconductor structure 610 includes a substrate 3, a signal line 2 and a transistor 1. The substrate 3 has a first surface A1, which is a plane. The signal line 2 is located on the first surface A1. The transistor 1 is located on the signal line 2 and is electrically connected to the signal line 2.

[0088] Exemplarily, the material of the substrate 3 includes, but is not limited to, one or more of silicon, germanium, silicon germanium, gallium nitride, gallium arsenide or other semiconductor materials. In addition, the material of the substrate 3 may also be, for example, glass, organic material or the like.

[0089] The number of the signal lines 2 is multiple, and the multiple signal lines 2 are arranged at intervals. Figures 9 to 11 The plurality of signal lines 2 extend along a first direction X and are spaced apart along a second direction Y. The first direction X and the second direction Y intersect and are parallel to the first surface A1.

[0090] The number of the transistors 1 is multiple, and the multiple transistors 1 are arranged at intervals. Figures 9 to 11 The plurality of transistors 1 are arranged in a plurality of rows and columns. The transistors 1 in the same row include a plurality of transistors 1 arranged in sequence along a first direction X, and the plurality of rows of transistors 1 are arranged in sequence along a second direction Y; the transistors 1 in the same column include a plurality of transistors 1 arranged in sequence along the second direction Y, and the plurality of columns of transistors 1 are arranged in sequence along the first direction X.

[0091] Optionally, the number of transistors 1 electrically connected to the same signal line 2 may be one or more. When the same signal line 2 is electrically connected to multiple transistors 1, the multiple transistors 1 may be located in the same column or in different columns. Fig.11 In the illustrated structure, there are a plurality of transistors 1 electrically connected to the same signal line 2, and the plurality of transistors 1 are located in the same column.

[0092] like Fig. 9 and Fig.10 As shown, the transistor 1 includes a semiconductor layer 11, which includes a first electrode 11b, a channel portion 11a, and a second electrode 11c stacked in sequence along a direction perpendicular to and away from the first surface A1 (i.e., a third direction Z). The second electrode 11c is located above the first electrode 11b, and the first electrode 11b is connected to the signal line 2. Among them, one of the first electrode 11b and the second electrode 11c is a drain, and the other is a source, which can be determined according to the type of the transistor 1.

[0093] The orthographic projection of the first pole 11b on the first surface A1, for example, coincides with the orthographic projection of the channel portion 11a on the first surface A1. Further, the orthographic projection of the channel portion 11a on the first surface A1, for example, coincides with the orthographic projection of the second pole 11c on the first surface A1. Further, the orthographic projections of the first pole 11b, the channel portion 11a, and the second pole 11c on the first surface A1, for example, coincide. This is conducive to reducing the area occupied by the semiconductor layer 11, thereby reducing the area occupied by the transistor 1, and improving the area utilization of the semiconductor structure 610.

[0094] Exemplarily, the material of the channel portion 11a includes, but is not limited to, silicon-based semiconductor materials such as silicon, silicon germanium, polycrystalline silicon, amorphous silicon, or oxide semiconductor materials such as indium gallium zinc oxide, or III-V compound semiconductor materials. The material of the first pole 11b includes a heavily doped semiconductor material, such as an N-type doped or P-type doped semiconductor material. The material of the second pole 11c includes a heavily doped semiconductor material, such as an N-type doped or P-type doped semiconductor material.

[0095] like Fig. 9 and Fig.10 As shown, the transistor 1 further includes a gate 12 and a gate dielectric layer 13. Along a direction perpendicular to the first surface A1, the gate dielectric layer 13 and the gate 12 are both located between the first electrode 11b and the second electrode 11c.

[0096] The gate dielectric layer 13 is located on one side of the channel portion 11a and surrounds the side of the channel portion 11a. For example, the gate dielectric layer 13 is tubular, sleeved on the channel portion 11a, and in contact with the channel portion 11a. The gate 12 is located on a side of the gate dielectric layer 13 away from the channel portion 11a. The gate 12 and the gate dielectric layer 13 are in direct contact, for example. The gate dielectric layer 13 is used to separate the gate 12 and the channel portion 11a to achieve electrical insulation between the gate 12 and the channel portion 11a. The gate 12 can be in contact with at least one side of the channel portion 11a. Optionally, the gate 12 surrounds the channel portion 11a.

[0097] It can be understood that the first pole 11b and the second pole 11c are arranged at intervals along the third direction Z, and the two are located in different layers. Moreover, along the third direction Z, the channel portion 11a is located between the first pole 11b and the second pole 11c. In this way, when the transistor 1 is turned on, the current between the first pole 11b and the second pole 11c flows along the third direction Z, and accordingly, the channel portion 11a can be called a vertical channel. The transistor 1 in the embodiment of the present application is a vertical channel transport transistor (vertical transportfield-effect transistor, VTFET), which can also be called a vertical pillar transistor (vertical pillartransistor, VPT). Compared with the transistor of the planar channel, the transistor 1 provided in the embodiment of the present application has a smaller positive projection area on the first surface A1, which can reduce the area occupied by the transistor 1 on the first surface A1 and improve the area utilization. Moreover, the transistor 1 provided in the embodiment of the present application has lower parasitic capacitance and stronger dynamic power consumption. This is also conducive to significantly improving the PPAC of the semiconductor structure 610 and the integrated circuit 600 used therein.

[0098] Continue reading Fig. 9 and Fig.10 The signal line 2 includes a wiring layer 21 and a first ohmic contact layer 22 which are sequentially stacked in a direction perpendicular to and away from the first surface A1. The first electrode 11b of the transistor 1 is located on the first ohmic contact layer 22. For example, the first electrode 11b is in direct contact with the first ohmic contact layer 22. The wiring layer 21 is mainly used to transmit electrical signals, and the first ohmic contact layer 22 is mainly used to form an ohmic contact with the first electrode 11b.

[0099] The material of the wiring layer 21 includes a metal material, which includes but is not limited to one or more of tungsten (W), copper (Cu), titanium nitride (TiN), ruthenium (Ru), molybdenum (Mo) or other metal materials. In this way, the wiring layer 21 can have a lower resistance and good conductivity, which is beneficial to reduce the resistance of the signal line 2 including the wiring layer 21 and improve the conductivity of the signal line 2.

[0100] The material of the first ohmic contact layer 22 includes a metal material, which includes but is not limited to one or more of nickel (Ni), titanium (Ti), cobalt (Co) or other metal materials. In this way, a good contact effect can be formed between the first ohmic contact layer 22 and the first electrode 11b, thereby reducing the contact resistance between the signal line 2 and the first electrode 11b.

[0101] The embodiment of the present application uses the first ohmic contact layer 22 and the routing layer 21 to form the signal line 2, which can make the signal line 2 have lower resistance and good conductivity, and can also form a good ohmic contact between the signal line 2 and the first electrode 11b.

[0102] It can be understood that the semiconductor layer 11 of the transistor 1 is connected to the first ohmic contact layer 22. That is to say, the signal line 2 is located below the semiconductor layer 11. This means that in the process of preparing and forming the semiconductor structure 610, the signal line 2 can be prepared first, and then the semiconductor layer 11 is formed, so that the signal line 2 and the first pole 11b form an ohmic contact. This process idea is different from the process idea of ​​first forming the semiconductor layer 11 and then forming the signal line 2 in the above-mentioned various implementations to make an ohmic contact, and can avoid the technical problems caused by the process ideas of the above-mentioned various implementations. On the one hand, the orthographic projection of the signal line 2 on the first surface A1 and the orthographic projection of the semiconductor layer 11 on the first surface A1 have overlapping parts. In this way, the signal line 2 and the transistor 1 can share part of the space, effectively reduce the area occupied by the signal line 2, and improve the area utilization of the semiconductor structure 610 and the integrated circuit 600. On the other hand, there is no need to etch to form a deep hole with a large depth-to-width ratio, and there is no need to etch the bottom of the semiconductor layer 11, which can reduce the process difficulty and process cost of the semiconductor structure 610 and improve the reliability of the semiconductor structure 610. On the other hand, the signal line 2 is a structure independent of the substrate 3. In the embodiment of the present application, the signal line 2 can be formed by using a metal material without etching the substrate 3 to form the signal line 2, which can effectively reduce the resistance of the signal line 2. In this way, when the semiconductor structure 610 is applied to a logic device, the parasitic impedance of the overall circuit can be reduced; when the semiconductor structure 610 is applied to a memory device, the impact on the read window of the memory device can be reduced, greatly improving the performance of the integrated circuit 600 to which the semiconductor structure 610 is applied.

[0103] Furthermore, if Fig. 9 and Fig.10 As shown, the maximum dimension of the orthographic projection of the transistor 1 on the first surface A1 in the first direction X is greater than the width of the signal line 2. That is, the signal line 2 and the transistor 1 are at different heights at the same position in the plane.

[0104] In this way, the signal line 2 does not occupy additional area, which is beneficial to further improve the area utilization of the semiconductor structure 610 and the integrated circuit 600 and improve the integration of the semiconductor structure 610 and the integrated circuit 600.

[0105] In some embodiments, Fig.10As shown, the semiconductor structure 610 further includes an anti-oxidation conductive layer 4. The anti-oxidation conductive layer 4 is located between the first ohmic contact layer 22 and the first electrode 11b, and the first electrode 11b is in contact with the anti-oxidation conductive layer 4. For example, the first electrode 11b is in direct contact with the anti-oxidation conductive layer 4.

[0106] The physical structure of the above-mentioned antioxidant conductive layer 4 is relatively loose. The antioxidant conductive layer 4 has, for example, pores, which may be linear or curved. The number of pores may be, for example, multiple, and the shapes of the multiple pores may be the same or different. Different pores may be connected or not connected. The arrangement of the pores may be determined according to the actual preparation process of the antioxidant conductive layer 4, and the embodiments of the present application do not limit this.

[0107] Exemplarily, the size of the above-mentioned pores is larger than the atomic diameter of the material of the first ohmic contact layer 22. The "size of the pores" refers to the size of the pores in the direction perpendicular to the extension direction of the pores. For example, if the pores are in the shape of through holes, the size of the pores is the aperture of the through holes. Optionally, in the case where the material of the first ohmic contact layer 22 includes nickel, the size of the pores in the anti-oxidation conductive layer 4 is larger than the diameter of nickel atoms. In the case where the material of the first ohmic contact layer 22 includes titanium, the size of the pores in the anti-oxidation conductive layer 4 is larger than the diameter of titanium atoms. In the case where the material of the first ohmic contact layer 22 includes cobalt, the size of the pores in the anti-oxidation conductive layer 4 is larger than the diameter of cobalt atoms. In the case where the material of the first ohmic contact layer 22 includes multiple metal materials, the size of the pores in the anti-oxidation conductive layer 4 is larger than the maximum value of the multiple metal atomic diameters.

[0108] The atoms of the material of the first ohmic contact layer 22 can move in the above-mentioned pores. Accordingly, the atoms of the material of the first ohmic contact layer 22 can move (or diffuse) from the upper surface of the first ohmic contact layer 22 through the pores in the anti-oxidation conductive layer 4 to the lower surface of the first electrode 11b. After the material of the first ohmic contact layer 22 diffuses to the first electrode 11b, it can react with the material of the first electrode 11b to form a metal silicide or other compound, so that the first ohmic contact layer 22 can form a good ohmic contact with the first electrode 11b through the anti-oxidation conductive layer 4.

[0109] The anti-oxidation conductive layer 4 has good conductivity, which can avoid affecting the contact resistance between the first ohmic contact layer 22 and the first electrode 11 b and the resistance of the signal line 2 .

[0110] The material of the anti-oxidation conductive layer 4 has high stability, so that the anti-oxidation conductive layer 4 is not easily oxidized. Therefore, the anti-oxidation conductive layer 4 also has good anti-oxidation performance. For example, the stability of the material of the anti-oxidation conductive layer 4 is higher than the stability of the material of the ohmic contact layer 22.

[0111] It is understandable that the first ohmic contact layer 22 can form a better ohmic contact with the first pole 11b than the wiring layer 21. However, compared with the wiring layer 21, the first ohmic contact layer 22 may be more easily oxidized. In other words, the stability of the material of the first ohmic contact layer 22 may be lower than the stability of the material of the wiring layer 21. In this way, before the first pole 11b is formed on the first ohmic contact layer 22, the first ohmic contact layer 22 may be exposed to the air and oxidized; or, in the process of depositing the semiconductor material on the first ohmic contact layer 22, it is oxidized due to heat. When the semiconductor material contacts the metal oxide, a Schottky barrier will be formed, which means that the contact resistance between the oxidized first ohmic contact layer 22 and the first pole 11b will be greatly increased, and affect the output characteristics of the transistor 1 and the electrical properties of the semiconductor structure 610.

[0112] In the embodiment of the present application, an anti-oxidation conductive layer 4 is provided between the first ohmic contact layer 22 and the first electrode 11b. The anti-oxidation conductive layer 4 can be used to protect the first ohmic contact layer 22, thereby reducing the risk of oxidation of the first ohmic contact layer 22 and avoiding affecting the contact resistance between the first ohmic contact layer 22 and the first electrode 11b, thereby avoiding affecting the output characteristics of the transistor 1 and the electrical properties of the semiconductor structure 610.

[0113] In some examples, along a direction perpendicular to the first surface A1 , the thickness of the anti-oxidation conductive layer 4 is less than the thickness of the routing layer 21 .

[0114] The thickness of the anti-oxidation conductive layer 4 is relatively small. Thus, on the basis of using the anti-oxidation conductive layer 4 to provide anti-oxidation protection for the first ohmic contact layer 22, the influence of the anti-oxidation conductive layer 4 on the contact resistance between the first ohmic contact layer 22 and the first electrode 11b can be reduced or even eliminated.

[0115] Exemplarily, the thickness of the anti-oxidation conductive layer 4 is at the nanometer level, and the thickness at different positions of the anti-oxidation conductive layer 4 is relatively uniform. The thickness of the anti-oxidation conductive layer 4 can be selected and set according to actual needs, so that the first ohmic contact layer 22 is basically not oxidized and the contact resistance between the first ohmic contact layer 22 and the first electrode 11b is basically not affected.

[0116] The orthographic projection relationship of the first electrode 11b, the anti-oxidation conductive layer 4, the first ohmic contact layer 22, and the wiring layer 21 on the first surface A1 includes various ones, which can be selected and set according to actual needs, and the embodiment of the present application does not limit this.

[0117] In some examples, combined Fig.10 and Fig.12The orthographic projection of the first electrode 11b on the first surface A1 is within the orthographic projection range of the anti-oxidation conductive layer 4 on the first surface A1. The orthographic projection area of ​​the first electrode 11b on the first surface A1 is smaller than the orthographic projection area of ​​the anti-oxidation conductive layer 4 on the first surface A1.

[0118] In the direction perpendicular to the first surface A1, at least part of the side surface of the anti-oxidation conductive layer 4 will exceed the side surface of the first electrode 11b, so that at least one side of the anti-oxidation conductive layer 4 will be arranged in a step-like manner with the first electrode 11b. Fig.10 In the embodiment, the left and right side surfaces of the anti-oxidation conductive layer 4 exceed the first electrode 11 b, so that the left and right sides of the anti-oxidation conductive layer 4 and the first electrode 11 b are arranged in a step shape.

[0119] There are many ways to set the above-mentioned anti-oxidation conductive layer 4. For example, the above-mentioned anti-oxidation conductive layer 4 is in a block shape. The anti-oxidation conductive layer 4 on the signal line 2 and the first electrode 11b of the transistor 1 are in contact with each other, for example, one by one. In the case where the signal line 2 is electrically connected to multiple transistors 1, for example, multiple anti-oxidation conductive layers 4 spaced from each other are also arranged on the signal line 2. For another example, the above-mentioned anti-oxidation conductive layer 4 is in a strip shape. In the case where the signal line 2 is electrically connected to multiple transistors 1, for example, at least one anti-oxidation conductive layer 4 is arranged on the signal line 2, and the same anti-oxidation conductive layer 4 is in contact with the first electrodes 11b of multiple transistors 1.

[0120] In this way, the anti-oxidation conductive layer 4 can be used to cover the portion of the first ohmic contact layer 22 opposite to the first pole 11b, thereby protecting the portion of the first ohmic contact layer 22 and preventing the portion of the first ohmic contact layer 22 from being oxidized, thereby affecting the ohmic contact between the portion of the first ohmic contact layer 22 and the first pole 11b.

[0121] In other examples, combined with Fig.10 , Fig.13 and Fig.14 The orthographic projection of the anti-oxidation conductive layer 4 on the first surface A1 coincides with the orthographic projection of the first ohmic contact layer 22 on the first surface A1. The orthographic projection area of ​​the anti-oxidation conductive layer 4 on the first surface A1 is equal to the orthographic projection area of ​​the first ohmic contact layer 22 on the first surface A1.

[0122] In the direction perpendicular to the first surface A1, the side of the anti-oxidation conductive layer 4 is flush with the side of the first ohmic contact layer 22. The anti-oxidation conductive layer 4 forms a relatively complete coverage of the first ohmic contact layer 22. The anti-oxidation conductive layer 4 and the first ohmic contact layer 22 are arranged in a one-to-one correspondence.

[0123] This can increase the area of ​​the anti-oxidation conductive layer 4 covering the first ohmic contact layer 22, enhance the protective effect of the anti-oxidation conductive layer 4 on the first ohmic contact layer 22, greatly reduce the area of ​​the first ohmic contact layer 22 exposed outside the anti-oxidation conductive layer 4, and greatly reduce the probability of the first ohmic contact layer 22 being oxidized, so that there can be a lower contact resistance between the first ohmic contact layer 22 and the first pole 11b.

[0124] In some other examples, combined with Fig.10 , Fig.12 and Fig.14 The orthographic projection of the first ohmic contact layer 22 on the first surface A1 coincides with the orthographic projection of the wiring layer 21 on the first surface A1. The orthographic projection area of ​​the first ohmic contact layer 22 on the first surface A1 is equal to the orthographic projection area of ​​the wiring layer 21 on the first surface A1.

[0125] In the direction perpendicular to the first surface A1, the side surface of the first ohmic contact layer 22 is flush with the side surface of the wiring layer 21. The first ohmic contact layer 22 forms a relatively complete coverage on the wiring layer 21. The wiring layer 21 and the first ohmic contact layer 22 are arranged in a one-to-one correspondence.

[0126] In this way, during the process of preparing the signal line 2, the conductive film where the wiring layer 21 is located and the conductive film where the first ohmic contact layer 22 is located can be synchronously etched in the same etching process to simultaneously form the first ohmic contact layer 22 and the wiring layer 21. This is conducive to simplifying the manufacturing process of the semiconductor structure 610 and improving the manufacturing efficiency of the semiconductor structure 610.

[0127] In some other examples, combined with Fig.10 and Fig.14 The orthographic projections of the anti-oxidation conductive layer 4, the first ohmic contact layer 22 and the wiring layer 21 on the first surface A1 overlap. The orthographic projections of the anti-oxidation conductive layer 4, the first ohmic contact layer 22 and the wiring layer 21 on the first surface A1 are equal.

[0128] In which, along the direction perpendicular to the first surface A1 , the side surface of the anti-oxidation conductive layer 4 , the side surface of the first ohmic contact layer 22 , and the side surface of the wiring layer 21 are flush.

[0129] In this way, in the process of preparing the signal line 2, the conductive film where the oxidation-resistant conductive layer 4 is located, the conductive film where the wiring layer 21 is located, and the conductive film where the first ohmic contact layer 22 is located can be synchronously etched in the same etching process, and the oxidation-resistant conductive layer 4, the first ohmic contact layer 22, and the wiring layer 21 are formed at the same time. This is conducive to further simplifying the preparation process of the semiconductor structure 610 and further improving the preparation efficiency of the semiconductor structure 610.

[0130] It is understandable that if Fig.10 and Fig.15 As shown, the second electrode 11c of the transistor 1 can also be electrically connected to other metal structures. In the case where the semiconductor structure 610 is applied to a logic device, such as Fig.10 As shown, the metal structure is, for example, a wiring, an interconnect structure, etc. When the semiconductor structure 610 is applied to a memory device, as shown in FIG. Fig.15 and Fig.16 As shown, the metal structure is, for example, a storage structure 5 .

[0131] For example, see Fig.15 The storage structure 5 includes but is not limited to a first electrode layer 51 and a second electrode layer 52 which are arranged opposite to each other, and a storage function layer 53 located between the first electrode layer 51 and the second electrode layer 52. The second electrode 11c of the transistor 1 is electrically connected to the first electrode layer 51. The storage structure 5 is used to store data.

[0132] In this case, the transistor 1 can be used as a selection transistor, and the storage structure 5 electrically connected to it constitutes a storage unit. There can be one or more storage structures 5 electrically connected to the same transistor 1. When the same transistor 1 is electrically connected to multiple storage structures 5, the multiple storage structures 5 are arranged in sequence, for example, along a direction perpendicular to the first surface A1.

[0133] There are many types of the storage function layer 53, and accordingly, there are many types of storage devices used in the semiconductor structure 610. The storage function layer 53 is mainly used to store data.

[0134] Exemplarily, the storage function layer 53 includes but is not limited to a high-k dielectric layer, a ferroelectric layer, a resistive layer, a phase change layer or a magnetic tunnel junction (MTJ).

[0135] Here, in the case where the storage function layer 53 includes a high-k dielectric layer, the type of the above-mentioned storage device may be a dynamic random access memory (DRAM). In the case where the storage function layer 53 includes a ferroelectric layer, the type of the above-mentioned storage device may be a random access memory (ferroelectric random access memory, FeRAM). In the case where the storage function layer 53 includes a resistive layer, the type of the above-mentioned storage device may be a resistive random access memory (resistive random access memory, RRAM). In the case where the storage function layer 53 includes a phase change layer, the type of the above-mentioned storage device may be a phase change random access memory (phase change random access memory, PCRAM). In the case where the storage function layer 53 includes a magnetic tunnel junction, the type of the above-mentioned storage device may be a magnetoresistive random access memory (magnetoresistive random access memory, MRAM).

[0136] It is understandable that the transistor 1 is a vertical structure transistor. When the semiconductor structure 610 is applied to a memory device, the projection area of ​​the transistor 1 on the first surface A1 is smaller, and more memory cells can be integrated on a unit area of ​​the substrate 3, thereby improving the storage density. Fig.17 As shown, a storage unit (such as Fig.17 As shown by the arrows in the figure, there are only 1F active area and 1F field area in the first direction X and the second direction Y respectively, and finally one storage unit occupies 2FX2F=4F 2 In this area, the advantage of increasing storage density is obvious. Fig.15 and Fig.16 In the embodiment, the signal line 2 can be used as a bit line BL, and the gates 12 of a plurality of transistors 1 in the same column can be connected to form a word line WL.

[0137] In some embodiments, Fig.15 As shown, the semiconductor structure 610 further includes a second ohmic contact layer 6. The second ohmic contact layer 6 is located on the second electrode 11c and contacts the second electrode 11c. For example, the second electrode 11c is in direct contact with the second ohmic contact layer 6. The second electrode 11c is electrically connected to the above-mentioned metal structure through the second ohmic contact layer 6.

[0138] The second ohmic contact layer 6 is mainly used to form an ohmic contact with the second electrode 11c. The material of the second ohmic contact layer 6 includes a metal material, which includes but is not limited to one or more of nickel, titanium, cobalt or other metal materials. In this way, a good contact effect can be formed between the second ohmic contact layer 6 and the second electrode 11c, reducing the contact resistance between the second ohmic contact layer 6 and the second electrode 11c.

[0139] Optionally, the material of the second ohmic contact layer 6 and the material of the first ohmic contact layer 22 may be the same or different.

[0140] The second ohmic contact layer 6 is provided to improve the contact performance between the second electrode 11 c and the other metal structures, thereby improving the electrical performance of the semiconductor structure 610 .

[0141] Some embodiments of the present application provide a method for preparing a semiconductor structure. The method is used, for example, to prepare a semiconductor structure 610 as described in any of the above embodiments. Fig.18 A flow chart of a method for preparing a semiconductor structure is illustrated; Figure 19a to Figure 19f A structural diagram corresponding to each step in a method for preparing a semiconductor structure is schematically shown; Figure 20a to Figure 20c The structure diagram corresponding to each step in another method for preparing a transistor is shown. It should be understood that Fig.18 The steps shown are not exclusive and can also be performed in Fig.18 Other steps may be performed before, after or between any of the steps shown. In addition, some of the steps may be performed simultaneously, or may be performed in different order. Fig.18 Executed in the order shown.

[0142] The following is a schematic illustration of the method for manufacturing a transistor in conjunction with the accompanying drawings. Fig.18 As shown, the preparation method includes: S100~S300.

[0143] S100, such as Fig.19a As shown, a substrate 3 is provided. The substrate 3 has a first surface A1.

[0144] The material of the substrate 3 can be found in the above related descriptions and will not be described again here.

[0145] S200, such as Fig.19b and Fig.19c As shown, a signal line 2 is formed on the first surface A1. The signal line 2 includes a wiring layer 21 and a first ohmic contact layer 22 which are sequentially stacked in a direction perpendicular to and away from the first surface A1.

[0146] Exemplarily, the method of forming the signal line 2 includes: Fig.19bAs shown, a metal deposition process (including but not limited to a sputtering process, etc.) is used to form a wiring film 21a on the substrate 3, and a first ohmic contact film 22a is formed on the wiring film 21a; then, as shown in FIG. Fig.19c As shown, an etching process (including but not limited to a photolithography process, a dry etching process, etc.) is used to etch the first ohmic contact film 22a and the routing film 21a to form a routing layer 21 and a first ohmic contact layer 22 located on the routing layer 21. Of course, according to different structures of the first ohmic contact layer 22, other preparation methods can also be used to form the routing layer 21 and the first ohmic contact layer 22.

[0147] The material of the wiring film 21a includes a metal material, which includes but is not limited to one or more of tungsten, copper, titanium carbide, ruthenium, molybdenum or other metal materials. The material of the first ohmic contact film 22a includes a metal material, which includes but is not limited to one or more of nickel, titanium, cobalt or other metal materials.

[0148] The configuration of the wiring layer 21 and the first ohmic contact layer 22 can be found in the above related descriptions and will not be described again here.

[0149] S300, such as Fig.19d and Fig.19e As shown, a semiconductor layer 11 is formed on the first ohmic contact layer 22. The semiconductor layer 11 includes a first electrode 11b, a channel portion 11a, and a second electrode 11c sequentially stacked in a direction perpendicular to and away from the first surface A1.

[0150] For example, the embodiment of the present application may adopt an epitaxial growth process, an etching process, etc. to form the first pole 11b, the channel portion 11a, and the second pole 11c on the first ohmic contact layer 22. Then, the environment in which the first ohmic contact layer 22 and the first pole 11b are located may be heated, so that the metal atoms in the first ohmic contact layer 22 can diffuse to the first pole 11b during the thermal process, react with the semiconductor material, and form a metal silicide or other compound, thereby forming an ohmic contact between the first ohmic contact layer 22 and the first pole 11b.

[0151] Optionally, before forming the semiconductor layer 11, Fig.19d As shown, in the embodiment of the present application, an insulating layer covering the signal line 2 may be first formed, and then an opening may be formed by etching at a preset position of the insulating layer to expose a portion of the first ohmic contact layer 22; then, as shown in FIG. Fig.19e As shown in FIG. 1 , a first electrode 11b is grown in the opening. After the semiconductor layer 11 is formed, Fig.19fAs shown, in the embodiment of the present application, a gate dielectric layer 13 can be first formed on the insulating layer, and the gate dielectric layer 13 covers the side of the channel portion 11a; then a gate 12 is formed on the side of the gate dielectric layer 13 away from the channel portion 11a to form a transistor 1.

[0152] Of course, the above preparation method is not limited thereto and can be adjusted according to actual needs.

[0153] After forming the transistor 1 and before forming other metal structures, a second ohmic contact layer may be formed on the second electrode 11 c .

[0154] It can be understood that the above-mentioned semiconductor layer 11 is formed above the signal line 2, that is, the transistor 1 is formed above the signal line 2, so that the signal line 2 and the transistor 1 are at different heights at the same position in the plane, thereby avoiding the signal line 2 occupying additional area, effectively improving the area utilization of the prepared semiconductor structure 610 and the integrated circuit 600, and improving the integration of the semiconductor structure 610 and the integrated circuit 600.

[0155] Moreover, in the above-mentioned various implementations, the process idea is to first form the semiconductor layer 11 and then form the signal line 2. However, the process idea of ​​the embodiment of the present application is to first form the signal line 2 and then form the semiconductor layer 11. The process idea of ​​the embodiment of the present application is different from the process ideas of the above-mentioned various implementations, which can avoid the technical problems caused by the process ideas of the above-mentioned various implementations. On the one hand, there is no need to etch to form a deep hole with a large depth-to-width ratio, and there is no need to etch the bottom of the semiconductor layer 11, thereby reducing the process difficulty and process cost of the semiconductor structure 610 and improving the reliability of the semiconductor structure 610. On the other hand, the signal line 2 in the embodiment of the present application is a structure formed of a metal material and independent of the substrate 3, rather than being formed by etching the substrate 3. Compared with using heavily doped semiconductor materials as signal lines, the resistance of the signal line 2 can be effectively reduced. In this way, when the semiconductor structure 610 is applied to a logic device, the parasitic impedance of the overall circuit can be reduced; when the semiconductor structure 610 is applied to a memory device, the impact on the read window of the memory device can be reduced, greatly improving the performance of the integrated circuit 600 to which the semiconductor structure 610 is applied.

[0156] In addition, after forming the signal line 2, the embodiment of the present application can start the preparation process flow of the transistor 1, which is compatible with the semiconductor back-end process, which is conducive to stacking and integrating the prepared semiconductor structure 610 to further improve the integration density.

[0157] In some embodiments, in combination Figure 20a to Figure 20cBefore the above S300, that is, before forming the semiconductor layer 11 on the first ohmic contact layer 22, the above preparation method further includes: forming an anti-oxidation conductive layer 4 on the first ohmic contact layer 22. The anti-oxidation conductive layer 4 has pores, and the size of the pores is larger than the atomic diameter of the material of the first ohmic contact layer 22; the anti-oxidation conductive layer 4 is in contact with the first electrode 11b.

[0158] For example, in the embodiment of the present application, a deposition process, a photolithography process, etc. can be used to form the anti-oxidation conductive layer 4 on the first ohmic contact layer 22. The physical structure of the formed anti-oxidation conductive layer 4 is relatively loose and has pores. For the structure of the above-mentioned "pores", please refer to the relevant description above, which will not be repeated here.

[0159] The stacked structure composed of the first ohmic contact layer 22 , the anti-oxidation conductive layer 4 , and the first electrode 11 b may be referred to as a sandwich structure.

[0160] In the sandwich structure, the stability of the material of the anti-oxidation conductive layer 4 is higher than that of the first ohmic contact layer 22. That is, the anti-oxidation performance of the anti-oxidation conductive layer 4 is higher than that of the first ohmic contact layer 22. The anti-oxidation conductive layer 4 is formed on the first ohmic contact layer 22, and the anti-oxidation conductive layer 4 can be used to cover and protect at least part of the first ohmic contact layer 22, so as to prevent the first ohmic contact layer 22 from being oxidized by air, or to prevent the semiconductor layer 11 from being oxidized by heat during the process of forming the semiconductor layer 11 on the first ohmic contact layer 22. In this way, the contact resistance between the first ohmic contact layer 22 and the anti-oxidation conductive layer 4 can be avoided from increasing, thereby avoiding affecting the output characteristics of the transistor 1 and the electrical properties of the semiconductor structure 610.

[0161] Moreover, the pores in the above-mentioned anti-oxidation conductive layer 4 can allow atoms of the material of the first ohmic contact layer 22 to move. At this time, the anti-oxidation conductive layer 4 can serve as a diffusion layer, so that atoms of the material of the first ohmic contact layer 22 can diffuse from the upper surface of the first ohmic contact layer 22 through the anti-oxidation conductive layer 4 to the lower surface of the first pole 11b, forming a good ohmic contact. Moreover, the anti-oxidation conductive layer 4 has good electrical conductivity. In this way, it is possible to avoid affecting the contact resistance between the first ohmic contact layer 22 and the first pole 11b, and avoid affecting the resistance of the signal line 2.

[0162] It is understandable that, depending on the structure of the anti-oxidation conductive layer 4, the anti-oxidation conductive layer 4 and the signal line 2 can be formed in the same etching process or in different etching processes. The embodiment of the present application is described by taking the anti-oxidation conductive layer 4 and the signal line 2 formed in the same etching process as an example.

[0163] In this case, if Fig.20a and Fig.20bAs shown, forming the signal line 2 and the anti-oxidation conductive layer 4 includes: S210-S220.

[0164] S210, such as Fig.20a As shown, a wiring film 21 a , a first ohmic contact film 22 a and an anti-oxidation conductive film 4 a are sequentially formed on the first surface A1 along a direction perpendicular to and away from the first surface A1 .

[0165] For example, the formation process and parameters of the anti-oxidation conductive film 4a can be selected and set according to actual needs, so that the physical structure of the prepared anti-oxidation conductive film 4a is relatively loose, and the atoms of the material of the first ohmic contact film 22a can be diffused. The thickness of the anti-oxidation conductive film 4a is small, and the thickness at different positions is relatively uniform.

[0166] Optionally, the routing film 21a, the first ohmic contact film 22a and the anti-oxidation conductive film 4a are formed in the same device to avoid exposing the first ohmic contact film 22a to air after the first ohmic contact film 22a is formed.

[0167] S220, such as Fig.20b As shown, the anti-oxidation conductive film 4a, the first ohmic contact film 22a and the wiring film 21a are etched synchronously to form the anti-oxidation conductive layer 4, the first ohmic contact layer 22 and the wiring layer 21. The orthographic projection of the anti-oxidation conductive layer 4 on the first surface A1, the orthographic projection of the first ohmic contact layer 22 on the first surface A1 and the orthographic projection of the wiring layer 21 on the first surface A1 overlap.

[0168] The anti-oxidation conductive layer 4, the first ohmic contact layer 22 and the wiring layer 21 are formed in the same etching process. On the one hand, the preparation process of the semiconductor structure 610 can be simplified; on the other hand, the first ohmic contact film 22a can be prevented from being exposed to the air, and before the semiconductor layer 11 is formed, the first ohmic contact layer 22 formed by etching can be more completely covered, which can greatly improve the protection effect of the first ohmic contact layer 22 and reduce the probability of the first ohmic contact layer 22 being oxidized, thereby greatly reducing the probability of the contact resistance between the first ohmic contact layer 22 and the first pole 11b being affected.

[0169] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present disclosure should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises: A substrate having a first surface; A signal line is located on the first surface; the signal line comprises a routing layer and a first ohmic contact layer stacked in sequence in a direction perpendicular to and away from the first surface; A transistor is located on the first ohmic contact layer; the transistor includes a semiconductor layer, and the semiconductor layer includes a first pole, a channel portion, and a second pole stacked in sequence in a direction vertical and away from the first surface.

2. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: an anti-oxidation conductive layer located between the first ohmic contact layer and the first electrode; the first electrode is in contact with the anti-oxidation conductive layer; The oxidation resistant conductive layer has pores, and the size of the pores is larger than the atomic diameter of the material of the first ohmic contact layer.

3. The semiconductor structure according to claim 2, characterized in that: The orthographic projection of the first electrode on the first surface is located within the range of the orthographic projection of the anti-oxidation conductive layer on the first surface.

4. The semiconductor structure according to claim 2 or 3, characterized in that: The orthographic projection of the anti-oxidation conductive layer on the first surface coincides with the orthographic projection of the first ohmic contact layer on the first surface.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: Along a direction perpendicular to the first surface, a thickness of the anti-oxidation conductive layer is less than a thickness of the routing layer.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that: The orthographic projection of the first ohmic contact layer on the first surface coincides with the orthographic projection of the routing layer on the first surface.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The semiconductor structure further includes: a second ohmic contact layer; The second ohmic contact layer is located on the second electrode and contacts the second electrode.

8. The semiconductor structure according to any one of claims 1 to 7, characterized in that: The transistor further comprises: A gate dielectric layer surrounding a side surface of the channel portion; The gate is located on a side of the gate dielectric layer away from the channel portion; along a direction perpendicular to the first surface, the gate dielectric layer and the gate are both located between the first pole and the second pole.

9. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises: Providing a substrate; the substrate having a first surface; forming a signal line on the first surface; the signal line comprises a wiring layer and a first ohmic contact layer stacked in sequence in a direction perpendicular to and away from the first surface; A semiconductor layer is formed on the first ohmic contact layer; the semiconductor layer includes a first electrode, a channel portion, and a second electrode sequentially stacked in a direction perpendicular to and away from the first surface.

10. The preparation method according to claim 9, characterized in that: Before forming a semiconductor layer on the first ohmic contact layer, the preparation method further includes: An anti-oxidation conductive layer is formed on the first ohmic contact layer; the anti-oxidation conductive layer has pores, the size of the pores is larger than the atomic diameter of the material of the first ohmic contact layer; the anti-oxidation conductive layer is in contact with the first electrode.

11. The preparation method according to claim 10, characterized in that: The signal line and the anti-oxidation conductive layer are formed, comprising: In a direction perpendicular to and away from the first surface, sequentially forming a wiring film, a first ohmic contact film and an anti-oxidation conductive film on the first surface; The anti-oxidation conductive film, the first ohmic contact film and the routing film are synchronously etched to form the anti-oxidation conductive layer, the first ohmic contact layer and the routing layer; the orthographic projection of the anti-oxidation conductive layer on the first surface, the orthographic projection of the first ohmic contact layer on the first surface and the orthographic projection of the routing layer on the first surface overlap.

12. An integrated circuit, characterized in that: The integrated circuit comprises: a packaging structure, and at least one semiconductor structure packaged inside the packaging structure; the semiconductor structure is the semiconductor structure according to any one of claims 1 to 8.

13. An electronic device, characterized in that: The electronic device comprises: a circuit board, and an integrated circuit connected to the circuit board; the integrated circuit is the integrated circuit as claimed in claim 12.

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