Integrated circuit with dielectric layer with selectively implanted stress setting dopant

Abstract

The invention relates to an integrated circuit with a dielectric layer having a selective implant stress setting dopant. An integrated circuit includes a dielectric layer over one or more metal interconnect layers. The dielectric layer includes selectively implanted stress setting dopant regions to provide different stress profiles in the dielectric layer to counteract stress applied by the package structure. Accordingly, the effect of stress applied by the package structure in the substrate can be counteracted by placing a stress setting dopant in a selective region of the dielectric layer.

Description

Technical Field

[0001] The present invention generally relates to integrated circuits having a dielectric layer with selectively implanted stress-setting dopant regions. Background Art

[0002] Integrated circuits utilize stressors to apply stress to the active areas of transistors to improve transistor performance. A stressor is a dielectric structure formed to induce stress (compressive or tensile) on the surrounding structures of the integrated circuit. A compressive stressor applies compressive stress on the structure directly below the compressive stressor. A compressive stressor is formed of a dielectric material (e.g., silicon nitride) and is under tensile stress when formed. A tensile stressor applies tensile stress on the structure directly below the tensile stressor. A tensile stressor is formed of a dielectric material (e.g., silicon nitride) and is under compressive stress when formed. Structures that are neither formed to apply compressive stress nor to apply tensile stress are characterized as neutral.

[0003] For some integrated circuits including field effect transistors (FETs), applying stress on the channel region can improve carrier mobility. Changing the carrier mobility can affect the drive current and threshold voltage of the transistor. For a specific semiconductor substrate with a given crystal orientation, the carrier mobility (e.g., electron mobility) in the channel region of an N-type FET (NFET) can be improved by applying tensile stress in both the longitudinal and lateral directions of the channel region. The longitudinal direction is the carrier flow direction in the channel region, and the lateral direction is transversely perpendicular to the carrier flow direction in the channel region. For a specific semiconductor substrate with a given crystal orientation, the carrier mobility (e.g., hole mobility) in the channel region of a P-type FET (PFET) can be improved by applying compressive stress on the channel in the longitudinal direction and applying tensile stress on the channel in the lateral direction. However, in the case of other transistors or substrates with different crystal orientations, channel stress may affect transistor performance in different ways. Summary of the invention

[0004] In one embodiment, an integrated circuit includes a substrate and one or more metal interconnect layers, the substrate including a semiconductor region for one or more semiconductor devices, the one or more metal interconnect layers including an electrical interconnect structure electrically coupled to the semiconductor region of the substrate. The integrated circuit includes a plurality of die terminals. Each die terminal is electrically coupled to the electrical interconnect structure of the one or more metal interconnect layers. The integrated circuit includes a dielectric layer located above the one or more metal interconnect layers. The dielectric layer includes a plurality of openings, wherein a conductive material resides in the openings of the plurality of openings and is electrically coupled to the electrical interconnect structure of the one or more metal interconnect layers. The dielectric layer includes a first region and a second region, the first region including a selectively implanted stress setting dopant, and the second region does not contain the selectively implanted stress setting dopant.

[0005] According to an example, the first region and the second region are each laterally closest to a first die end, wherein the first region is laterally closer to the first die end than the second region.

[0006] According to an example, the dielectric layer comprises nitride.

[0007] According to an example, the dielectric layer includes a third region including the selectively implanted stress-setting dopant.

[0008] According to an example, the selectively implanted stress-setting dopant in the first region provides a first stress profile for the first region, wherein the first region is under a first type of stress, and the selectively implanted stress-setting dopant implanted into the third region provides a second stress profile for the third region, wherein the second region is under a second type of stress opposite to the first type of stress.

[0009] According to an example, the selectively implanting stress-setting dopants provides a first stress profile for the first region, wherein the first region is under a stress greater in magnitude than the second region.

[0010] According to an example, the selectively implanted stress-setting dopant in the first region has a first kind of dopant, wherein a concentration of the first kind of dopant in the first region is at least five atomic percent greater than a concentration of the first kind of dopant in the second region.

[0011] According to an example, the first species comprises one of the group consisting of: xenon, boron, phosphorus, oxygen, argon, nitrogen, hydrogen, helium, fluorine, germanium and silicon.

[0012] According to an example, the selectively implanting stress-setting dopants provides a first stress profile to the first region, and wherein the second region has a second stress profile different from the first stress profile.

[0013] According to an example, the first region is positioned closest to a first die end of the plurality of die ends, wherein a concentration of stress-setting dopants in a first portion of the first region is higher than a concentration of stress-setting dopants in a second portion of the first region, wherein the second portion is positioned laterally further away from the first die end than the first portion.

[0014] According to an example, the dielectric layer is characterized as a passivation layer.

[0015] In another embodiment, a packaged integrated circuit includes the aforementioned integrated circuit.

[0016] In another embodiment, an integrated circuit includes: a substrate including a semiconductor region for one or more semiconductor devices; one or more metal interconnect layers including an electrical interconnect structure electrically coupled to the semiconductor region of the substrate; and a dielectric layer located above the one or more metal interconnect layers. The dielectric layer includes a plurality of openings, wherein a conductive material resides in the openings of the plurality of openings and is electrically coupled to the electrical interconnect structure of the one or more metal interconnect layers. The dielectric layer has a first region and a second region. The second region is directly transverse to the first region, wherein a concentration of a first type of dopant in the first region is at least five atomic percent greater than a concentration of the first type of dopant in the second region.

[0017] According to an example, the dielectric layer comprises a third region comprising a selectively implanted stress-setting dopant of at least one of the group consisting of a different kind and a different concentration than the first kind of dopant in the first region.

[0018] According to an example, the first kind of dopant in the first region provides a first stress distribution for the first region, wherein the first region is under a first type of stress, and the selectively implanted stress-setting dopant implanted into the third region provides a second stress distribution for the third region, wherein the third region is under a second type of stress opposite to the first type of stress.

[0019] According to an example, the dielectric layer is characterized as a passivation layer.

[0020] According to an example, the first species comprises one of the group consisting of: xenon, boron, phosphorus, oxygen, argon, nitrogen, hydrogen, helium, fluorine, germanium and silicon.

[0021] According to an example, the first kind of dopant provides a first stress profile to the first region, and wherein the second region has a second stress profile different from the first stress profile.

[0022] In another embodiment, a packaged integrated circuit includes the aforementioned integrated circuit.

[0023] In another embodiment, a method includes forming a semiconductor region for a semiconductor device in a substrate; and forming one or more metal interconnect layers above the substrate. The one or more metal interconnect layers include an electrical interconnect structure electrically coupled to the semiconductor region of the substrate. The method includes forming a plurality of die terminals, wherein each die terminal is electrically coupled to the electrical interconnect structure of the one or more metal interconnect layers. The method includes: forming a dielectric layer located above the one or more metal interconnect layers; and selectively implanting a stress-setting dopant into a first region of the dielectric layer, wherein a second region of the dielectric layer is masked from being implanted with the stress-setting dopant. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0025] Figure 1 is a partial cross-sectional side view of a prior art integrated circuit.

[0026] Figure 2 is a top view of a prior art integrated circuit illustrating how die end stress affects different areas of the substrate.

[0027] Figure 3 is a partial cross-sectional side view of a wafer during a stage in its fabrication in accordance with one embodiment of the present invention.

[0028] Figure 4 is a partial cross-sectional side view of a wafer during another stage of its fabrication in accordance with one embodiment of the present invention.

[0029] Figure 5 is a cross-sectional side view of a packaged integrated circuit in accordance with one embodiment of the present invention.

[0030] Figure 6 is a partial top view of a passivation layer according to an embodiment of the present invention.

[0031] Figure 7 is a partial top view of a passivation layer according to another embodiment of the present invention.

[0032] Figure 8 is a partial top view of a passivation layer according to another embodiment of the present invention.

[0033] Fig. 9 is a partial top view of a passivation layer according to another embodiment of the present invention.

[0034] Fig.10is a flow chart of a method for manufacturing a packaged integrated circuit according to one embodiment of the present invention.

[0035] Unless otherwise indicated, the same reference numerals are used in different drawings to indicate the same items. The drawings are not necessarily drawn to scale. DETAILED DESCRIPTION

[0036] The following is a detailed description of at least one mode for carrying out the invention. This description is intended to illustrate the invention and should not be considered limiting.

[0037] As disclosed herein, an integrated circuit includes a dielectric layer located above one or more metal interconnect layers. The dielectric layer includes a selectively implanted stress setting dopant region to provide a different stress distribution in the dielectric layer to offset the stress applied by the packaging structure. Thus, the effect of the stress applied by the packaging structure in the substrate can be offset by placing the stress setting dopant in the selective region of the dielectric layer.

[0038] Figure 1 is a partial cross-sectional side view of a prior art integrated circuit 101 . Figure 1 PFET 103 and NFET 105 are shown, each including an active region located in substrate 107 . Figure 1 Not shown in Figure 1 1. The PFET 103 includes a gate 121 located above an active region positioned between shallow trench isolation (STI) structures 117 and 119, and also includes a P-type source region 128, a P-type drain region 129, and an N-type well (N-well) region 109. When a voltage lower than the threshold voltage of the PFET 103 is applied to the gate 121, a conductive channel region 125 is formed between the source region 128 and the drain region 129 in the well region 109 directly below the gate 121.

[0039] NFET 105 includes a gate 123 located over an active region positioned between shallow trench isolation structures 119 and 120, which includes an N-type source region 138, an N-type drain region 139, and a P-type well (P-well) region 111. When a voltage higher than the threshold voltage of NFET 105 is applied to gate 121, a conductive channel region 135 is formed between source region 138 and drain region 139 in well region 111.

[0040] Compressive stressor 131 is located directly above PFET 103 and is made of a patterned silicon nitride layer under tensile stress. Stressor 131 applies a desired amount of compressive stress on channel region 125 in the direction of carrier flow to increase carrier flow during transistor conduction.

[0041] Tensile stressor 133 is located directly above NFET 105 and is made of a patterned silicon nitride layer under compressive stress. Stressor 133 applies a desired amount of tensile stress in channel region 135 in the direction of carrier flow to increase carrier flow during transistor conduction.

[0042] The stressors 131 and 133 are configured (e.g., size, location, thickness, and amount of internal stress) to exert a desired amount of stress on the channel region to improve carrier mobility in the transistor. However, other packaging structures (eg, Figure 1 ), such as metal interconnect structures in the die interconnect layer, external die ends (eg, bonding pads, pillars, bumps), metal plates, solder, package plates, and package encapsulation (see Figure 5 ), stress may also be applied to the channel region, which may offset or increase the stress provided by stressors 131 and 133, such that the desired amount of stress is not provided to the channel region. In addition, the stress caused by the packaged structure is not necessarily uniform across the integrated circuit, but may depend on the distance of the package structure to the channel region. Because the compressive stressor can be patterned from a single layer and the tensile stressor can be patterned from a single layer, the parameters that give the layer the desired stress cannot be changed to account for changes in the package structure stress due to position. Therefore, transistor mobility may vary based on the transistor position in the integrated circuit. Such changes in carrier mobility may result in changes in drive current and voltage thresholds based on transistor position. Such changes are undesirable for proper integrated circuit operation.

[0043] Figure 2 2 is a top view of integrated circuit 201 showing regions of stress variation on the channel region due to external die terminals (e.g., bond pads, pillars, bumps, studs). In one embodiment, such stress may occur due to a mismatch in thermal expansion coefficients between the die terminals and the laminate. Figure 2 The smaller identified areas (e.g., 203) in the diagram represent the approximate locations of the outer die ends, where the greatest amount of stress affects the channel regions of the transistors in those areas. The area 205 surrounding the smaller areas represents an area of ​​moderate stress from the outer die ends. Figure 2 As shown, the stress caused by the die end tends to decrease as the distance from the end increases. The stress of the external die end includes not only the stress applied by the die end structure itself, but also the stress from other packaging structures mechanically coupled to the end. Moreover, the amount of stress applied by the die end can depend on the position of the die end. For example, compared with the internal die end, the corner die end can apply greater stress on the substrate.

[0044] In some embodiments, the stress applied to the substrate may be compressive. In other embodiments, the stress may be tensile. In still other embodiments, the stress may be compressive just below the die end and tensile in the region radiating outward from the die end. In still other embodiments, the stress may be tensile in one direction and compressive in a second direction.

[0045] In some embodiments, the copper pillar die end can impose a threshold voltage shift from -1.3 to 0.4 mV (millivolts) on a FET having a channel in a substrate. In some embodiments, the relationship between the threshold voltage shift and stress can be characterized as 30 mV / 0.12 GPa.

[0046] In addition, the stress caused by the package structure may affect the operability of other semiconductor devices (e.g., diodes, bipolar transistors) including semiconductor regions in the substrate. In addition, such package structure stress may cause tension in the package, which may affect package durability (e.g., delamination, corrosion, cracking).

[0047] Some integrated circuits may utilize a semiconductor device keep-out zone beneath the die end as a way to avoid the effects of stress applied by the die end. However, as the area of ​​integrated circuits decreases, utilizing a keep-out zone may be impractical.

[0048] As described herein, utilizing stress-setting dopants in selective regions of a dielectric layer (eg, a passivation layer) located above one or more metal interconnect layers can alter the stress profile of the dielectric layer to counteract the effects of stress induced by a packaging structure on a semiconductor region of a substrate.

[0049] Figure 3 301 during its manufacturing stage according to an embodiment of the present invention. Wafer 301 includes a substrate 303 made of one or more semiconductor materials, such as single crystal silicon, silicon germanium, silicon carbide, gallium nitride, gallium arsenide or other III-V semiconductor materials. In one embodiment, substrate 303 has a bulk semiconductor configuration. In other embodiments, substrate 303 may have an SOI (semiconductor on insulator) configuration. In some embodiments, substrate 303 is formed by a single portion of a semiconductor material grown integrally. In other embodiments, portions of substrate 303 may include epitaxially grown semiconductor materials. Substrate 303 may also include dielectric structures (e.g., shallow trench isolation structures, buried oxide layers (not shown)).

[0050] The substrate 303 includes semiconductor regions for a plurality of semiconductor devices (eg, transistors, diodes) of the integrated circuit. Figure 3FET 307 (PFET or NFET) is shown including source region 308 and drain region 310 located in substrate 303. In the embodiment shown, FET 307 is a planar transistor. However, in other embodiments, substrate 303 will include semiconductor regions for other types of transistors, such as bipolar transistors, JFETs (junction field effect transistors) and FinFETs (not shown), stacked transistors, nanotubes, and multi-sheet transistors, as well as semiconductor regions for other types of semiconductor devices, such as diodes (not shown).

[0051] Wafer 301 includes an interconnect layer 305 located above substrate 303, the interconnect layer 305 including conductive interconnects (323) and vias (321), and including an intermediate dielectric material 309 that provides electrical isolation of these conductive structures. The conductive structures of interconnect layer 305 provide conductive paths between semiconductor device terminals and conductive paths from the terminals to circuitry external to integrated circuit 301 (not shown).

[0052] exist Figure 3 In the embodiment of the present invention, the electrical interconnects of layer 305 are implemented in four metal interconnect layers 341-344. The metal interconnect layers of the integrated circuit are layers that include one or more electrical interconnects that provide conductive lateral paths in the layer and include intra-layer dielectric materials (part of dielectric material 309) that laterally isolate the interconnects in the layer. For example, metal interconnect layer 342 includes electrical interconnect 323, and top metal interconnect layer 344 includes electrical interconnect 325. The electrical interconnects are made of conductive materials (e.g., copper, aluminum, gold) and may include conductive barrier layers (e.g., titanium and titanium nitride).

[0053] Interlayer dielectric material (part of dielectric material 309) is located between metal interconnect layers 341-344 for electrical isolation. Conductive vias (313) located in the interlayer dielectric material provide a conductive path between interconnects of different metal interconnect layers. For example, conductive via 322 provides a conductive path from interconnect 329 of layer 343 to interconnect 323 of layer 342. In the illustrated embodiment, the interconnects of different metal layers have different thicknesses, and the metal interconnect layers have different spacings between layers. Although Figure 3 Four metal interconnect layers are shown in FIG. 1 , but other embodiments may include a different number of metal interconnect layers.

[0054] In some embodiments, the metal interconnect layer and vias are formed by forming openings in a dielectric layer (e.g., oxide) of material 309, depositing a conductive metal (e.g., copper, aluminum, gold) in the openings, and then planarizing the wafer. In other embodiments, the interconnects may be formed by depositing a metal layer on the dielectric material layer 309 and then patterning the metal layer. In some embodiments, the conductive interconnects and underlying vias may be formed by a dual damascene process. In some embodiments, the interconnects and vias may include a barrier layer (not shown) such as titanium and titanium nitride.

[0055] A passivation layer 331 is formed over layer 305. A passivation layer is one of one or more dielectric layers that protects the integrated circuit from chemical contamination, such as corrosion, that may occur during a subsequent packaging process or from another packaging structure. In one embodiment, the passivation layer 331 is made of nitride and has a thickness of 20 Å, but in other embodiments may have other thicknesses (e.g., 5-5000 Å), be made of other materials, and / or be formed by other processes. For example, in some embodiments, layer 331 may be made of silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxide, silicon dioxide, or a polymer. In some embodiments, the passivation layer 331 may be made of multiple layers of different passivation materials. For example, the passivation layer 331 may include a silicon dioxide layer, a silicon oxynitride layer, and a silicon nitride layer.

[0056] In the illustrated embodiment, stress setting dopants are selectively implanted into layer 331 at regions 333 and 335 to modify the stress profile of layer 331 at regions 333 and 335 to compensate for stress from packaging structures, such as subsequently formed die end structures ( Figure 4 Columns 403 and 405), encapsulating agent ( Figure 5 503 in), packaging board ( Figure 5 505) and packaging pads ( Figure 5 507).

[0057] In the illustrated embodiment, region 333 is located in region 304 of wafer 301, which region 304 will be located in a portion of an integrated circuit package where substrate 303 will be under compressive stress due to stress caused by the packaging structure. In order to counteract the compressive stress imposed in substrate 303 by the packaging structure in region 304, region 333 will be implanted with stress-setting dopants so that region 333 will be under compressive stress to impose tensile stress on region 304 of substrate 303, thereby neutralizing the effect of the compressive stress imposed by the packaging structure. Thus, the net stress effect on region 306 in substrate 303 will be neutral, or at the level of stress caused by a stressor located closer to the substrate (e.g., see FIG. 1 ). Figure 1The desired stress level and type set by the stress sources 131 and 133).

[0058] In one embodiment where layer 331 is made of silicon nitride, by 13 To 5e 15 Atom / cm 2 The nitrogen dopant is selectively implanted into the region 333 at a dose of 0.8 to 10 keV and an energy of 0.8 to 10 keV to place the region 333 under compressive stress, while the other portions of the masking layer 331 ( Figure 3 The mask is not shown in Figure 3 to prevent implantation of dopants or implant damage in these areas (e.g., in regions 334 and 335 of layer 331). However, other types of dopant species (e.g., xenon, boron, phosphorus, oxygen, argon, hydrogen, helium, fluorine, germanium, and / or silicon) may be used at sufficient doses to compress region 333. The specific dose and energy will depend on the species, the type of passivation film, and its intrinsic residual stress. For most species, a relatively high dose implant will cause the region to become compressed due to the heating caused by the high dose implant.

[0059] In the illustrated embodiment, region 335 is located in region 306 of wafer 301, which will be located in a portion of an integrated circuit package where substrate 303 will be under tensile stress due to stress caused by the package structure. To counteract the tensile stress applied by the package structure in region 306, region 335 will be implanted with stress-setting dopants so that region 335 will be under tensile stress to apply compressive stress on region 306 of substrate 303, thereby neutralizing the effect of the tensile stress applied by the package structure.

[0060] In one embodiment where layer 331 is made of silicon dioxide, by 13 / cm 2 The dose and energy of 4MeV will convert Xe +4 Dopants are implanted into region 335 to place region 335 under tensile stress while masking other portions of layer 331 to prevent implantation of dopants into those regions. However, other types of dopant species may be used, for example, xenon, boron, phosphorus, oxygen, argon, hydrogen, helium, fluorine, germanium and / or silicon. The specific dose and energy will depend on the species, the type of passivation film and its intrinsic residual stress. For most species, implantation at a relatively low dose will cause the region to become tensile. For most species, the dose used to stretch the layer is less than the dose used to compress the layer.

[0061] In some embodiments where layer 331 is a multi-layer passivation layer, the stress-setting dopant may be implanted into less than all layers of the passivation layer. For example, in an embodiment where passivation layer 331 is composed of a silicon dioxide layer and a silicon nitride layer (e.g., Si 3 N 4) layer, the dopants can be implanted into the silicon dioxide layer instead of the silicon nitride layer to place region 335 under tensile stress, and implanted into the silicon nitride layer instead of the silicon dioxide layer to place region 333 under compressive stress.

[0062] In the illustrated embodiment, other portions of layer 331 (e.g., regions 334) are not implanted with stress-setting dopants. However, in some embodiments, these regions may include dopants of the same species as the implanted dopants but at significantly lower concentrations. For example, the concentration of regions implanted with one species of stress-setting dopants to adjust the doping profile will be at least five atomic percent greater than the concentration of regions not implanted with stress-setting dopants.

[0063] After the stress-setting dopants have been implanted, a low temperature anneal is performed (eg, 350-400 C). In some embodiments, another anneal will be performed to repair ion implantation damage.

[0064] In one embodiment, the implantation of the stress-setting dopant is performed by an ion implantation process. In other embodiments, the implantation of the stress-setting dopant is performed by a plasma immersion implantation process. In one embodiment, the plasma implantation process can be performed with equipment that is less expensive than equipment used to perform the ion implantation process.

[0065] In the illustrated embodiment, both a region under compressive stress (region 333) and a region under tensile stress (region 335) are formed in the passivation layer 331. However, in some embodiments, only tensile regions or only compressive regions are formed in the passivation layer.

[0066] Figure 4 is a partial cross-sectional side view of wafer 301 after the addition of pillars 403 and 405. Figure 3 After the stage of , opening 411 is formed in region 333 to expose interconnect 329, and opening 421 is formed in region 335 to expose interconnect 325. Thereafter, a layer of barrier material (e.g., titanium or titanium nitride) is formed over wafer 301 (including in openings 411 and 421) to contact interconnects 329 and 325, followed by a layer of aluminum, and then another layer of barrier material. The three layers (barrier, aluminum, and barrier) are then patterned to form a liner including barrier layer portion 412, aluminum portion 413, and barrier layer portion 414 in region 304, and a liner including barrier layer portion 422, aluminum portion 423, and barrier layer portion 424 is formed in region 306.

[0067] A second passivation layer 401 is formed over wafer 301. Openings are then formed in layer 401 to expose barrier layer portions 414 and 424. Copper pillar portions 415 and 425 of pillars 403 and 405, respectively, are then formed in the openings (e.g., by plating). Solder caps 417 and 427 are formed on portions 415 and 425, respectively. In other embodiments, pillars 403 and 405 may be formed by other methods, have other configurations, and / or be made of other materials in other embodiments. Other embodiments of integrated circuits may utilize other types of die terminals, such as bonding pads, pillars, or bumps.

[0068] Figure 5 4 is a cross-sectional side view of a packaged integrated circuit 501 according to one embodiment of the present invention. After forming pillars 403 and 405, wafer 301 is singulated into a plurality of integrated circuits including integrated circuit 502, wherein each integrated circuit includes a plurality of semiconductor devices. Integrated circuit 502 includes a semiconductor device located on one side of integrated circuit 502 (e.g., Figure 5 509). The integrated circuit 502 is encapsulated in the encapsulant 503. In other embodiments, other integrated circuit packages may have other structures or packaging configurations. For example, in some embodiments, the packaged integrated circuit may be oriented so that the die ends, such as bonding pads, face upward and include wire bonds (not shown). In other embodiments, the packaged integrated circuit may include a lead frame (not shown).

[0069] In addition to the stress caused by the pillars (403 and 405), stress may also be generated on the substrate of the integrated circuit 502 by the package board 505, the package pad 507 and the solder 508 through the pillars and the encapsulant 503. Therefore, selectively implanting stress-setting dopants into the passivation layer 331 can tune the stress induced in the channel region to adjust the package structure stress that may be position-dependent.

[0070] In some embodiments, the stress effects of the die end and other packaging structures decrease laterally from the die end. Therefore, to compensate for this reduction in stress from the die end, the concentration of the stress-setting dopant can decrease as the lateral distance from the die end decreases.

[0071] Figure 6 It is the passivation layer 601 of the integrated circuit (similar to Figure 3331 in FIG. 3 ) showing a stress setting dopant implant region 605 positioned relative to a location 603 of a subsequently formed die end. Other portions of the layer 601 shown are not implanted with stress setting dopants. Figure 6 In an embodiment of the present invention, doped region 605 has a flower shape with petals radiating outward from a center, such that the net concentration of dopants at equal distances from location 603 decreases with lateral distance. With such a configuration, the stress applied by region 605 decreases with decreasing lateral distance from location 603 to match the decrease in stress effects at the die end with increasing lateral distance from the die end.

[0072] Figure 7 7 is a top view of the passivation layer 701 showing stress setting dopant implant regions 705, 707 and 709 positioned relative to a location 703 of a subsequently formed die end. Other portions of the layer 701 are shown without being implanted with stress setting dopants. Figure 7 In the embodiment of implantation region 705, implantation region 705 has a circular shape, and regions 707 and 709 have annular shapes, the radial thickness of which and the spacing from adjacent annular regions decrease with increasing lateral distance from position 703. Figure 7 In the case of a design of , due to the reduction in thickness and area, the amount of stress applied by the region decreases with lateral distance from location 703. In other embodiments, the implant ring region may have a non-circular shape or may be split into segments.

[0073] Figure 8 8 is a top view of the passivation layer 801 showing a plurality of stress setting dopant implant regions 805, 807 and 811 positioned relative to a location 803 of a subsequently formed die end. Other portions of the layer 801 are shown without being implanted with stress setting dopants. Figure 8 805 has a circular shape. Region 807 is a smaller doped region surrounding region 805. Region 811 is an even smaller doped region surrounding region 807. With this configuration, the net concentration of stress-setting dopants decreases laterally from location 803, such that the stress applied by the doped regions decreases with increasing lateral distance from location 803. Other embodiments may include other spatial patterns in which the size and density of stress-setting dopant regions decreases with decreasing distance from the location at the die end.

[0074] like Figure 6-8 As shown, all doped regions have the same stress setting dopant concentration. However, because the total area of ​​implantation decreases with increasing lateral distance from the location of the die end, the net concentration of dopants implanted in the passivation layer decreases with increasing lateral distance from the location of the die end. Figure 6-8In the case of , a net concentration reduction can be achieved by using only one mask (not shown) for the selective dopant implantation by reducing the total area implanted with increasing lateral distance from the die end.

[0075] Fig. 9 Another embodiment of a top view of a passivation layer 901 is shown, wherein the net concentration of dopants implanted in the passivation layer decreases with increasing lateral distance from a location 903 of the die end. Fig. 9 In the embodiment of FIG. 1 , implant regions 909, 907, and 905 have different dopant concentrations, with region 905 having the highest concentration, region 907 having the next highest concentration, and region 909 having the lowest concentration. Other portions of layer 901 are shown not doped with stress-setting dopants. Fig. 9 In an embodiment of the present invention, regions 905, 907, and 905 are implanted using multiple implant steps using different masks to achieve different concentration levels. In one embodiment, a first mask having an opening in the shape of the outer perimeter of region 909 is formed over layer 901, wherein the stress-setting dopant is implanted in the opening at a final concentration of region 909. A second mask is formed over layer 901, the second mask having an opening in the shape of the outer perimeter of region 907. The second implant is performed at a dopant concentration of the final concentration of region 907 minus the final concentration of region 909 (the concentration of the previous implant process). A third mask is formed over layer 901, the third mask having an opening in a shape defined by the outer perimeter of region 905. The third implant is performed at a dopant concentration of the final concentration of region 905 minus the final concentration of region 907 (the concentration of the previous two implant processes).

[0076] exist Figure 6-9 In the embodiments of FIG. 1 , the net doping concentration is shown as symmetrical about the die tip location. However, the implanted region may be adjusted to account for asymmetric stress effects at the die tip. In some embodiments, a region of the substrate may be subject to stress from multiple die tips. Thus, the net amount of stress setting dopant implanted into the region may be adjusted to compensate for stress in the substrate from multiple sources. For example, referring back to FIG. Figure 2 , the selectively doped regions can be chosen to match the location, magnitude, and type (eg, tensile or compressive) of stress applied by the package structure at a particular location.

[0077] Fig.10 1 is a flow chart illustrating a method 1001 for designing and manufacturing a packaged integrated circuit according to one embodiment of the present invention. The method 1001 begins by generating a desired channel stress profile for transistors (and other semiconductor devices) of the integrated circuit in operation 1003. In one embodiment, for each transistor, the desired channel stress profile generated is based on the conductivity type of the transistor (e.g., N-type or P-type), the size of the transistor, and the desired drive current of the transistor.

[0078] In operation 1005 , a distribution of cumulative stress effects of a package structure on a substrate of an integrated circuit is generated. The distribution indicates cumulative package structure stress at each channel position of the integrated circuit. In one embodiment, operation 1005 may be performed before operation 1003 .

[0079] At operation 1007, locations of stress-setting dopants in the passivation layer or other dielectric layer are determined based on the desired stress profile generated in operation 1003 and the package structure stress profile generated in operation 1005. In one embodiment, the locations are selected to provide the desired stress in the channel of each transistor, thereby compensating for the package stress on the channel at each location. The planning is implemented in a wafer mask set and process recipe for a wafer used to manufacture the integrated circuit. Operations 1003, 1005, and 1007 can be performed using a computer-aided design (CAD) tool for integrated circuit design.

[0080] In operation 1009, integrated circuits are fabricated to have stress-setting dopant implants in selected regions. In one embodiment, semiconductor devices, overlying metal interconnect layers, and die terminations are formed on a wafer, which is then singulated to form a plurality of integrated circuits. In operation 1011, the integrated circuits are packaged to form packaged integrated circuits. In other embodiments, integrated circuits having selectively implanted stress-setting dopant regions may be designed and / or fabricated by other processes.

[0081] As described above, the stress setting dopant is implanted into the passivation layer (e.g., 331). However, the dopant may be implanted into other dielectric layers to control stress. For example, the stress setting dopant may be implanted into other passivation layers (e.g., passivation layer 401) and / or into at least one or more dielectric layers of the interconnect layer 305 to counteract the stress of the package structure.

[0082] Providing an integrated circuit having a selectively implanted stress-setting dopant region in a dielectric layer above one or more metal interconnect layers can provide a mechanism for counteracting stresses applied by a packaging structure. In addition, such an approach can allow packaging stress compensation to occur at higher levels of the IC, making the compensation independent of the substrate and lower level designs. For example, because stress compensation occurs at upper integrated circuit levels (e.g., at a passivation layer), it is not necessary to modify substrate processing operations and etch stop processing operations used to form the integrated circuit to change the packaging structure that applies stress to the substrate.

[0083] Providing an integrated circuit with selectively implanted stress-setting dopant regions above one or more metal interconnect layers may also allow the stress of a channel region of the integrated circuit to be individually adjusted at different locations of the integrated circuit. Thus, in some embodiments, the location of the stress-setting dopant in the passivation layer (or other upper dielectric layer) may be used to adjust the stress of the channel region to a stress beyond that required to offset the package stress, to further improve transistor performance.

[0084] Thus, in some embodiments, the use of selective implant regions in a dielectric layer above one or more metal interconnect layers may allow for the reduction or elimination of the use of stressors (eg, stressors 131 and 133 ) located on the substrate.

[0085] In addition, stress setting dopants may also be used to counteract package structural stress at other locations of the IC and / or locations of the packaged integrated circuit. This stress reduction may be beneficial to the integrated circuit package integrity.

[0086] The source and drain regions are the current terminal regions of the FET, and the gate is the control terminal of the FET. The stress distribution of a region or structure defines the type of stress (tensile or compressive) to which the region or structure is subjected and the magnitude of the stress. The active region of a transistor includes the regions in the substrate of semiconductor material for the terminals of the transistor (e.g., the current terminals and the control terminals if present in the substrate) and the semiconductor paths that conduct carriers between the terminals of the transistor. For a FET, the active region will include the source region, the drain region, and the channel region.

[0087] As disclosed herein, a first structure is "directly above" a second structure if the first structure is above the second structure on a line having a direction perpendicular to the generally planar major side of the wafer or substrate. Figure 4 , pillar portion 425 is directly above interconnect 325. Pillar portion 425 is not directly above transistor 307. As disclosed herein, a first structure is “directly below” or “directly under” a second structure if the first structure is below the second structure on a line having a direction perpendicular to the major side of the substantially plane of the wafer or substrate. For example, in Figure 4 , interconnect 329 is located directly below post portion 415. Interconnect 329 is not located directly below post portion 425. A structure is “located directly between” two structures on a line if two other structures are located on opposite sides of the line. For example, Figure 1 in Figure 1In the cross-sectional side view of , STI 119 is located in a line centered between STI 117 and STI 120. STI 119 is not located in a line centered between gates 121 and 123. A first structure is "directly transverse" to a second structure if the first structure and the second structure are located in a line having a direction parallel to the major side of the generally planar surface of the wafer or substrate. For example, gate 121 and gate 123 are directly transverse to each other. A structure is "laterally centered between" two other structures if the two other structures are located on opposite sides of the structure in a line parallel to the major side of the generally planar surface of the wafer or substrate. For example, in Figure 1 , STI 119 is laterally located centered between STI 117 and STI 120. A surface is at a "higher elevation" than another surface if it is closer to the top of the active side of the wafer or integrated circuit on a line having a direction perpendicular to the major sides of the generally planar surface of the wafer or integrated circuit. Figure 4 In the view of FIG. 3 , the active side of the wafer 301 is Figure 4 For example, column portion 415 is at a higher elevation than interconnect 323.

[0088] Features specifically shown or described with respect to one embodiment set forth herein may be implemented in other embodiments set forth herein.

[0089] While particular embodiments of the present invention have been shown and described, those skilled in the art will recognize that, based on the teachings herein, further changes and modifications may be made without departing from the present invention and its broader aspects, and therefore, the appended claims are intended to cover within their scope all such changes and modifications that are within the true spirit and scope of the present invention.

Claims

1. An integrated circuit, characterized in that: include: a substrate including a semiconductor region for one or more semiconductor devices; one or more metal interconnect layers, the one or more metal interconnect layers comprising electrical interconnect structures electrically coupled to a semiconductor region of the substrate; a plurality of die ends, wherein each die end is electrically coupled to an electrical interconnect structure of the one or more metal interconnect layers; a dielectric layer overlying the one or more metal interconnect layers, the dielectric layer comprising a plurality of openings, wherein a conductive material resides in the openings of the plurality of openings and is electrically coupled to an electrical interconnect structure of the one or more metal interconnect layers; The dielectric layer includes a first region and a second region, the first region includes a selectively implanted stress-setting dopant, and the second region does not contain the selectively implanted stress-setting dopant.

2. The integrated circuit according to claim 1, characterized in that The first region and the second region are each laterally closest to a first die end, wherein the first region is laterally closer to the first die end than the second region.

3. The integrated circuit according to claim 1, characterized in that The dielectric layer includes a third region including a selectively implanted stress-setting dopant.

4. The integrated circuit according to claim 3, characterized in that The selectively implanted stress-setting dopant in the first region provides a first stress profile for the first region, wherein the first region is under a first type of stress, and the selectively implanted stress-setting dopant implanted into the third region provides a second stress profile for the third region, wherein the second region is under a second type of stress opposite to the first type of stress.

5. The integrated circuit according to claim 1, characterized in that The first region is positioned proximate to a first die end of the plurality of die ends, wherein a concentration of stress-setting dopants in a first portion of the first region is higher than a concentration of stress-setting dopants in a second portion of the first region, wherein the second portion is positioned laterally further away from the first die end than the first portion.

6. A packaged integrated circuit, characterized in that: Comprising an integrated circuit according to claim 1.

7. An integrated circuit, characterized in that: include: a substrate including a semiconductor region for one or more semiconductor devices; one or more metal interconnect layers, the one or more metal interconnect layers comprising electrical interconnect structures electrically coupled to a semiconductor region of the substrate; a dielectric layer overlying the one or more metal interconnect layers, the dielectric layer comprising a plurality of openings, wherein a conductive material resides in the openings of the plurality of openings and is electrically coupled to an electrical interconnect structure of the one or more metal interconnect layers; The dielectric layer includes a first region and a second region, the second region being directly transverse to the first region, wherein a concentration of a first type of dopant in the first region is at least five atomic percent greater than a concentration of the first type of dopant in the second region.

8. The integrated circuit according to claim 7, characterized in that The dielectric layer includes a third region including a selectively implanted stress-setting dopant of at least one of the group consisting of a different kind and a different concentration than the first kind of dopant in the first region.

9. A packaged integrated circuit, characterized in that: Comprising an integrated circuit according to claim 7.

10. A method, characterized in that include: forming a semiconductor region for a semiconductor device in a substrate; forming one or more metal interconnect layers over the substrate, wherein the one or more metal interconnect layers include electrical interconnect structures electrically coupled to a semiconductor region of the substrate; forming a plurality of die ends, wherein each die end is electrically coupled to an electrical interconnect structure of the one or more metal interconnect layers; forming a dielectric layer over the one or more metal interconnect layers; A stress-setting dopant is selectively implanted into a first region of the dielectric layer, wherein a second region of the dielectric layer is masked from being implanted with the stress-setting dopant.

Images