Test structure and test method

Abstract

A test structure and test method are disclosed, wherein the test structure includes: a test active area; a test gate structure; a test shared conductive plug electrically connected to the test gate structure and the test active area; a test conductive plug located on the test gate structure; a first test pad; a second test pad; a third test pad; a fourth test pad; and a fifth test pad. The test conductive plugs are arranged to simulate the actual environment of a memory cell, so that the environment of the test shared conductive plugs in the test structure is closer to the environment of the shared conductive plugs in a real static random access memory, and the test results of the test structure more accurately reflect the performance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a test structure and a test method. Background Art

[0002] In order to reduce the area of ​​static random access memory (SRAM) in integrated circuits, a shared contact (SCT) structure was introduced in more advanced processes. Shared contact holes have a significant impact on the yield of finished products manufactured in SRAM. The morphology of shared contact holes is different from that of ordinary contact holes. Part of the shared contact hole contacts the drain active area, part contacts the gate polysilicon, and even part directly contacts the oxide isolation layer. Compared with ordinary contact hole structures, the working environment of shared contact holes is more complex. Overlay accuracy, the morphology of metal silicide (Salicide) and the gate will affect the contact of the shared contact hole, thereby increasing the resistance of the entire system.

[0003] However, the current test structure of shared contact holes needs to be improved. Summary of the Invention

[0004] The problem solved by the present invention is how to further optimize the test structure of the shared contact hole so as to make the performance test of the shared contact hole more accurate.

[0005] To solve the above problems, the present invention provides a test structure for testing a semiconductor structure, wherein the semiconductor structure comprises: an active area, wherein the active area is located in a substrate; a gate structure, wherein the gate structure is located on the substrate; a shared conductive plug, wherein the shared conductive plug is located on the active area and the gate structure, wherein the shared conductive plug is electrically connected to the active area and the shared conductive plug is electrically connected to the gate structure; a conductive plug, wherein the conductive plug is located on the gate structure and the conductive plug is electrically connected to the gate structure; the test structure comprises: a test active area, wherein the test active area and the active area are formed through the same process, wherein the test active area comprises a first portion, a second portion and a connecting portion, wherein the connecting portion connects one end of the first portion and one end of the second portion; a test gate structure, wherein the test gate structure and the gate structure are formed through the same process, wherein the test gate structure comprises a first portion, a second portion and a connecting portion, wherein the connecting portion A connecting portion connects one end of the first portion and one end of the second portion; a test shared conductive plug, the test shared conductive plug and the shared conductive plug are formed through the same process, and the test shared conductive plug is electrically connected to the connecting portion of the test gate structure and the connecting portion of the test active area; a test conductive plug, the test conductive plug and the conductive plug are formed through the same process, and the test conductive plug is located on the test gate structure; a first test pad, the first test pad is electrically connected to the other end of the second portion of the test active area; a second test pad, the second test pad is electrically connected to the other end of the second portion of the test gate structure; a third test pad, the third test pad is electrically connected to the test shared conductive plug; a fourth test pad, the fourth test pad is electrically connected to the other end of the first portion of the test active area; and a fifth test pad is electrically connected to the other end of the first portion of the test gate structure.

[0006] Optionally, there is no electrical connection between the test conductive plug and the test gate structure.

[0007] Optionally, the first portion of the test active area and the second portion of the test active area are both in a strip shape, and an extension direction of the first portion of the test active area is perpendicular to an extension direction of the second portion of the test active area.

[0008] Optionally, the first portion of the test gate structure and the second portion of the test gate structure are both in a strip shape, and an extension direction of the first portion of the test gate structure is perpendicular to an extension direction of the second portion of the test gate structure.

[0009] Optionally, an extension direction of the first portion of the test gate structure is parallel to an extension direction of the second portion of the test active region.

[0010] Optionally, an extension direction of the second portion of the test gate structure is parallel to an extension direction of the first portion of the test active region.

[0011] Correspondingly, the present invention also provides a testing method, comprising: providing a semiconductor structure as described in any one of the above items; loading a drain power supply voltage through the fourth test pad; obtaining a first test current through the fifth test pad; obtaining a first test voltage through the first test pad; obtaining a second test voltage through the second test pad; and obtaining the contact resistance of the test shared conductive plug based on the first test voltage, the second test voltage, and the first test current.

[0012] Optionally, in the step of obtaining a first test current through the fifth test pad, the first test current passes through a first portion of the test active area to a first portion of the test gate structure.

[0013] Optionally, the method further includes: loading a 0V voltage through the fifth test pad.

[0014] Optionally, the method further includes: obtaining a third test voltage through the third test pad.

[0015] Optionally, the contact resistance between the test shared conductive plug and the test active area is obtained according to the first test voltage, the third test voltage, and the first test current.

[0016] Optionally, the contact resistance between the test shared conductive plug and the test gate structure is obtained according to the second test voltage, the third test voltage, and the first test current.

[0017] Correspondingly, the present invention also provides a testing method, comprising: providing a semiconductor structure as described in any one of the above items; loading a fourth test voltage through the third test pad; obtaining a second test current through the first test pad; and obtaining the block resistance of the test active area based on the second test current, combined with the fourth test voltage and a preset number of blocks.

[0018] Optionally, the method further includes: loading a 0V voltage through the first test pad.

[0019] Optionally, the step of obtaining the preset number of blocks includes: obtaining the length of the second part of the test active area and the width of the second part of the test active area; and obtaining the preset number of blocks based on the length of the second part of the test active area and the width of the second part of the test active area.

[0020] Correspondingly, the present invention also provides a testing method, comprising: providing a semiconductor structure as described in any one of the above items; loading a fifth test voltage through the third test pad; obtaining a third test current through the second test pad; and obtaining the block resistance of the test gate structure based on the third test current, combined with the fifth test voltage and a preset number of blocks.

[0021] Optionally, the method further includes: loading a 0V voltage through the second test pad.

[0022] Optionally, the step of obtaining the preset number of blocks includes: obtaining the length of the second part of the test gate structure and the width of the second part of the test gate structure; and obtaining the preset number of blocks based on the length of the second part of the test gate structure and the width of the second part of the test gate structure.

[0023] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0024] In the test structure of the technical solution of the present invention, the test conductive plug is provided to simulate the environment of the storage unit of the static random access memory, so that when the test shared conductive plug is formed by etching and planarization, the pattern density of the test shared conductive plug is closer to the pattern density of the conductive plug and the shared conductive plug in the semiconductor structure, thereby reducing the difference in morphology between the test shared conductive plug of the test structure and the shared conductive plug of the semiconductor structure caused by the load effect, making the environment of the test shared conductive plug in the test structure closer to the environment of the shared conductive plug in the real static random access memory, so that the test results of the test structure more accurately reflect the performance of the semiconductor device; and The test structure measures the contact resistance of the test shared conductive plug, the contact resistance between the test shared conductive plug and the test active area, and the contact resistance between the test shared conductive plug and the test gate structure through a first test pad located on the test active area, a second test pad located on the test gate structure, and a third test pad located on the test shared conductive plug. The test structure reduces the parasitic resistance of the test structure and improves the test accuracy of the test structure. In addition, the test structure is also suitable for measuring the square resistance of the test active area and the square resistance of the test gate structure, saving test area while achieving more accurate monitoring of the test structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a top view of a test structure according to an embodiment of the present invention;

[0026] Figure 2 3 is a schematic cross-sectional structural diagram of a test structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] As can be seen from the background technology, the contact resistance of the shared contact hole in the prior art still has problems. The reasons for the problem are analyzed in conjunction with an embodiment:

[0028] The graphic density of the test shared contact plugs in the existing test structure (TestKey, abbreviated as TSK) is different from the graphic density of the shared contact plugs in the storage cells of the static random access memory, resulting in a large difference in the morphology of the test shared contact plugs in the test structure and the shared conductive plugs in the storage cells of the static random access memory, affecting the accuracy of the performance test of the test shared contact plugs.

[0029] In order to solve the technical problem, the present invention provides a test structure, comprising: a test active area, wherein the test active area and the active area are formed through the same process, the test active area comprises a first portion, a second portion and a connecting portion, and the connecting portion connects one end of the first portion and one end of the second portion; a test gate structure, wherein the test gate structure and the gate structure are formed through the same process, the test gate structure comprises a first portion, a second portion and a connecting portion, and the connecting portion connects one end of the first portion and one end of the second portion; a test shared conductive plug, wherein the test shared conductive plug and the shared conductive plug are formed through the same process, and the test shared conductive plug and the connecting portion of the test gate structure and the test gate structure are connected. The connection parts of the test active area are all electrically connected; a test conductive plug, the test conductive plug and the conductive plug are formed through the same process, and the test conductive plug is located on the test gate structure; a first test pad, the first test pad is electrically connected to the other end of the second part of the test active area; a second test pad, the second test pad is electrically connected to the other end of the second part of the test gate structure; a third test pad, the third test pad is electrically connected to the test shared conductive plug; a fourth test pad, the fourth test pad is electrically connected to the other end of the first part of the test active area; and a fifth test pad, the fifth test pad is electrically connected to the other end of the first part of the test gate structure.

[0030] In the test structure of the technical solution of the present invention, the test conductive plug is located on the test gate structure. The test conductive plug is provided to simulate the process environment of a memory cell of a static random access memory (SRAM), so that the environment of the test shared conductive plug in the test structure is closer to the environment of the shared conductive plug in a real SRAM, and the test results of the test structure more accurately reflect the performance of the semiconductor device.

[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] The test structure described in this embodiment is used to test a semiconductor structure, which includes: an active area, wherein the active area is located in a substrate; a gate structure, wherein the gate structure is located on the substrate; a shared conductive plug, wherein the shared conductive plug is located on the active area and the gate structure, wherein the shared conductive plug is electrically connected to the active area and the shared conductive plug is electrically connected to the gate structure; and a conductive plug, wherein the conductive plug is located on the gate structure and electrically connected to the gate structure.

[0033] Please refer to Figure 1 and Figure 2 , Figure 2 for Figure 1 Cross-sectional view at position AA1, Figure 1 The metal silicide layer is not shown. The test structure includes: a test active area 101, which is formed by the same process as the active area. The test active area 101 includes a first portion I, a second portion II, and a connecting portion, wherein the connecting portion connects one end of the first portion I and one end of the second portion II.

[0034] Specifically, in some embodiments of the present invention, the first portion I of the test active area 101 and the second portion II of the test active area 101 are both in the shape of long strips, and the extension direction of the first portion I of the test active area 101 is perpendicular to the extension direction of the second portion II of the test active area 101.

[0035] Please refer to Figure 2 The test active area 101 is located in the substrate 100. Specifically, in some embodiments of the present invention, the second portion II of the test active area 101 extends along the first direction X; and the first portion I of the test active area 101 extends along the second direction Y.

[0036] Please refer to Figure 1 and Figure 2 The test structure includes: a test gate structure 102, the test gate structure 102 and the gate structure are formed through the same process, the test gate structure 102 includes a first part I, a second part II and a connecting part, the connecting part connects one end of the first part I and one end of the second part II.

[0037] Specifically, in some embodiments of the present invention, the first part I of the test gate structure 102 and the second part II of the test gate structure 102 are both in the shape of long strips, and the extension direction of the first part I of the test gate structure 102 is perpendicular to the extension direction of the second part II of the test gate structure 102.

[0038] Please refer to Figure 2The test gate structure 102 is located on the substrate 100. Specifically, in some embodiments of the present invention, the first portion I of the test gate structure 102 extends along a first direction X; and the second portion II of the test gate structure 102 extends along a second direction Y.

[0039] The first portion I of the test gate structure 102 extends in a direction parallel to the second portion II of the test active area 101; the second portion II of the test gate structure 102 extends in a direction parallel to the first portion I of the test active area 101. Specifically, in some embodiments of the present invention, the first portion I of the test gate structure 102 extends along a first direction X, and the second portion II of the test active area 101 extends along the first direction X; the second portion II of the test gate structure 102 extends along a second direction Y, and the first portion I of the test active area 101 extends along the second direction Y.

[0040] Please refer to Figure 2 The test structure includes: a test shared conductive plug 103, the test shared conductive plug 103 and the shared conductive plug are formed through the same process, and the test shared conductive plug 103 is electrically connected to the connection part of the test gate structure 102 and the connection part of the test active area 101.

[0041] The test shared conductive plug 103 is located on the test active area 101 and the test gate structure 102 . The test shared conductive plug 103 is electrically connected to the test active area 101 and the test gate structure 102 .

[0042] Specifically, in some embodiments of the present invention, the test shared conductive plug 103 is located on the test active area 101 and the test gate structure 102, that is: the projection of the test shared conductive plug 103 on the surface of the substrate 100 partially overlaps with the projection of the test active area 101 on the surface of the substrate 100, and the projection of the test shared conductive plug 103 on the surface of the substrate 100 partially overlaps with the projection of the test gate structure 102 on the surface of the substrate 100.

[0043] Please refer to Figure 1 and Figure 2 The test structure includes: a test conductive plug 104, the test conductive plug 104 and the conductive plug are formed through the same process, and the test conductive plug 104 is located on the test gate structure.

[0044] The purpose of setting up multiple test conductive plugs 104 in the test structure is to simulate the environment of the storage unit of the static random access memory, so that the environment of the test shared conductive plug 103 in the test structure is closer to the environment of the shared conductive plug in the real static random access memory, so that the test results of the test structure can more accurately reflect the performance of the semiconductor device, such as more accurately measuring the contact resistance of the test shared conductive plug 103, the contact resistance between the test shared conductive plug 103 and the test active area 101, and the contact resistance between the test shared conductive plug 103 and the test gate structure 102, thereby improving the test accuracy of the test structure.

[0045] The reason why arranging a plurality of the test conductive plugs 104 in the test structure can make the environment of the test shared conductive plug 103 closer to the environment of the shared conductive plug in the real static random access memory is that: when the etching and planarization processes are performed to form the test shared conductive plug 103 and the test conductive plug 104, the graphic density of the test shared conductive plug 103 and the test conductive plug 104 is closer to the graphic density of the conductive plug and the shared conductive plug in the semiconductor structure, thereby reducing the difference in morphology between the test shared conductive plug 103 of the test structure and the shared conductive plug of the semiconductor structure caused by the load effect.

[0046] Specifically, in some embodiments of the present invention, the test conductive plug 104 is not electrically connected to the test gate structure 102, and no voltage is applied to the test conductive plug 104. The test conductive plug 104 only simulates the process environment of the SRAM storage cell, and does not simulate the electrical environment of the SRAM storage cell. In other embodiments, a voltage may be applied to the test conductive plug to simulate the electrical environment of the SRAM storage cell.

[0047] The test conductive plug 104 is suitable for simulating the environment of a static random access memory cell. Specifically, in some embodiments of the present invention, the area of ​​the test structure where the test conductive plug 104 is located is the same as the area of ​​a 1×1 SRAM memory cell.

[0048] Please refer to Figure 1 The test structure includes: a first test pad 105 , which is electrically connected to the other end of the second portion II of the test active area 101 .

[0049] Please refer to Figure 1The second part II of the test active area 101 has two opposite ends, one end of the second part II of the test active area 101 is electrically connected to the connecting part of the test active area 101, and the other end of the second part II of the test active area 101 is electrically connected to the first test pad 105.

[0050] In some embodiments of the present invention, the first test pad 105 is adapted to obtain a voltage of the test active area 101 to obtain a contact resistance of the test shared conductive plug 103 .

[0051] In some embodiments of the present invention, the first test pad 105 is adapted to obtain a voltage of the test active area 101 , so as to obtain a contact resistance between the test shared conductive plug 103 and the test active area 101 .

[0052] Please refer to Figure 1 The test structure includes: a second test pad 106 , and the second test pad 106 is electrically connected to the other end of the second portion II of the test gate structure 102 .

[0053] The second portion II of the test gate structure 102 has two opposite ends. One end of the second portion II of the test gate structure 102 is electrically connected to the connection portion of the test gate structure 102 , and the other end of the second portion II of the test gate structure 102 is electrically connected to the second test pad 106 .

[0054] In some embodiments of the present invention, the second test pad 106 is adapted to obtain a voltage of the test gate structure 102 to obtain a contact resistance of the test shared conductive plug 103 .

[0055] In some embodiments of the present invention, the second test pad 106 is adapted to obtain a voltage of the test gate structure 102 to obtain a contact resistance between the test shared conductive plug 103 and the test gate structure 102 .

[0056] Please refer to Figure 2 The test structure includes: a third test pad 107 , wherein the third test pad 107 is electrically connected to the test shared conductive plug 103 .

[0057] The third test pad 107 is located on the test shared conductive plug 103 .

[0058] In some embodiments of the present invention, the third test pad 107 is adapted to obtain a voltage of the test shared conductive plug 103 to obtain a contact resistance between the test shared conductive plug 103 and the test active area 101 .

[0059] In some embodiments of the present invention, the third test pad 107 is adapted to obtain a voltage of the test shared conductive plug 103 to obtain a contact resistance between the test shared conductive plug 103 and the test gate structure 102 .

[0060] Please refer to Figure 1 The test structure includes: a fourth test pad 108, wherein the fourth test pad 108 is electrically connected to the other end of the first portion I of the test active area 101.

[0061] The first portion I of the test active area 101 has two opposite ends. One end of the first portion I of the test active area 101 is electrically connected to the connection portion of the test active area 101 , and the other end of the first portion I of the test active area 101 is electrically connected to the fourth test pad 108 .

[0062] Specifically, in some embodiments of the present invention, the fourth test pad 108 is suitable for loading a drain voltage.

[0063] Please refer to Figure 1 The test structure includes: a fifth test pad 109, and the fifth test pad 109 is electrically connected to the other end of the first portion I of the test gate structure 102.

[0064] The first portion I of the test gate structure 102 has two opposite ends, one end of the first portion I of the test gate structure 102 is electrically connected to the connecting portion of the test gate structure 102, and the other end of the first portion I of the test gate structure 102 is electrically connected to the fifth test pad 109.

[0065] Accordingly, an embodiment of the present invention also provides a testing method, comprising: providing a semiconductor structure as described in any one of the above items; loading a drain power supply voltage through the fourth test pad 108; obtaining a first test current through the fifth test pad 109; obtaining a first test voltage through the first test pad 105; obtaining a second test voltage through the second test pad 106; and obtaining the contact resistance of the test shared conductive plug 103 based on the first test voltage, the second test voltage, and the first test current.

[0066] The testing method further includes applying a 0V voltage through the fifth test pad 109. That is, after applying Vdd to the fourth test pad 108 and applying a 0V voltage to the fifth test pad 109, a first test current I1 is obtained through the fifth test pad 109; a first test voltage V1 is obtained through the first test pad 105; and a second test voltage V2 is obtained through the second test pad 106.

[0067] In the step of obtaining a first test current through the fifth test pad 109 , the first test current flows through the first portion I of the test active region 101 to the first portion I of the test gate structure 102 .

[0068] The contact resistance of the test shared conductive plug 103 is obtained according to the first test voltage, the second test voltage and the first test current, that is, the contact resistance RCKV of the test shared conductive plug 103 is obtained according to the first test voltage V1, the second test voltage V2 and the first test current I1. _SCT The contact resistance of the test shared conductive plug 103 is:

[0069]

[0070] The testing method further includes: obtaining a third testing voltage V3 through the third testing pad 107 .

[0071] The testing method includes obtaining a contact resistance RCKV_SCT_AA between the test shared conductive plug 103 and the test active area 101 according to the first test voltage, the third test voltage, and the first test current. Specifically, the contact resistance RCKV_SCT_AA between the test shared conductive plug 103 and the test active area 101 is obtained according to the first test voltage V1, the third test voltage V3, and the first test current I1. The magnitude of the contact resistance between the test shared conductive plug 103 and the test active area 101 is:

[0072] The testing method includes: obtaining a contact resistance RCKV_SCT_POLY between the test shared conductive plug 103 and the test gate structure 102 according to the second test voltage, the third test voltage, and the first test current, that is, obtaining a contact resistance RCKV_SCT_POLY between the test shared conductive plug 103 and the test gate structure 102 according to the second test voltage V2, the third test voltage V3, and the first test current I1. The magnitude of the contact resistance between the test shared conductive plug 103 and the test gate structure 102 is:

[0073] Accordingly, an embodiment of the present invention also provides a testing method, comprising: providing a semiconductor structure as described in any one of the above items; loading a fourth test voltage through the third test pad 107; obtaining a second test current through the first test pad 105; and obtaining the block resistance of the test active area 101 based on the second test current, combined with the fourth test voltage and a preset number of blocks.

[0074] The test method further includes: applying a 0V voltage through the first test pad 105 , that is, applying a fourth test voltage V4 to the third test pad 107 , and obtaining a second test current I2 through the first test pad 105 after applying the 0V voltage to the first test pad 105 .

[0075] According to the second test current, in combination with the fourth test voltage and the preset number of blocks, the sheet resistance of the test active area 101 is obtained. That is, according to the second test current I2, in combination with the fourth test voltage V4 and the preset number of blocks Sq1, the sheet resistance RS_AA of the test active area 101 is obtained. The size of the sheet resistance of the test active area 101 is:

[0076] Specifically, in some embodiments of the present invention, the step of obtaining the preset number of blocks includes: obtaining the length of the second part II of the test active area 101 and the width of the second part II of the test active area 101; and obtaining the preset number of blocks according to the length of the second part II of the test active area 101 and the width of the second part II of the test active area 101.

[0077] Specifically, in some embodiments of the present invention, the length L1 of the second portion II of the test active area 101 is the size of the second portion II of the test active area 101 along the first direction X; the width W1 of the second portion II of the test active area 101 is the size of the second portion II of the test active area 101 along the second direction Y.

[0078] Specifically, in some embodiments of the present invention, the preset number of blocks is obtained, that is, according to the ratio of the length L1 of the second portion II of the test active area 101 to the width W1 of the second portion II of the test active area 101, the preset number of blocks is obtained.

[0079] Accordingly, an embodiment of the present invention further provides a testing method, comprising: providing a semiconductor structure as described above; applying a fifth test voltage through the third test pad 107; obtaining a third test current through the second test pad 106; and obtaining the sheet resistance of the test gate structure 102 based on the third test current, the fifth test voltage, and a predetermined number of squares. The testing method further comprises: applying a 0V voltage through the second test pad 106. Specifically, after applying the fifth test voltage V5 to the third test pad 107 and applying the 0V voltage to the second test pad 106, a third test current I3 is obtained through the second test substrate 100.

[0080] According to the third test current, in combination with the fifth test voltage and the preset number of blocks, the square resistance of the test gate structure 102 is obtained, that is, according to the third test current I3, in combination with the fifth test voltage V5 and the preset number of blocks Sq2, the square resistance RS_POLY of the test gate structure 102 is obtained. The square resistance of the test gate structure 102 is

[0081] Specifically, in some embodiments of the present invention, the step of obtaining the preset number of blocks includes: obtaining the length of the second part II of the test gate structure 102 and the width of the second part II of the test gate structure 102; and obtaining the preset number of blocks based on the length of the second part II of the test gate structure 102 and the width of the second part II of the test gate structure 102.

[0082] Specifically, in some embodiments of the present invention, the length L2 of the second part II of the test gate structure 102 is the size of the second part II of the test gate structure 102 along the first direction X; the width W2 of the second part II of the test gate structure 102 is the size of the second part II of the test gate structure 102 along the second direction Y.

[0083] Specifically, in some embodiments of the present invention, the preset number of blocks is obtained, that is, the preset number of blocks is obtained according to the ratio of the length L2 of the second portion II of the test gate structure 102 to the width W2 of the second portion II of the test gate structure 102.

[0084] In summary, by setting the test conductive plug, the process environment of the storage unit of the static random access memory is simulated in the test structure, so that the environment of the test shared conductive plug in the test structure is closer to the environment of the shared conductive plug in the real static random access memory, so that the test result of the test structure more accurately reflects the performance of the semiconductor device, and the contact resistance of the test shared conductive plug, the contact resistance between the test shared conductive plug and the test active area, and the contact resistance between the test shared conductive plug and the test gate structure measured by the test structure are more accurate, which can better monitor the test shared conductive plug of the storage unit of the static random access memory and ensure the stability of the process.

[0085] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A test structure, characterized in that: Used for testing a semiconductor structure, the semiconductor structure comprising: an active region, wherein the active region is located in the substrate; a gate structure, wherein the gate structure is located on the substrate; a shared conductive plug, the shared conductive plug being located on the active area and the gate structure, the shared conductive plug being electrically connected to the active area, and the shared conductive plug being electrically connected to the gate structure; a conductive plug, the conductive plug being located on the gate structure and electrically connected to the gate structure; The test structure includes: a test active region, wherein the test active region and the active region are formed through the same process, the test active region comprising a first portion, a second portion, and a connecting portion, wherein the connecting portion connects one end of the first portion and one end of the second portion; a test gate structure, wherein the test gate structure and the gate structure are formed through the same process, the test gate structure comprising a first portion, a second portion, and a connecting portion, wherein the connecting portion connects one end of the first portion and one end of the second portion; a test shared conductive plug, wherein the test shared conductive plug and the shared conductive plug are formed through the same process, and the test shared conductive plug is electrically connected to a connection portion of the test gate structure and a connection portion of the test active area; a test conductive plug, wherein the test conductive plug and the conductive plug are formed through the same process, and the test conductive plug is located on the test gate structure; a first test pad electrically connected to the other end of the second portion of the test active area; a second test pad electrically connected to the other end of the second portion of the test gate structure; a third test pad electrically connected to the test shared conductive plug; a fourth test pad electrically connected to the other end of the first portion of the test active area; A fifth test pad is electrically connected to the other end of the first portion of the test gate structure.

2. The test structure according to claim 1, wherein: There is no electrical connection between the test conductive plug and the test gate structure.

3. The test structure according to claim 1, wherein: The first portion of the test active area and the second portion of the test active area are both in a strip shape, and an extension direction of the first portion of the test active area is perpendicular to an extension direction of the second portion of the test active area.

4. The test structure according to claim 1, wherein: The first portion of the test gate structure and the second portion of the test gate structure are both in a strip shape, and an extension direction of the first portion of the test gate structure is perpendicular to an extension direction of the second portion of the test gate structure.

5. The test structure according to claim 1, wherein: An extension direction of the first portion of the test gate structure is parallel to an extension direction of the second portion of the test active region.

6. The test structure according to claim 1, wherein: An extension direction of the second portion of the test gate structure is parallel to an extension direction of the first portion of the test active region.

7. A testing method, characterized in that: include: Providing a semiconductor structure according to any one of claims 1 to 6; Applying a drain power supply voltage via the fourth test pad; obtaining a first test current through the fifth test pad; obtaining a first test voltage through the first test pad; obtaining a second test voltage through the second test pad; The contact resistance of the test shared conductive plug is obtained according to the first test voltage, the second test voltage, and the first test current.

8. The testing method according to claim 7, wherein: In the step of obtaining a first test current through the fifth test pad, the first test current flows through a first portion of the test active region to a first portion of the test gate structure.

9. The testing method according to claim 7, wherein: Also includes: A voltage of 0 V is applied through the fifth test pad.

10. The testing method according to claim 7, wherein: Also includes: A third test voltage is obtained through the third test pad.

11. The testing method according to claim 10, wherein: The contact resistance between the test shared conductive plug and the test active area is obtained according to the first test voltage, the third test voltage, and the first test current.

12. The testing method according to claim 10, wherein: The contact resistance between the test shared conductive plug and the test gate structure is obtained according to the second test voltage, the third test voltage, and the first test current.

13. A testing method, characterized in that: include: Providing a semiconductor structure according to any one of claims 1 to 6; applying a fourth test voltage through the third test pad; obtaining a second test current through the first test pad; The sheet resistance of the test active area is obtained according to the second test current, in combination with the fourth test voltage and a preset number of sheets.

14. The testing method according to claim 13, wherein: Also includes: A voltage of 0 V is applied through the first test pad.

15. The testing method according to claim 13, wherein: The step of obtaining the preset number of blocks includes: The length of the second portion of the test active area and the width of the second portion of the test active area are obtained; and the preset number of blocks is obtained according to the length of the second portion of the test active area and the width of the second portion of the test active area.

16. A testing method, characterized in that: include: Providing a semiconductor structure according to any one of claims 1 to 6; applying a fifth test voltage through the third test pad; obtaining a third test current through the second test pad; The sheet resistance of the test gate structure is obtained according to the third test current, in combination with the fifth test voltage and a preset number of blocks.

17. The testing method according to claim 16, wherein: Also includes: A voltage of 0 V is applied through the second test pad.

18. The testing method according to claim 16, wherein: The step of obtaining the preset number of blocks includes: obtaining a length of the second portion of the test gate structure and a width of the second portion of the test gate structure; The preset number of blocks is obtained according to the length of the second portion of the test gate structure and the width of the second portion of the test gate structure.

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