Electromagnetic interference shielding packaging structure and manufacturing method thereof

Abstract

The invention relates to an electromagnetic interference shielding packaging structure and a manufacturing method thereof. The present disclosure provides a semiconductor structure including a die / die stack attached on a substrate, a conductive top block covering a top surface of the die / die stack, and a plurality of ground lines conductively connecting the conductive top block to the substrate. The conductive top block, the plurality of ground lines, and the substrate form a Faraday cage to provide electromagnetic interference shielding of the die / die stack.

Description

[0001] This application is a divisional application of the Chinese invention patent application with the application date of June 8, 2021, application number 202180001890.6, and application name “Electromagnetic interference shielding packaging structure and manufacturing method thereof”. Technical Field

[0002] The present disclosure relates generally to the field of semiconductor technology, and more particularly to an electromagnetic interference shielding package structure and a method for manufacturing the same. Background Art

[0003] Electronic devices generate unwanted radio frequencies (RF), which, when emitted from the device, may cause electromagnetic interference ("EMI") to other nearby electronic devices. Unwanted EMI emitted from electronic devices may interfere with input / output broadcast signals. In conventional semiconductor packaging structures, semiconductor chips are packaged by one or more substrates (as lead frames) and various molding compounds, etc. Typically, one or more substrates include a composite material, and the molding compound includes an insulating material, such as plastic or a similar polymer. Electronic devices encapsulated on semiconductor chips in conventional semiconductor packaging structures provide little protection from EMI emissions.

[0004] In order to minimize the unwanted EMI emissions emitted from the electronic devices disposed within the housing, EMI shielding is required on certain semiconductor devices to minimize the EMI radiation from the semiconductor devices. EMI shielding is also required to prevent EMI radiation from external sources from interfering with the operation of the semiconductor devices. Currently, the application frequency range of semiconductor devices is becoming higher and higher, which requires higher EMI shielding requirements.

[0005] Conventional methods of shielding electronic devices include enclosing the device in a metal box, housing or cage, and coating the device with a metal coating. Unfortunately, these methods significantly increase the weight of the device, increase manufacturing costs, and may have corrosion problems in long-term use. Therefore, it would be useful to provide a method and structure for substantially shielding an electronic device, wherein the structure is relatively light, can be provided and incorporated into the device at a relatively low cost, while adding little weight to the device, and is corrosion resistant. Summary of the invention

[0006] Embodiments of electromagnetic interference shielding packaging structures and methods of making the same are described in this disclosure.

[0007] One aspect of the present disclosure provides a semiconductor structure, comprising: a first die / die stack attached to a substrate, a conductive top block covering a top surface of the first die / die stack, and a plurality of ground lines conductively connecting the conductive top block to the substrate. The conductive top block, the plurality of ground lines, and the substrate form a Faraday cage to provide electromagnetic interference shielding for the first die / die stack.

[0008] In some embodiments, the plurality of ground lines surround the first die / die stack.

[0009] In some embodiments, in a plane substantially parallel to the main surface of the substrate, the size of the conductive top block is larger than the size of the first die / die stack such that the top surface of the first die / die stack is completely covered by the conductive top block.

[0010] In some embodiments, the semiconductor structure further includes a molding compound layer on the substrate and covering the conductive top block and the plurality of ground lines, and a plurality of solder balls attached to a bottom surface of the substrate.

[0011] In some embodiments, the conductive top block includes a conductive plate having a thickness between about 20 μm and about 100 μm, an insulating layer covering a top surface of the conductive plate, and a plurality of bonding pads embedded in the insulating layer and in electrical contact with the conductive plate.

[0012] In some embodiments, the conductive plate is a metal plate or a conductive polymer plate doped with a metal or a metal oxide.

[0013] In some embodiments, the plurality of bond pads are positioned adjacent to all edges of the conductive top block and have a thickness between about 0.5 μm and about 1 μm, and have a bond pad pitch between about 50 μm and about 5 mm.

[0014] In some embodiments, the conductive top block includes a conductive film on the top surface of the silicon wafer, an insulating layer covering the top surface of the conductive film, and a plurality of bonding pads embedded in the insulating layer and electrically contacting the conductive film, wherein the thickness of the conductive film is in a range from about 1 μm to about 20 μm.

[0015] In some embodiments, the conductive film is a metal film or a conductive ink film.

[0016] In some embodiments, the first die / die stack is attached to the substrate by a first adhesive film, and the conductive top block is attached to the top surface of the first die / die stack by a second adhesive film different from the first adhesive film.

[0017] In some embodiments, the first adhesive film is a die attach film, and the second adhesive film is a film over wire penetrated by a plurality of signal lines of the die / die stack.

[0018] In some embodiments, the semiconductor structure further includes a second die / die stack without EMI protection.

[0019] In some embodiments, the second die / die stack is located on one side of the first die / die stack in a lateral direction.

[0020] In some embodiments, the second die / die stack includes a three-dimensional NAND flash memory device, and the first die / die stack includes a memory controller for controlling the three-dimensional NAND flash memory device.

[0021] In some embodiments, the second die / die stack is located on the top surface of the conductive top block.

[0022] Another aspect of the present disclosure provides a method of forming a semiconductor structure, comprising: attaching a first tube die / die stack on a substrate; forming a conductive top block having a size larger than the first tube die / die stack; attaching the conductive top block to cover the top surface of the first tube die / die stack; and forming a plurality of ground lines conductively connecting the conductive top block and the substrate, so that the conductive top block, the plurality of ground lines and the substrate form a Faraday cage to provide electromagnetic interference shielding for the first tube die / die stack.

[0023] In some embodiments, forming the plurality of ground lines includes forming the plurality of ground lines around the first die / die stack.

[0024] In some embodiments, the method further includes: forming a molding compound layer on the substrate to cover the conductive top block and the plurality of ground lines; and attaching a plurality of solder balls to a bottom surface of the substrate.

[0025] In some embodiments, forming a conductive top block includes: forming a conductive plate having a thickness between about 20 μm and about 100 μm; forming an insulating layer covering a top surface of the conductive plate; and forming a plurality of bonding pads having a thickness between about 0.5 μm and about 1 μm embedded in the insulating layer and in electrical contact with the conductive plate.

[0026] In some embodiments, the method further includes arranging the plurality of bonding pads adjacent to all edges of the conductive top block and having a bonding pad pitch between about 50 μm and about 5 mm.

[0027] In some embodiments, the method further includes: forming a conductive film on the top surface of the silicon wafer by spin coating, spraying, plating or sputtering, wherein the thickness of the conductive film is in a range from about 1 μm to about 20 μm; forming an insulating layer covering the top surface of the conductive film; and forming a plurality of bonding pads with a thickness between about 0.5 μm and about 1 μm embedded in the insulating layer and electrically contacting the conductive film.

[0028] In some embodiments, the method further includes forming at least one signal line connecting the first die / die stack to the substrate, wherein a portion of the at least one signal line penetrates a second adhesive film for attaching the conductive top block.

[0029] In some embodiments, the method further includes forming a second die / die stack without EMI protection located on a side of the first die / die stack in a lateral direction.

[0030] In some embodiments, the method further includes forming a second die / die stack without EMI protection on the top surface of the conductive top block.

[0031] Other aspects of the present disclosure may be understood by those skilled in the art based on the specification, claims and drawings of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present invention and, together with the description, further serve to explain the principles of the invention and enable one skilled in the relevant art to make and use the invention.

[0033] Figure 1 Schematic diagram illustrating a perspective side view of an exemplary semiconductor device structure according to some embodiments of the present disclosure.

[0034] Figure 2A A schematic diagram illustrating a perspective side view of an exemplary conductive top block according to some embodiments of the present disclosure.

[0035] Figure 2B A schematic diagram illustrating a perspective side view of another exemplary conductive top block according to some embodiments of the present disclosure.

[0036] Figure 2C A schematic diagram illustrating a top view of an exemplary conductive top block according to some embodiments of the present disclosure.

[0037] Figure 3 A flow chart is shown of an exemplary method for forming an electromagnetic interference shielding packaging structure according to some embodiments of the present disclosure.

[0038] Figure 4A A schematic diagram illustrating a perspective side view of another exemplary semiconductor device structure according to some embodiments of the present disclosure.

[0039] Figure 4B Schematic diagram showing a top view of an exemplary semiconductor device structure according to some embodiments of the present disclosure.

[0040] Figure 5 A schematic diagram illustrating a perspective side view of another exemplary semiconductor device structure according to some embodiments of the present disclosure.

[0041] The features and advantages of the present invention will become more apparent from the detailed description set forth below in conjunction with the accompanying drawings, in which the same reference numerals always identify corresponding elements. In the accompanying drawings, the same reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit or digits in the corresponding reference numeral.

[0042] Embodiments of the present disclosure will be described with reference to the drawings. DETAILED DESCRIPTION

[0043] Although specific configurations and arrangements have been discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in various other applications.

[0044] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0045] Typically, a term can be understood at least in part by its usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "one", "an" or "the" can also be understood to express singular usage or to express plural usage. In addition, the term "based on" can be understood to not necessarily express an exclusive set of factors, but can allow for the presence of other factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0046] It should be readily understood that the meaning of "on", "over", and "over" in the present disclosure should be interpreted in the broadest manner, such that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers. In addition, "on" or "over" not only means "on something" or "above something", but also includes the meaning of "on something" or "over something" without intervening features or layers (i.e., directly on something).

[0047] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," and "upper" may be used herein to describe the relationship of one element or feature to other (one or more) elements or (one or more) features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or process steps in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0048] As used herein, the term "substrate" refers to a material to which subsequent material layers are added. The substrate includes a "top" surface and a "bottom" surface. Unless otherwise specified, the front side of the substrate is generally where the semiconductor device is formed, and thus the semiconductor device is formed on the top side of the substrate. The bottom surface is opposite to the front side, and thus the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0049] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is adjacent to the substrate, and the top side is relatively far away from the substrate. The layer can extend over the entire lower or upper structure, or can have a range less than the lower or upper structure range. In addition, the layer can be a region of a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure or between any horizontal plane sets at the top surface and the bottom surface. The layer can extend laterally, vertically and / or along a tapered surface. The substrate can be a layer, wherein one or more layers can be included, and / or one or more layers can be provided on, above and / or below it. The layer can include multiple layers. For example, the interconnect layer can include one or more conductive and contact layers (wherein contacts, interconnect lines and / or vertical interconnect paths (VIA) are formed) and one or more dielectric layers.

[0050] As used herein, the term "nominal / nominally" refers to an expected or target value for a characteristic or parameter of a component or process step set during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. The range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" refers to a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "approximately" may mean that the value of a given quantity varies, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0051] In this disclosure, the terms “horizontal / horizontally / lateral / laterally” refer to nominally parallel to a lateral surface of a substrate, and the terms “vertical” or “vertically” refer to nominally perpendicular to a lateral surface of a substrate.

[0052] In the past, EMI shielding structures were usually implemented in several ways. The first method is to attach a Faraday cage over the component after attaching it to a substrate (such as a printed circuit board). The Faraday cage is formed by using wire bonding technology. However, this method has several problems. First, such a Faraday cage has a high cost due to the consumption of precious metals (such as gold, silver, and copper). Second, the manufacturing process is slow in order to connect the metal wires one by one. Third, some complex integrated circuit (IC) layouts require long wires across the chip, which increases the difficulty of the manufacturing process.

[0053] Another method is to form a plated coating as an EMI film by sputtering or spraying a conductive material on the surface or part of the surface of the package body. However, this method also has several problems. First, the cost is high because a dedicated expensive sputtering or spraying device is required, and a precious metal (such as silver) is required as a conductive material for sputtering or spraying. Second, the ground line connection formed by connecting the exposed ground traces around the substrate has the risk of high contact resistance. Third, the surface of the plated coating is easily damaged and oxidized.

[0054] The present disclosure provides an electromagnetic interference shielding packaging structure and a manufacturing method thereof to solve the above problems. In some embodiments, the disclosed EMI shielding packaging structure may include a conductive block covering the top surface of a tube core or a tube core stack that needs EMI protection. The conductive top block may be a metal plate, or a silicon film with a conductive coating (plating) layer on the surface. Such a conductive block can be formed at low cost by using a mature manufacturing process. The disclosed EMI shielding packaging structure may also include a plurality of grounding wires that electrically connect the edge of the conductive top block and the base substrate or frame at a ground level. The grounding wire may have a relatively short length to reduce the influence of contact resistance, and the grounding wire may be manufactured by using a mature manufacturing process without the need for a special device. The conductive top block, the plurality of grounding wires, and the base substrate or frame may form a Faraday cage to electromagnetically shield the tube core or tube core stack located in the Faraday cage. Since the Faraday cage is embedded in the packaging structure, it can be protected by the molding compound layer of the packaging structure to avoid potential damage. In addition, the disclosed EMI shielding packaging structure is simple in design and has a low product cost.

[0055] refer to Figure 1 , a schematic diagram illustrating a perspective side view of an example semiconductor device structure according to some embodiments of the present disclosure.

[0056] As shown, semiconductor device structure 100 may include base substrate 110. Base substrate 110 may be any suitable semiconductor substrate having any suitable structure, such as a single crystal single layer substrate, a polycrystalline silicon (polycrystalline silicon) single layer substrate, a polycrystalline silicon and metal multilayer substrate, etc.

[0057] The die / die stack 120 may be attached to the base substrate by a first adhesive film 125. In some embodiments, the die / die stack 120 may be any suitable semiconductor die / die stack that is sensitive to high frequency electromagnetic signals (e.g., input / output signals greater than 1 GHz), and thus requires EMI protection. The first adhesive film 125 may be any suitable die attach film (DAF).

[0058] The semiconductor device structure 100 may further include a conductive top block 130 attached to the top surface of the die / die stack 120 by a second adhesive film 135. Figure 1 As shown, in a plane substantially parallel to the main surface of the substrate, the size of the conductive top block 130 may be slightly larger than the size of the die / die stack 120. That is, the conductive top block 130 may completely cover the top surface of the die / die stack 120.

[0059] refer to Figure 2A and Figure 2B , a schematic diagram showing a perspective side view of an exemplary conductive top block according to some embodiments of the present disclosure. Figure 2C , a schematic diagram showing a top view of an exemplary conductive top block according to some embodiments of the present disclosure.

[0060] In such Figure 2A In some embodiments shown, the conductive top block 200-1 may include a conductive plate 220. The conductive plate 220 may include any suitable conductive material, such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof, and / or other materials known to those skilled in the art. In some embodiments, the conductive plate 220 may also include a binder to allow the internal metal particles to bond to each other. In other embodiments, the conductive plate 220 may include a conductive polymer doped with a metal or metal oxide, such as polyacetylene, polyaniline, polypyrrole, polythiophene, or polysulfur nitride. The thickness of the conductive plate 220 may be in the range from about 20 micrometers (μm) to about 100 μm (e.g., 40 μm or 60 μm).

[0061] The insulating layer 230 may cover the top surface of the conductive plate 220. The insulating layer 230 may include any suitable dielectric material, such as silicon dioxide (SiO2) or silicon nitride (SiN x ). A plurality of bonding pads (or contact pads, redistribution pads, or similar structures known to those skilled in the art) 235 may be embedded in the insulating layer 230 and electrically contact the conductive plate 220 to improve wire bonding. The thickness of the bonding pads 235 may be in a range from about 0.5 μm to about 1 μm (e.g., 0.8 μm). The plurality of bonding pads 235 may be formed by a plating process or a sputtering process.

[0062] In such Figure 2BIn some other embodiments shown, the conductive top block 200-2 may include a silicon wafer 210 having a conductive film 240 on the top surface of the silicon wafer 210. In some embodiments, the conductive film 240 may be a metal film formed by spin coating, spray coating, plating, sputtering, combinations thereof, and / or other process techniques known to those skilled in the art. The conductive film 240 may include any suitable conductive material, such as Cu, Ni, Au, Ag, Pt, Co, Ti, Cr, Zr, Mo, Ru, Hf, W, Re, graphite, carbon black, combinations thereof, and / or other materials known to those skilled in the art. In addition, the conductive film 240 may include a conductive ink prepared by mixing conductive materials such as carbon black, graphite, silver, etc. The thickness of the conductive film 240 may be in the range from about 1 μm to about 20 μm (e.g., 5 μm or 10 μm).

[0063] Similarly, the insulating layer 230 may cover the top surface of the conductive film 240. The insulating layer 230 may include any suitable dielectric material, such as silicon dioxide (SiO2) or silicon nitride (SiN x ). Similarly, a plurality of bonding pads 235 may be embedded in the insulating layer 230 and electrically contact the conductive film 240 to improve wire bonding. The thickness of the bonding pad 235 may be in the range from about 0.5 μm to about 1 μm (e.g., 0.8 μm). The plurality of bonding pads 235 may be formed by a plating process or a sputtering process.

[0064] like Figure 2C As shown, a plurality of bonding pads 235 can be positioned adjacent to all edges of the conductive top block. The bonding pad spacing defined by the distance between adjacent bonding pads 235 can be predetermined by the electromagnetic signal frequency range that needs to be shielded. Corresponding to a higher electromagnetic signal frequency range, a smaller bonding pad spacing can be used. In some embodiments, the bonding pad spacing can be in the range of from about 50 μm to about 5 millimeters (mm).

[0065] Return to reference Figure 1 The semiconductor device structure 100 may further include a plurality of signal lines 128 electrically connecting the top surface of the die / die stack 120 with the base substrate 110. In some embodiments, the second adhesive film 135 may be any suitable film on wire (FOW), and the plurality of signal lines 128 may be formed as follows. Figure 1 Shown penetrating FOW.

[0066] In some embodiments, the semiconductor device structure 100 may further include a plurality of grounding lines 138 conductively connecting the top surface of the conductive top block 130 and the base substrate 110. In some embodiments, each of the plurality of grounding lines 138 may be conductively connected to the above combination. Figure 2A-2CSince the plurality of bonding pads 235 are positioned adjacent to all edges of the conductive top block 130, as shown in FIG. Figure 2C As shown, the plurality of ground lines 138 may surround the conductive top block 130 and the die / die stack 120. The term "surrounding" is intended to indicate that the ground lines are disposed on all sides of the layers 120, 125, 130, and 135. Thus, the conductive top block 130, the plurality of ground lines 138, and the base substrate 110 may form a Faraday cage to electromagnetically enclose the die / die stack 120 that requires EMI protection.

[0067] In addition, the semiconductor device structure 100 may include a molding compound layer 140 on the base substrate 110, so that the tube core / die stack 120, the conductive top block 130, the plurality of signal lines 128 and the ground line 138 are completely embedded in the molding compound layer 140 of the finished package. In some embodiments, the molding compound layer 140 can be a heat-curable epoxy molding compound or a heat-curable epoxy molding resin. For example, the molding compound layer 140 includes an inorganic filler (e.g., silicon dioxide), an epoxy resin, a curing agent, a flame retardant, a curing accelerator, a release agent, and any other suitable components known to those skilled in the art. In some embodiments, a plurality of solder balls 150 can be attached to the bottom surface of the base substrate 110. It should be noted that the semiconductor device structure 100 may also include Figure 1 Any other suitable components not shown.

[0068] refer to Figure 3 , shows a flowchart of an exemplary method for forming an electromagnetic interference shielding packaging structure according to some embodiments of the present disclosure. It should be understood that Figure 3 The operations and / or steps shown in the drawings are not exhaustive, and other operations may be performed before, after, or between any shown operations.

[0069] like Figure 3 As shown, method 300 begins at operation 310, where a die / die stack may be attached to a base substrate using any suitable adhesive or fastening means known in the art. Figure 1 In some embodiments shown, a first adhesive film 125 (e.g., a die attach film (DAF)) may be attached to the bottom surface of the die / die stack 120. The die / die stack 120 may then be permanently attached or fixed to the top surface of the base substrate 110 by the DAF 125.

[0070] Method 300 may proceed to operation 320 where a plurality of signal lines may be formed to electrically connect the die / die stack and the base substrate. Figure 1A single die is shown as an example. In this example, a plurality of signal lines 128 are formed to connect a plurality of signal pads (not shown) on the top surface of the die to the base substrate 110, respectively. Figure 1 In some other embodiments not shown in the figure, the die stack may include multiple die layers stacked in a vertical direction. In this case, the plurality of signal lines 128 may include groups of signal lines connecting multiple signal pads and / or redistribution pads on each layer of the die stack.

[0071] Return to reference Figure 3 , method 300 may proceed to operation 330, where a conductive top block may be attached to the top surface of the die / die stack by using any suitable adhesive or fastening means known in the art. The conductive top block may be, for example, Figure 2A The conductive plate shown, or Figure 2B A silicon wafer with a conductive film attached is shown. In some embodiments, in a horizontal plane, the size of the conductive top block can be slightly larger than the size of the die / die stack, so that the conductive top block can completely cover the top surface of the die / die stack.

[0072] In some embodiments, forming Figure 2A The process of the conductive top block 200-1 shown may include forming a conductive plate, forming an insulating layer covering the top surface of the conductive plate, and forming a plurality of bonding pads in the insulating layer. The conductive plate may be formed by using any suitable conductive material, such as Cu, Ni, Au, Ag, Pt, Co, Ti, Cr, Zr, Mo, Ru, Hf, W, Re, graphite, carbon black, or any suitable combination thereof. The thickness of the formed conductive plate may be in the range from about 20 μm to about 100 μm, for example, the thickness of the formed conductive plate may be 40 μm or 70 μm. The insulating layer may be formed by using any suitable dielectric material, such as silicon dioxide (SiO2) or silicon nitride (SiN x ). A plurality of bonding pads may be formed in the insulating layer by a plating process or a sputtering process and adjacent to all edges of the conductive top block. In some embodiments, the thickness of the formed bonding pads may be in a range from about 0.5 μm to about 1 μm (e.g., 0.8 μm), and the bonding pad spacing between adjacent bonding pads may be in a range from about 50 μm to about 5 mm (e.g., 100 μm).

[0073] In some other embodiments, such as Figure 2BThe process of forming the conductive top block 200-2 shown may include forming a conductive film 240 on the top surface of the silicon wafer 210, forming an insulating layer 230 covering the top surface of the conductive film 240, and forming a plurality of bonding pads 235 in the insulating layer 240. The conductive film 240 may be formed by spin coating, spray coating, plating, sputtering, or any other suitable process and using any suitable conductive material, such as Cu, Ni, Au, Ag, Pt, Co, Ti, Cr, Zr, Mo, Ru, Hf, W, Re, graphite, carbon black, or a conductive ink prepared by mixing the above conductive materials. The thickness of the formed conductive film may be in the range from about 1 μm to about 20 μm (e.g., 5 μm or 15 μm). The conductive film 240 may be formed by using any suitable dielectric material (e.g., silicon dioxide (SiO2) or silicon nitride (SiN x )) to form the insulating layer 230. A plurality of bonding pads 235 may be formed in the insulating layer 230 by a plating process or a sputtering process and adjacent to all edges of the conductive top block. In some embodiments, the thickness of the formed bonding pads 235 may be in the range from about 0.5 μm to about 1 μm, and the bonding pad spacing between adjacent bonding pads may be in the range from about 50 μm to about 5 mm.

[0074] exist Figure 1 In some embodiments shown, a second adhesive film 135 (e.g., film on wire (FOW)) may be attached to the bottom surface of the conductive top block 130. The conductive top block 130 may then be permanently attached or fixed to the top surface of the die / die stack 120 via the FOW 135. Portions of the signal lines 128 may partially penetrate or pass through the FOW 135.

[0075] Return to reference Figure 3 , method 300 may proceed to operation 330, where a plurality of grounding lines conductively connect the top surface of the conductive top block and the base substrate. In some embodiments, each of the plurality of grounding lines may be formed to conductively connect between a corresponding bonding pad on the top surface of the conductive top block and the base substrate. Since the plurality of bonding pads may be as Figure 2C The ground is shown arranged adjacent to all edges of the conductive top block, so multiple ground lines can be formed around the conductive top block and the die / die stack. Thus, the conductive top block, the multiple ground lines and the base substrate can form a Faraday cage to electromagnetically enclose the die / die stack that requires EMI protection.

[0076] The method 300 may proceed to operation 340, where a molding compound layer is formed on the base substrate to cover the die / die stack, the conductive top block, the plurality of signal lines, and the ground line. In some embodiments, the molding compound layer may be formed of any suitable material, such as a heat-curable epoxy molding compound material or a heat-curable epoxy molding resin. For example, the molding compound layer may be formed by using an inorganic filler (e.g., silicon dioxide), an epoxy resin, a curing agent, a flame retardant, a curing accelerator, a release agent, and any other suitable components known to those skilled in the art.

[0077] The method 300 may then proceed to operation 350 where a plurality of solder balls may be formed to attach to the bottom surface of the base substrate.

[0078] refer to Figure 4A and Figure 4B , a schematic diagram showing a perspective side view and a top view of another example semiconductor device structure according to some embodiments of the present disclosure. Figure 4A and Figure 4B As shown, the semiconductor device structure 400 may include one or more EMI shielding structures 460 and one or more dies / die stacks 480 without EMI shielding located on one side of the one or more EMI shielding structures 460 .

[0079] In some embodiments, the structure and manufacturing process of one or more EMI shielding structures 460 can refer to the above combined Figure 1 , Figure 2A-2C and Figure 3 Description of. In some embodiments, one or more dies / die stacks 480 without EMI shielding may be formed while forming a die / die stack 120 requiring EMI shielding. Signal line 428 may be formed while forming signal line 128 or ground line 138. In some other embodiments, one or more dies / die stacks 480 without EMI shielding may be formed before or after forming die / die stack 120 and / or conductive top block 130. In an example, the die in one or more dies / die stacks 480 may be a three-dimensional NAND flash memory device, and the die in die / die stack 120 may be a memory controller for controlling the three-dimensional NAND flash memory device.

[0080] refer to Figure 4B, two EMI shielding structures 460 are formed in the semiconductor device structure to protect two groups of tube dies / tube die stacks, and two tube dies / tube die stacks 480 without EMI shielding requirements can be excluded from the EMI shielding structure. It should be noted that the number of EMI shielding structures 460 and tube dies / tube die stacks 480 and the positions of EMI shielding structures 460 and tube dies / tube die stacks 480 can be arranged and adjusted based on actual needs without being affected by Figure 4B Limitations. Figure 4A and Figure 4B In this example, one or more EMI shielding structures can be partially allocated in the finished package while retaining the rest of the die / die stack without EMI shielding requirements to balance the needs between performance and cost.

[0081] refer to Figure 5 , a schematic diagram showing a perspective side view of another exemplary semiconductor device structure according to some embodiments of the present disclosure. Figure 4A and Figure 4B The example shown in Figure 5 In the semiconductor device structure 500 shown, a die / die stack 480 without EMI shielding can be formed on the top surface of the EMI shielding structure 460 to reduce the size of the semiconductor device structure 500 in the horizontal plane. It should be noted that one or more dies 420 and the conductive top block 130 can be attached to the lower layer by using a wire film (FOW) 135 to allow partial penetration of signal lines or ground lines. In this design, the EMI shielding portion is placed at the bottom portion of the package, while the upper portion of the package is used for more die stacking, which can increase the overall space utilization.

[0082] Therefore, various embodiments of an electromagnetic interference shielding packaging structure and a method for manufacturing the same are disclosed. In the disclosed EMI packaging structure, a conductive top block can be formed on a die / die stack that requires EMI shielding. A plurality of ground wires can be formed to conductively connect the edge of the conductive top block and the base substrate. The conductive top block, the plurality of ground wires, and the base substrate can form a Faraday cage to electromagnetically shield the die / die stack located within the Faraday cage. Since the Faraday cage is embedded in the packaging structure, it can be protected by the molding compound layer of the packaging structure to avoid potential damage. In some embodiments, one or more dies / die stacks 480 without EMI shielding can be formed on the side or top of the conductive top block. The disclosed EMI shielding packaging structure is simple in design and has a low product cost.

[0083] One aspect of the present disclosure provides a semiconductor structure, comprising: a first die / die stack attached to a substrate, a conductive top block covering a top surface of the first die / die stack, and a plurality of ground lines conductively connecting the conductive top block to the substrate. The conductive top block, the plurality of ground lines, and the substrate form a Faraday cage to provide electromagnetic interference shielding for the first die / die stack.

[0084] In some embodiments, the plurality of ground lines surround the first die / die stack.

[0085] In some embodiments, in a plane substantially parallel to the main surface of the substrate, the size of the conductive top block is larger than the size of the first die / die stack such that the top surface of the first die / die stack is completely covered by the conductive top block.

[0086] In some embodiments, the semiconductor structure further includes a molding compound layer on the substrate and covering the conductive top block and the plurality of ground lines, and a plurality of solder balls attached to a bottom surface of the substrate.

[0087] In some embodiments, the conductive top block includes a conductive plate having a thickness between about 20 μm and about 100 μm, an insulating layer covering a top surface of the conductive plate, and a plurality of bonding pads embedded in the insulating layer and in electrical contact with the conductive plate.

[0088] In some embodiments, the conductive plate is a metal plate or a conductive polymer plate doped with a metal or a metal oxide.

[0089] In some embodiments, the plurality of bond pads are positioned adjacent to all edges of the conductive top block and have a thickness between about 0.5 μm and about 1 μm, and have a bond pad pitch between about 50 μm and about 5 mm.

[0090] In some embodiments, the conductive top block includes a conductive film on the top surface of the silicon wafer, an insulating layer covering the top surface of the conductive film, and a plurality of bonding pads embedded in the insulating layer and electrically contacting the conductive film, wherein the thickness of the conductive film is in a range from about 1 μm to about 20 μm.

[0091] In some embodiments, the conductive film is a metal film or a conductive ink film.

[0092] In some embodiments, the first die / die stack is attached to the substrate by a first adhesive film, and the conductive top block is attached to the top surface of the first die / die stack by a second adhesive film different from the first adhesive film.

[0093] In some embodiments, the first adhesive film is a die attach film, and the second adhesive film is a wire cover film penetrated by a plurality of signal lines of the die / die stack.

[0094] In some embodiments, the semiconductor structure further includes a second die / die stack without EMI protection.

[0095] In some embodiments, the second die / die stack is located on one side of the first die / die stack in a lateral direction.

[0096] In some embodiments, the second die / die stack includes a three-dimensional NAND flash memory device, and the first die / die stack includes a memory controller for controlling the three-dimensional NAND flash memory device.

[0097] In some embodiments, the second die / die stack is located on the top surface of the conductive top block.

[0098] Another aspect of the present disclosure provides a method of forming a semiconductor structure, comprising: attaching a first tube die / die stack on a substrate; forming a conductive top block having a size larger than the first tube die / die stack; attaching the conductive top block to cover the top surface of the first tube die / die stack; and forming a plurality of ground lines conductively connecting the conductive top block and the substrate, so that the conductive top block, the plurality of ground lines and the substrate form a Faraday cage to provide electromagnetic interference shielding for the first tube die / die stack.

[0099] In some embodiments, forming the plurality of ground lines includes forming the plurality of ground lines around the first die / die stack.

[0100] In some embodiments, the method further includes: forming a molding compound layer on the substrate to cover the conductive top block and the plurality of ground lines; and attaching a plurality of solder balls to a bottom surface of the substrate.

[0101] In some embodiments, forming a conductive top block includes: forming a conductive plate having a thickness between about 20 μm and about 100 μm; forming an insulating layer covering a top surface of the conductive plate; and forming a plurality of bonding pads having a thickness between about 0.5 μm and about 1 μm embedded in the insulating layer and in electrical contact with the conductive plate.

[0102] In some embodiments, the method further includes arranging the plurality of bonding pads adjacent to all edges of the conductive top block and having a bonding pad pitch between about 50 μm and about 5 mm.

[0103] In some embodiments, the method further includes: forming a conductive film on the top surface of the silicon wafer by spin coating, spraying, plating or sputtering, wherein the thickness of the conductive film is in a range from about 1 μm to about 20 μm; forming an insulating layer covering the top surface of the conductive film; and forming a plurality of bonding pads with a thickness between about 0.5 μm and about 1 μm embedded in the insulating layer and electrically contacting the conductive film.

[0104] In some embodiments, the method further includes forming at least one signal line connecting the first die / die stack to the substrate, wherein a portion of the at least one signal line penetrates a second adhesive film for attaching the conductive top block.

[0105] In some embodiments, the method further includes forming a second die / die stack without EMI protection located on a side of the first die / die stack in a lateral direction.

[0106] In some embodiments, the method further includes forming a second die / die stack without EMI protection on the top surface of the conductive top block.

[0107] The above description of the specific embodiments will fully reveal the overall nature of the present invention so that others can easily modify and / or change these specific embodiments by applying the knowledge in the art to be suitable for various applications without excessive experimentation and without departing from the overall concept of the present disclosure. Therefore, based on the disclosure and guidance given herein, these changes and modifications are intended to be within the meaning and scope of the equivalent transformations of the disclosed embodiments. It should be understood that the wording or terminology herein is for descriptive purposes rather than for limiting purposes, so that the terms or wording of this specification will be interpreted by those skilled in the art based on the disclosure and guidance.

[0108] The embodiments of the present disclosure have been described above with the aid of functional building blocks, which illustrate implementations of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks are arbitrarily defined herein. As long as the specific functions and their relationships are properly performed, replaceable boundaries may be defined.

[0109] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by one or more inventors, and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0110] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor structure comprising: A substrate, a first die / die stack, and a conductive top block stacked in a first direction; a plurality of grounding lines connecting the conductive top block and the substrate; A plurality of signal lines connecting the first die / die stack and the substrate; a molding compound layer in contact with sidewalls of the first die / die stack in a second direction; a first adhesive film disposed between the substrate and the first die / die stack; as well as a second adhesive film located between the first die / die stack and the conductive top block and in contact with the first die / die stack, wherein the first tube die / tube die stack is located between the substrate and the conductive top block, wherein a portion of at least one of the signal lines passes through the second adhesive film, The first direction is perpendicular to the second direction.

2. The semiconductor structure according to claim 1, wherein: The conductive top block, the plurality of ground wires, and the substrate form a Faraday cage.

3. The semiconductor structure according to claim 1, wherein: The plurality of ground lines surround the first die / die stack.

4. The semiconductor structure according to claim 1, wherein: Along the second direction, the size of the conductive top block is larger than the size of the first die / die stack.

5. The semiconductor structure according to claim 1, further comprising: a plurality of solder balls attached to the bottom surface of the substrate, wherein the substrate comprises a top surface and a bottom surface disposed opposite to each other along the first direction, the molding compound layer is located on the top surface and covers the conductive top block and the plurality of grounding lines, Wherein, a plurality of the solder balls are attached to the bottom surface.

6. The semiconductor structure according to claim 1, wherein: The conductive top block comprises: a conductive layer and an insulating layer arranged along the first direction; and a plurality of bonding pads embedded in the insulating layer and in electrical contact with the conductive layer, Wherein, the insulating layer is located on a side of the conductive layer away from the substrate.

7. The semiconductor structure according to claim 6, wherein: The conductive layer includes at least one of a metal plate, a conductive polymer plate doped with a metal or a metal oxide, a metal film, and a conductive ink film.

8. The semiconductor structure according to claim 6, wherein: The plurality of bonding pads are positioned adjacent to all edges of the conductive top block, and the plurality of ground lines connect the conductive top block and the substrate through the plurality of bonding pads.

9. The semiconductor structure according to claim 6, wherein: The pad distance between two adjacent bonding pads is between 50 μm and 5 mm.

10. The semiconductor structure according to claim 6, wherein: The bonding pad spacing between two adjacent bonding pads is predetermined according to the frequency range of electromagnetic signals to be shielded by the first die / die stack.

11. The semiconductor structure of claim 10, wherein: The first adhesive film comprises a die attach film; and The second adhesive film includes a wire covered film.

12. The semiconductor structure of claim 1, further comprising: A second tube die / die stack is located on one side of the first tube die / die stack in the second direction.

13. The semiconductor structure according to claim 12, wherein: The second die / die stack includes a three-dimensional NAND flash memory device, and the first die / die stack includes a memory controller for controlling the three-dimensional NAND flash memory device.

14. A semiconductor structure comprising: A substrate, a first die / die stack, a conductive top block, and a second die / die stack stacked in a first direction; a plurality of grounding lines connecting the conductive top block and the substrate; A plurality of signal lines connecting the first die / die stack and the substrate; a first adhesive film disposed between the substrate and the first die / die stack; as well as a second adhesive film located between the first die / die stack and the conductive top block and in contact with the first die / die stack, wherein a portion of at least one of the signal lines passes through the second adhesive film, The first tube die / tube stack is located between the substrate and the conductive top block, and the second tube die / tube stack is located on a side of the conductive top block away from the first tube die / tube stack.

15. The semiconductor structure according to claim 14, further comprising, A molding compound layer covers the conductive top block and the plurality of ground lines and contacts the sidewalls of the first die / die stack in a second direction, the first direction being perpendicular to the second direction.

16. The semiconductor structure according to claim 14, wherein: The conductive top block, the plurality of ground wires, and the substrate form a Faraday cage.

17. The semiconductor structure according to claim 14, wherein: The plurality of ground lines surround the first die / die stack.

18. The semiconductor structure according to claim 14, wherein: The conductive top block comprises: a conductive layer and an insulating layer arranged along the first direction; and a plurality of bonding pads embedded in the insulating layer and in electrical contact with the conductive layer, Wherein, the insulating layer is located on a side of the conductive layer away from the substrate.

19. The semiconductor decomposition structure according to claim 18, wherein: The bonding pad spacing between two adjacent bonding pads is predetermined according to the frequency range of electromagnetic signals to be shielded by the first die / die stack.

20. The semiconductor structure of claim 14, wherein: The first adhesive film comprises a die attach film; and The second adhesive film includes a wire covered film.

21. The semiconductor structure of claim 14, wherein: The second die / die stack includes a three-dimensional NAND flash memory device, and the first die / die stack includes a memory controller for controlling the three-dimensional NAND flash memory device.

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