VCSEL light emitting point, VCSEL array, optical apparatus, and method of manufacturing VCSEL device

Abstract

The invention discloses a VCSEL light emitting point, a VCSEL array, optical equipment and a manufacturing method of a VCSEL device. The VCSEL luminous point comprises a luminous point main body, a VCSEL anode and a VCSEL cathode. The luminous point main body comprises a substrate layer, a bottom mirror part, an active region, a main limiting layer, a top mirror part and an electrode contact layer; wherein the bottom mirror part comprises a bottom N-DBR layer, a bottom limiting layer and a bottom tunnel junction; wherein the bottom N-DBR layer is formed on the substrate layer, and the bottom limiting layer and the bottom tunnel junction are stacked on the bottom N-DBR layer; the active region and the main limiting layer are located between the bottom mirror part and the top mirror part; the electrode contact layer is formed on the top mirror portion. The VCSEL anode comprises a first N-type metal layer, and the first N-type metal layer is formed on the N-type substrate layer. The VCSEL cathode comprises an electrode metal layer, and the electrode metal layer is formed on the electrode contact layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor lasers, and more specifically to a VCSEL light emitting point, a VCSEL array, an optical device, and a manufacturing method of a VCSEL device. Background Art

[0002] VCSEL (Vertical-Cavity Surface-Emitting Laser) is a semiconductor laser that emits laser light in a direction perpendicular to its substrate. VCSEL has the characteristics of small divergence angle, symmetrical beam, high wavelength thermal stability, and stable beam quality. It has great application potential in the fields of communications, consumption, and automotive. At present, VCSEL products have been widely used in industries such as short-distance fiber-optic communications, face recognition, and 3D sensing.

[0003] In a typical VCSEL structure, such as Figure 1 As shown, the VCSEL includes, from bottom to top, an N-type metal electrode layer, an N-type substrate layer, an N-type Bragg reflector, an active region, a confinement layer, a P-type Bragg reflector, a P-type contact layer and a P-type metal electrode layer.

[0004] The area where the N-type substrate layer and the N-type Bragg reflector are located is the N-type area, and the area where the P-type Bragg reflector is located is the P-type area. In the N-type area, free electrons are majority carriers, and holes are almost zero, which are minority carriers; in the P-type area, holes are majority carriers, and free electrons are minority carriers. Accordingly, a concentration difference between electrons and holes appears at the junction of the N-type area and the P-type area. Furthermore, in a typical VCSEL structure, the P-type metal electrode layer forms the anode of the VCSEL, and the N-type metal electrode layer forms the cathode of the VCSEL.

[0005] In a typical VCSEL application, multiple VCSELs form a VCSEL array. Usually, multiple VCSELs share an N-type substrate and an N-type metal electrode layer, that is, multiple VCSELs share a cathode. However, in some application scenarios of VCSELs, it is desired that the VCSEL array formed by multiple VCSELs share an anode and a substrate layer.

[0006] Theoretically, the N-type substrate layer can be replaced with a P-type substrate layer, the positions of the N-type Bragg reflector and the P-type Bragg reflector can be swapped, the positions of the N-type metal electrode layer and the P-type metal electrode layer can be swapped, and the P-type contact layer can be adjusted to an N-type contact layer. That is, the structure of the VCSEL is adjusted to include, from bottom to top, a P-type metal electrode layer, a P-type substrate layer, a P-type Bragg reflector, an active region, a confinement layer, an N-type Bragg reflector, an N-type contact layer, and an N-type metal electrode layer.

[0007] However, the P-type substrate layer has a high defect density, a high resistivity, and a low yield. Therefore, the above VCSEL structural adjustment scheme is hindered in practical applications, and a new VCSEL structural design scheme needs to be proposed. Summary of the invention

[0008] One advantage of the present application is that it provides a VCSEL light-emitting point and a VCSEL array as well as a method for manufacturing an optical device and a VCSEL device, wherein the structure of the VCSEL light-emitting point is suitable for a common anode VCSEL array, and the substrate layer is kept as an N-type substrate layer.

[0009] In order to achieve at least one of the above advantages or other advantages and purposes, according to one aspect of the present application, a VCSEL light-emitting point is provided, which includes: A light-emitting point body, the light-emitting point body comprising: substrate layer; A bottom mirror portion, the bottom mirror portion is formed on the substrate layer, the bottom mirror portion comprises a bottom N-DBR layer, a bottom confinement layer and a bottom tunnel junction; wherein the bottom N-DBR layer is formed on the substrate layer, the bottom confinement layer and the bottom tunnel junction are stacked on the bottom N-DBR layer; a top mirror portion, the top mirror portion comprising at least one top DBR layer; an active region located between the bottom mirror portion and the top mirror portion; a main confining layer located between the bottom mirror portion and the top mirror portion; and an electrode contact layer formed on the top mirror portion; A VCSEL anode, the VCSEL anode comprising a first N-type metal layer, wherein the first N-type metal layer is formed on the substrate layer; A VCSEL cathode comprises an electrode metal layer formed on the electrode contact layer.

[0010] In one embodiment of the VCSEL light-emitting point according to the present application, the active region includes at least one PN junction.

[0011] In one embodiment of the VCSEL light-emitting point according to the present application, the bottom confinement layer and the bottom tunnel junction are located above the bottom N-DBR layer, and the bottom confinement layer is located between the bottom tunnel junction and the bottom N-DBR layer.

[0012] In one embodiment of the VCSEL light-emitting point according to the present application, the main confinement layer is located above and / or below the active region.

[0013] In one embodiment of the VCSEL light-emitting point according to the present application, the top DBR layer is a top N-DBR layer.

[0014] In one embodiment of the VCSEL light-emitting point according to the present application, the electrode contact layer of the VCSEL cathode is an N-type electrode contact layer, and the electrode metal layer is a second N-type metal layer.

[0015] In one embodiment of the VCSEL light-emitting point according to the present application, the substrate layer is an N-type substrate layer, and the first N-type metal layer is formed below the substrate layer.

[0016] In one embodiment of the VCSEL light-emitting point according to the present application, the first N-type metal layer is located above the substrate layer, and the VCSEL anode also includes an N-type metal extension layer, which extends from the first N-type metal layer to below the substrate layer, and the N-type metal extension layer is made of a metal material.

[0017] According to another aspect of the present application, a VCSEL array is provided, which includes: two or more VCSEL light-emitting points, wherein the VCSEL light-emitting points include: A light-emitting point body, the light-emitting point body comprising: substrate layer; A bottom mirror portion, the bottom mirror portion is formed on the substrate layer, the bottom mirror portion comprises a bottom N-DBR layer, a bottom confinement layer and a bottom tunnel junction; wherein the bottom N-DBR layer is formed on the substrate layer, the bottom confinement layer and the bottom tunnel junction are stacked on the bottom N-DBR layer; a top mirror portion, the top mirror portion comprising at least one top DBR layer; an active region located between the bottom mirror portion and the top mirror portion; a main confining layer located between the bottom mirror portion and the top mirror portion; and an electrode contact layer formed on the top mirror portion; A VCSEL anode, the VCSEL anode comprising a first N-type metal layer, wherein the first N-type metal layer is formed on the substrate layer; A VCSEL cathode, wherein the VCSEL cathode comprises an electrode metal layer, and the electrode metal layer is formed on the electrode contact layer; Wherein, the VCSEL anode of two or more VCSEL light-emitting points is shared.

[0018] In one embodiment of the VCSEL array according to the present application, the bottom confinement layer and the bottom tunnel junction are located above the bottom N-DBR layer, and the bottom confinement layer is located between the bottom tunnel junction and the bottom N-DBR layer.

[0019] In one embodiment of the VCSEL array according to the present application, the main confinement layer is located above and / or below the active region.

[0020] In one embodiment of the VCSEL array according to the present application, the top DBR layer is a top N-DBR layer.

[0021] In one embodiment of the VCSEL array according to the present application, the electrode contact layer of the VCSEL cathode is an N-type electrode contact layer, and the electrode metal layer is a second N-type metal layer.

[0022] In one embodiment of the VCSEL array according to the present application, the substrate layer is an N-type substrate layer, and the first N-type metal layer is formed below the substrate layer.

[0023] In one embodiment of the VCSEL array according to the present application, the first N-type metal layer is located above the substrate layer, and the VCSEL anode also includes an N-type metal extension layer, which extends from the first N-type metal layer to below the substrate layer, and the N-type metal extension layer is made of a metal material.

[0024] In one embodiment of the VCSEL array according to the present application, the active region includes at least one PN junction.

[0025] According to another aspect of the present application, an optical device is provided, comprising: at least one VCSEL array, wherein the VCSEL array comprises: two or more VCSEL light emitting points, wherein the VCSEL light emitting points comprise: A light-emitting point body, the light-emitting point body comprising: substrate layer; A bottom mirror portion, the bottom mirror portion is formed on the substrate layer, the bottom mirror portion comprises a bottom N-DBR layer, a bottom confinement layer and a bottom tunnel junction; wherein the bottom N-DBR layer is formed on the substrate layer, the bottom confinement layer and the bottom tunnel junction are stacked on the bottom N-DBR layer; a top mirror portion, the top mirror portion comprising at least one top DBR layer; an active region located between the bottom mirror portion and the top mirror portion; a main confining layer located between the bottom mirror portion and the top mirror portion; and an electrode contact layer formed on the top mirror portion; A VCSEL anode, the VCSEL anode comprising a first N-type metal layer, wherein the first N-type metal layer is formed on the substrate layer; A VCSEL cathode, wherein the VCSEL cathode comprises an electrode metal layer, and the electrode metal layer is formed on the electrode contact layer; Wherein, the VCSEL anode of two or more VCSEL light-emitting points is shared.

[0026] According to another aspect of the present application, a method for manufacturing a VCSEL device is provided, comprising: A light-emitting point body is formed, the light-emitting point body comprising: a substrate layer, a bottom mirror portion, an active region, a main limiting layer, a top mirror portion and an electrode contact layer; wherein the bottom mirror portion is formed on the substrate layer, the bottom mirror portion comprises a bottom N-DBR layer, a bottom limiting layer and a bottom tunnel junction; the bottom N-DBR layer is formed on the substrate layer, the bottom limiting layer and the bottom tunnel junction are stacked on the bottom N-DBR layer; the top mirror portion comprises at least one top DBR layer; the active region is located between the bottom mirror portion and the top mirror portion; the main limiting layer is located between the bottom mirror portion and the top mirror portion; the electrode contact layer is formed on the top mirror portion; forming a VCSEL cathode, the VCSEL cathode comprising an electrode metal layer, the electrode metal layer being formed on the electrode contact layer; and A VCSEL anode is formed, wherein the VCSEL anode includes a first N-type metal layer formed on the substrate layer.

[0027] Further objectives and advantages of the present application will be fully reflected through understanding of the following description and drawings.

[0028] These and other objects, features and advantages of the present application are fully reflected in the following detailed description, drawings and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] These and / or other aspects and advantages of the present application will become clearer and easier to understand from the following detailed description of the embodiments of the present application in conjunction with the accompanying drawings, in which: Figure 1 A schematic diagram of a typical VCSEL structure is shown.

[0030] Figure 2 The figure shows a schematic diagram of the structural layer arrangement of an implementation of a VCSEL light-emitting point according to an embodiment of the present application.

[0031] Figure 3FIG. 1 is a cross-sectional schematic diagram of an implementation of a VCSEL light-emitting point according to an embodiment of the present application.

[0032] Figure 4 FIG. 4 is a cross-sectional schematic diagram of another implementation of a VCSEL light-emitting point according to an embodiment of the present application.

[0033] Figure 5 FIG. 4 is a schematic diagram of a VCSEL array according to an embodiment of the present application.

[0034] Figure 6 FIG. 4 is a partial schematic diagram of a VCSEL array according to an embodiment of the present application.

[0035] Figure 7 FIG. 1 is a partial schematic diagram of a VCSEL device according to an embodiment of the present application.

[0036] Figure 8 The figure shows a schematic flow chart of a manufacturing process of a VCSEL device according to an embodiment of the present application.

[0037] Fig. 9 FIG. 1 is a schematic diagram of a manufacturing process of a VCSEL integrated wafer according to an embodiment of the present application.

[0038] Fig.10 FIG2 is a second schematic diagram of a manufacturing process of a VCSEL integrated wafer according to an embodiment of the present application. DETAILED DESCRIPTION

[0039] The terms and words used in the following specification and claims are not limited to the literal meanings, but are merely used by the inventor to enable a clear and consistent understanding of the present application. Therefore, it will be apparent to those skilled in the art that the following description of various embodiments of the present application is provided for illustration purposes only and not for the purpose of limiting the present application as defined by the appended claims and their equivalents.

[0040] It is to be understood that the term "one" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element may be one, while in another embodiment, the number of the element may be multiple, and the term "one" should not be understood as a limitation on the quantity.

[0041] Although ordinals such as "first," "second," and the like will be used to describe various components, those components are not limited herein. The term is used only to distinguish one component from another. For example, a first component may be referred to as a second component, and likewise, a second component may be referred to as a first component without departing from the teachings of the present application. The term "and / or" as used herein includes any and all combinations of one or more associated listed items.

[0042] The terms used herein are only used for the purpose of describing various embodiments and are not intended to be limiting. As used herein, singular forms are intended to also include plural forms, unless the context clearly indicates an exception. In addition, it will be understood that the terms "including" and / or "having" when used in this specification specify the presence of the described features, numbers, steps, operations, components, elements or combinations thereof, without excluding the presence or addition of one or more other features, numbers, steps, operations, components, elements or groups thereof.

[0043] Application Summary: As mentioned above, in typical VCSEL applications, multiple VCSELs form a VCSEL array. Usually, multiple VCSELs share an N-type substrate and an N-type metal electrode layer, that is, multiple VCSELs share a cathode. However, in some application scenarios of VCSELs, it is expected that the VCSEL array formed by multiple VCSELs shares an anode and a substrate layer.

[0044] Theoretically, the N-type substrate layer can be replaced with a P-type substrate layer, the positions of the N-type Bragg reflector and the P-type Bragg reflector can be swapped, the positions of the N-type metal electrode layer and the P-type metal electrode layer can be swapped, and the P-type contact layer can be adjusted to an N-type contact layer. That is, the structure of the VCSEL is adjusted to include, from bottom to top, a P-type metal electrode layer, a P-type substrate layer, a P-type Bragg reflector, an active region, a confinement layer, an N-type Bragg reflector, an N-type contact layer, and an N-type metal electrode layer.

[0045] However, the P-type substrate layer has a high defect density, a high resistivity, and a low yield. Therefore, the above VCSEL structural adjustment scheme is hindered in practical applications, and a new VCSEL structural design scheme needs to be proposed.

[0046] Under the premise of keeping the substrate layer as an N-type substrate layer, the Bragg reflector formed on the upper surface of the N-type substrate layer also remains an N-type Bragg reflector, and the metal electrode layer stacked on the N-type substrate layer is also an N-type metal electrode layer. However, as mentioned above, in the N-type region, free electrons are majority carriers, and holes are almost zero, which are minority carriers. If an attempt is made to use the N-type metal electrode layer stacked on the N-type substrate layer as an anode, a tunnel junction can be set in the original N-type region to reverse the carrier type in the N-type region.

[0047] Accordingly, according to one aspect of the present application, the present application proposes a VCSEL light-emitting point, which includes: a light-emitting point body, a VCSEL anode and a VCSEL cathode. The light-emitting point body includes: a substrate layer, a bottom mirror part, an active region, a main confinement layer, a top mirror part and an electrode contact layer; wherein the bottom mirror part is formed on the substrate layer, and the bottom mirror part includes a bottom N-DBR layer, a bottom confinement layer and a bottom tunnel junction; wherein the bottom N-DBR layer is formed on the substrate layer, and the bottom confinement layer and the bottom tunnel junction are stacked on the bottom N-DBR layer; the top mirror part includes at least one top DBR layer; the active region is located between the bottom mirror part and the top mirror part; the main confinement layer is located between the bottom mirror part and the top mirror part; the electrode contact layer is formed on the top mirror part. The VCSEL anode includes a first N-type metal layer, and the first N-type metal layer is formed on the N-type substrate layer. The VCSEL cathode includes an electrode metal layer, and the electrode metal layer is formed on the electrode contact layer.

[0048] After introducing the basic principles of the present application, various non-limiting embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0049] Schematic VCSEL luminous point: Figures 2 to 4 As shown, a VCSEL light emitting point 1 according to an embodiment of the present application is illustrated, wherein, as Figure 2 and Figure 3 As shown, the VCSEL light-emitting point 1 includes a light-emitting point body 10, a VCSEL anode 20 and a VCSEL cathode 30. The light-emitting point body 10 includes: a substrate layer 11, a bottom mirror portion 12, an active region 13, a main limiting layer 14, a top mirror portion 15 and an electrode contact layer 16. The bottom mirror portion 12 is formed on the substrate layer 11. The active region 13 is located between the bottom mirror portion 12 and the top mirror portion 15. The main limiting layer 14 is located between the bottom mirror portion 12 and the top mirror portion 15. The electrode contact layer 16 is formed on the top mirror portion 15. The VCSEL anode 20 is stacked on the substrate layer 11, and the VCSEL cathode 30 is formed on the electrode contact layer 16. In practical applications, the VCSEL anode 20 is connected to the positive pole of the power supply, and the VCSEL cathode 30 is connected to the negative pole of the power supply.

[0050] In some embodiments of the present application, the substrate layer 11 is an N-type substrate layer 11 , and the material of the N-type substrate layer 11 may be a doped material such as InP, GaN, or GaAs.

[0051] The bottom mirror portion 12 includes a bottom N-DBR layer 121, a bottom confinement layer 122, and a bottom tunnel junction 123. The bottom N-DBR layer 121 is formed on the N-type substrate layer 11, and the bottom confinement layer 122 and the bottom tunnel junction 123 are stacked on the bottom N-DBR layer 121.

[0052] In one embodiment of the present application, the bottom confinement layer 122 and the bottom tunnel junction 123 are located above the bottom N-DBR layer 121. The bottom confinement layer 122 is located between the bottom tunnel junction 123 and the bottom N-DBR layer 121. That is, the bottom confinement layer 122 is located above the bottom N-DBR layer 121, and the bottom tunnel junction 123 is located above the bottom confinement layer 122.

[0053] In other embodiments of the present application, the bottom confinement layer 122 and the bottom tunnel junction 123 may also be disposed at other locations. For example, the bottom confinement layer 122 and the bottom tunnel junction 123 are located above the bottom N-DBR layer 121, and the bottom tunnel junction 123 is located between the bottom confinement layer 122 and the bottom N-DBR layer 121. That is, the bottom tunnel junction 123 is located above the bottom N-DBR layer 121, and the bottom confinement layer 122 is located above the bottom tunnel junction 123.

[0054] The N-DBR layer is composed of N-type doped Al x Ga 1-x As (x=1~0) and N-type doped low aluminum content Al x Ga 1-x The bottom N-DBR layer 121 refers to the N-DBR layer in the bottom mirror portion 12 .

[0055] The bottom tunnel junction 123 is used to reverse the carrier type of the bottom N-DBR layer 121. For example, the bottom tunnel junction 123 can convert carriers from the bottom N-DBR layer 121 to the P-type semiconductor layer. The tunnel junction is composed of at least one P-type semiconductor layer and at least one N-type semiconductor layer. The tunnel junction can be Al x Ga 1-x As (x=1~0), and the tunnel junction P-type semiconductor layer and N-type semiconductor layer of the tunnel junction are both highly doped (<1e 18 cm -3 ).

[0056] The top mirror portion 15 includes at least one top DBR layer 151. In one embodiment of the present application, the top DBR layer 151 is a top N-DBR layer. The top N-DBR layer refers to the N-DBR layer in the top mirror portion 15. In another embodiment of the present application, the top DBR layer 151 is a top P-DBR layer. The top P-DBR layer refers to the P-DBR layer in the top mirror portion 15. The P-DBR layer is composed of a P-type doped Al with a high aluminum content. x Ga 1-x As (x=1~0) and P-type doped low aluminum content Al x Ga 1-x As (x=1-0) is formed by alternating layers. When the top DBR layer 151 is a top P-DBR layer, the top mirror portion 15 may further be provided with a top tunnel junction. The top tunnel junction of the top mirror portion 15 may be provided below the top P-DBR layer.

[0057] The active region 13 is sandwiched between the bottom mirror portion 12 and the top mirror portion 15 to form a resonant cavity, wherein photons are reflected back and forth in the resonant cavity after being excited and are repeatedly amplified to form laser oscillation, thereby forming a laser. A person skilled in the art should know that by configuring and designing the bottom mirror portion 12 and the top mirror portion 15, the emission direction of the laser can be selectively controlled, for example, emitting from the bottom mirror portion 12, or emitting from the top mirror portion 15. Accordingly, the bottom mirror portion 12 and the top mirror portion 15 are configured so that after the VCSEL light-emitting point 1 is turned on, the laser generated by the active region 13 is reflected multiple times in the resonant cavity formed between the bottom mirror portion 12 and the top mirror portion 15 and then emitted from the top mirror portion 15, or the bottom mirror portion 12.

[0058] In the embodiment of the present application, the active region 13 includes at least one PN junction. Specifically, the PN junction includes at least one P-type semiconductor layer, at least one quantum well, and at least one N-type semiconductor layer. The P-type semiconductor layer, the quantum well, and the N-type semiconductor layer are stacked to form the PN junction.

[0059] The bottom restriction layer 122 has a central area located at the center thereof and a peripheral area surrounding the central area, wherein the central area of ​​the bottom restriction layer 122 forms a bottom restriction hole 101, and the peripheral area thereof forms a bottom restriction area. The main restriction layer 14 has a central area located at the center thereof and a peripheral area surrounding the central area, wherein the central area of ​​the main restriction layer 14 forms a main restriction hole 102, and the peripheral area thereof forms a main restriction area.

[0060] After the VCSEL light-emitting point 1 is turned on, the current is restricted by the main restriction layer 14 and the bottom restriction layer 122, and is finally introduced into the middle region of the VCSEL light-emitting point 1, so that the middle region of the active area 13 generates laser. Specifically, the restriction region has a higher resistivity to restrict the flow of carriers into the middle region of the VCSEL light-emitting point 1, and the refractive index of the restriction region is lower to laterally restrict photons. The carrier and optical lateral restriction increases the density of carriers and photons in the active area 13, and improves the efficiency of generating light in the active area 13.

[0061] In the embodiment of the present application, the main confinement layer 14 and the bottom confinement layer 122 may be implemented as an oxidized confinement layer, which is formed by an oxidation process. The main confinement layer 14 and the bottom confinement layer 122 may also be implemented as other types of confinement layers, for example, as an ion confinement layer, which is formed by an ion implantation process. The main confinement layer 14 is formed above and / or below the active region 13.

[0062] In the embodiment of the present application, the VCSEL anode 20 includes a first N-type metal layer 21, wherein the first N-type metal layer 21 is formed on the N-type substrate layer 11. In one embodiment of the present application, the substrate layer 11 is an N-type substrate layer 11, and the first N-type metal layer 21 is formed below the substrate layer 11.

[0063] like Figure 4 As shown, in another embodiment of the present application, the first N-type metal layer 21 is located above the substrate layer 11, and the VCSEL anode 20 further includes an N-type metal extension layer 22, the N-type metal extension layer 22 extends from the first N-type metal layer 21 to below the substrate layer 11, and the N-type metal extension layer 22 is made of a metal material. The material of the N-type metal extension layer can be consistent with the material of the first N-type metal layer 21. In this embodiment, the substrate layer 11 can be an N-type substrate. The substrate layer 11 can also be a substrate with poor conductivity and almost insulation.

[0064] The VCSEL cathode 30 includes an electrode metal layer 31, wherein the electrode metal layer 31 is formed on the electrode contact layer 16. In one embodiment of the present application, the top DBR layer 151 is a top N-DBR layer; the electrode contact layer 16 of the VCSEL cathode 30 is an N-type electrode contact layer 16, and the electrode metal layer 31 is a second N-type metal layer.

[0065] In another embodiment of the present application, the top DBR layer 151 is a top N-DBR layer; the top mirror portion 15 also includes a top tunnel junction, the electrode contact layer 16 of the VCSEL cathode 30 is a P-type electrode contact layer 16, the electrode metal layer 31 is a P-type metal layer, and the top tunnel junction of the top mirror portion 15 is located above the top N-DBR layer and is formed between the top N-DBR layer and the P-type electrode contact layer 16.

[0066] In another embodiment of the present application, the top DBR layer 151 is a top P-DBR layer; the top mirror portion 15 further includes a top tunnel junction. The top tunnel junction of the top mirror portion 15 may be disposed below the top P-DBR layer. The electrode contact layer 16 of the VCSEL cathode 30 is a P-type electrode contact layer 16, and the electrode metal layer 31 is a P-type metal layer. The P-type electrode contact layer 16 is formed above the top P-DBR layer.

[0067] Schematic VCSEL array: Accordingly, according to another aspect of the present application, a VCSEL array 100 is also provided. Figure 5 and Figure 6 As shown, the VCSEL array 100 includes: two or more VCSEL light-emitting points 1 as described above, wherein the VCSEL anodes 20 of the two or more VCSEL light-emitting points 1 are shared. The VCSEL cathodes 30 of the two or more VCSEL light-emitting points 1 are electrically isolated. The specific manner in which the VCSEL cathodes 30 of the two or more VCSEL light-emitting points 1 are electrically isolated is not limited by the present application. For example, an isolation groove may be provided between two adjacent VCSEL light-emitting points 1, wherein the isolation groove extends downward from the upper surface of the VCSEL light-emitting point 1 to the bottom N-DBR layer 121; or ions may be injected between two adjacent VCSEL light-emitting points 1 to form an ion isolation portion, wherein the ion isolation portion extends downward from the upper surface of the VCSEL light-emitting point 1 to the bottom N-DBR layer 121. The specific structure and function of the VCSEL light-emitting point 1 have been described in the above reference. Figures 2 to 4 The illustrated VCSEL light emitting point 1 is described in detail in the description thereof, and therefore, a repeated description thereof will be omitted.

[0068] Schematic optical device: Accordingly, according to another aspect of the present application, an optical device 200 is also provided. Figure 7As shown, the optical device 200 includes at least one VCSEL array 100 as described above. When the optical device 200 includes a plurality of VCSEL arrays 100, the plurality of VCSEL arrays 100 can be arranged according to requirements.

[0069] The specific structure and function of the VCSEL light emitting point 1 in the VCSEL array 100 have been described above with reference to Figures 2 to 4 The illustrated VCSEL light emitting point 1 is described in detail in the description thereof, and therefore, a repeated description thereof will be omitted.

[0070] Schematic method for manufacturing a VCSEL device: Accordingly, in an embodiment of the present application, a method for manufacturing a VCSEL device is proposed. Figures 8 to 10 As shown, it includes: S110, forming a light-emitting point body 10, the light-emitting point body 10 includes: a substrate layer 11, a bottom mirror part 12, an active area 13, a main limiting layer 14, a top mirror part 15 and an electrode contact layer 16; wherein the bottom mirror part 12 is formed on the substrate layer 11, and the bottom mirror part 12 includes a bottom N-DBR layer 121, a bottom limiting layer 122 and a bottom tunnel junction 123; the bottom N-DBR layer 121 is formed on the N-type substrate layer 11, and the bottom limiting layer 122 and the bottom tunnel junction 123 are stacked on the bottom N-DBR layer 121; the top mirror part 15 includes at least one A top DBR layer 151; the active region 13 is located between the bottom mirror portion 12 and the top mirror portion 15; the main limiting layer 14 is located between the bottom mirror portion 12 and the top mirror portion 15; the electrode contact layer 16 is formed on the top mirror portion 15; S120, a VCSEL cathode 30 is formed, the VCSEL cathode 30 includes an electrode metal layer 31, the electrode metal layer 31 is formed on the electrode contact layer 16; and, S130, a VCSEL anode 20 is formed, the VCSEL anode 20 includes a first N-type metal layer 21, the first N-type metal layer 21 is formed on the substrate layer 11.

[0071] In step S110, a light-emitting point body 10 is formed. Specifically, the specific implementation method of forming the light-emitting point body 10 is not limited by the present application. In a specific example of the present application, first, a substrate layer 11 is provided; then, a bottom N-type semiconductor alternating layer, a bottom confinement layer forming layer, a bottom tunnel junction forming layer, an active area forming layer, a main confinement layer forming layer, a top doped semiconductor alternating layer and a top contact layer forming layer stacked on the substrate layer 11 are grown on the substrate layer 11 through an epitaxial growth process to form an epitaxial main body structure; the epitaxial main body structure includes a bottom N-type semiconductor alternating layer, a bottom confinement layer forming layer, a bottom tunnel junction forming layer, an active area forming layer, a main confinement layer forming layer, a top doped semiconductor alternating layer and a top contact layer forming layer stacked on the substrate layer 11. The top doped semiconductor alternating layer is implemented as an N-type semiconductor alternating layer. Next, a VCSEL light-emitting point formation region is defined, and the portion other than the VCSEL light-emitting point 1 of the epitaxial body is removed by an etching process, so that the epitaxial body structure is divided into a plurality of unit structures for forming the VCSEL light-emitting point 1. Specifically, each layer structure of the epitaxial body structure (i.e., the bottom N-type semiconductor alternating layer, the bottom confinement layer forming layer, the bottom tunnel junction forming layer, the active region forming layer, the main confinement layer forming layer, the top doped semiconductor alternating layer, and the top contact layer forming layer) is respectively divided into a plurality of sub-unit regions. Each unit structure includes: a bottom N-type semiconductor alternating layer sub-unit region, a bottom confinement layer forming layer sub-unit region, a bottom tunnel junction forming layer sub-unit region, an active region forming layer sub-unit region, a main confinement layer forming layer sub-unit region, a top doped semiconductor alternating layer sub-unit region, and a top contact layer forming layer sub-unit region. The unit structure is oxidized so that the portion of the bottom restriction layer forming layer sub-unit region in the unit structure close to the outer edge of the unit structure and the portion of the main restriction layer forming layer sub-unit region close to the outer edge of the unit structure are oxidized, thereby forming a restriction area; the portion of the bottom restriction layer forming layer sub-unit region close to the center of the unit structure and the portion of the main restriction layer forming layer close to the center of the unit structure are not oxidized, forming a restriction hole in the restriction area. The restriction layer can also be formed by other methods, for example, by an ion implantation process.In this way, each oxidized unit structure and the substrate layer 11 form the light-emitting point body 10, wherein the bottom N-type semiconductor alternating layer subunit area forms the bottom N-DBR layer 121, the bottom confinement layer forming layer subunit area forms the bottom confinement layer 122 having the bottom confinement hole 101, the bottom tunnel junction forming layer subunit area forms the bottom tunnel junction 123, the active area forming layer subunit area forms the active area 13, the main confinement layer forming layer subunit area forms the main confinement layer 14 having the main confinement hole 102, the top doped semiconductor alternating layer subunit area forms the top DBR layer 151, and the top contact layer forming layer subunit area forms the electrode contact layer 16. In the embodiment of the present application, the substrate layer 11 can be thinned.

[0072] In step S120, a VCSEL cathode 30 is formed. Specifically, a metal is plated on the electrode contact layer 16 to form an electrode metal layer 31. The electrode metal layer 31 may be an N-type metal layer.

[0073] In step S130, a VCSEL anode 20 is formed. Specifically, an N-type metal is plated on the lower surface of the substrate layer 11 to form a first N-type metal layer 21. Alternatively, first, in the process of forming the light-emitting point body 10, after a substrate layer 11, a first N-type metal layer 21 is first formed on the substrate layer 11, and then the epitaxial main structure is formed on the first N-type metal layer 21. Then, a hole is dug on the substrate layer 11, the hole passes through the upper surface and the lower surface of the substrate layer 11, and the hole extends to the first N-type metal layer 21; then, the N-type metal is injected into the hole of the substrate layer 11, and the N-type metal injected into the hole of the substrate layer 11 extends to the first N-type metal layer 21. When the N-type metal is injected into the hole of the substrate layer 11, the N-type metal can be injected to overflow the hole of the substrate layer 11, so that at least part of the N-type metal extends to the bottom of the substrate layer 11, thereby forming an N-type metal extension layer 22, wherein the N-type metal extension layer 22 extends from the first N-type metal layer 21 to the bottom of the substrate layer 11.

[0074] In summary, the VCSEL light emitting point 1 and VCSEL array 100 as well as the manufacturing method of the optical device 200 and the VCSEL device according to the embodiment of the present application are explained. The structure of the VCSEL light emitting point 1 is suitable for the common anode VCSEL array 100, and the substrate layer 11 is kept as an N-type substrate layer 11.

[0075] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

Claims

1. A VCSEL light emitting point, characterized in that: include: A light-emitting point body, the light-emitting point body comprising: substrate layer; A bottom mirror portion, the bottom mirror portion is formed on the substrate layer, the bottom mirror portion comprises a bottom N-DBR layer, a bottom confinement layer and a bottom tunnel junction; wherein the bottom N-DBR layer is formed on the substrate layer, the bottom confinement layer and the bottom tunnel junction are stacked on the bottom N-DBR layer; a top mirror portion, the top mirror portion comprising at least one top DBR layer; an active region located between the bottom mirror portion and the top mirror portion; a main confining layer located between the bottom mirror portion and the top mirror portion; and an electrode contact layer formed on the top mirror portion; A VCSEL anode, the VCSEL anode comprising a first N-type metal layer, wherein the first N-type metal layer is formed on the substrate layer; A VCSEL cathode comprises an electrode metal layer formed on the electrode contact layer.

2. The VCSEL light emitting point according to claim 1, wherein: The active region includes at least one PN junction.

3. The VCSEL light emitting point according to claim 1, wherein: The bottom confinement layer and the bottom tunnel junction are located above the bottom N-DBR layer, and the bottom confinement layer is located between the bottom tunnel junction and the bottom N-DBR layer.

4. The VCSEL light emitting point according to claim 1, wherein: The main confinement layer is located above and / or below the active region.

5. The VCSEL light emitting point according to claim 1, wherein: The top DBR layer is a top N-DBR layer.

6. The VCSEL light emitting point according to claim 1, wherein: The electrode contact layer of the VCSEL cathode is an N-type electrode contact layer, and the electrode metal layer is a second N-type metal layer.

7. The VCSEL light emitting point according to claim 1, wherein: The substrate layer is an N-type substrate layer, and the first N-type metal layer is formed below the substrate layer.

8. The VCSEL light emitting point according to claim 1, wherein: The first N-type metal layer is located above the substrate layer. The VCSEL anode further includes an N-type metal extension layer. The N-type metal extension layer extends from the first N-type metal layer to below the substrate layer. The N-type metal extension layer is made of metal material.

9. A VCSEL array, characterized in that: include: Two or more VCSEL light-emitting points, wherein the VCSEL light-emitting points include: A light-emitting point body, the light-emitting point body comprising: substrate layer; A bottom mirror portion, the bottom mirror portion is formed on the substrate layer, the bottom mirror portion comprises a bottom N-DBR layer, a bottom confinement layer and a bottom tunnel junction; wherein the bottom N-DBR layer is formed on the substrate layer, the bottom confinement layer and the bottom tunnel junction are stacked on the bottom N-DBR layer; a top mirror portion, the top mirror portion comprising at least one top DBR layer; an active region located between the bottom mirror portion and the top mirror portion; a main confining layer located between the bottom mirror portion and the top mirror portion; and an electrode contact layer formed on the top mirror portion; A VCSEL anode, the VCSEL anode comprising a first N-type metal layer, wherein the first N-type metal layer is formed on the substrate layer; A VCSEL cathode, wherein the VCSEL cathode comprises an electrode metal layer, and the electrode metal layer is formed on the electrode contact layer; Wherein, the VCSEL anode of two or more VCSEL light-emitting points is shared.

10. The VCSEL array according to claim 9, wherein: The bottom confinement layer and the bottom tunnel junction are located above the bottom N-DBR layer, and the bottom confinement layer is located between the bottom tunnel junction and the bottom N-DBR layer.

11. The VCSEL array according to claim 9, wherein: The main confinement layer is located above and / or below the active region.

12. The VCSEL array according to claim 9, wherein: The top DBR layer is a top N-DBR layer.

13. The VCSEL array according to claim 9, wherein: The electrode contact layer of the VCSEL cathode is an N-type electrode contact layer, and the electrode metal layer is a second N-type metal layer.

14. The VCSEL array according to claim 9, wherein: The substrate layer is an N-type substrate layer, and the first N-type metal layer is formed below the substrate layer.

15. The VCSEL array according to claim 9, wherein: The first N-type metal layer is located above the substrate layer. The VCSEL anode further includes an N-type metal extension layer. The N-type metal extension layer extends from the first N-type metal layer to below the substrate layer. The N-type metal extension layer is made of metal material.

16. The VCSEL array according to claim 9, wherein: The active region includes at least one PN junction.

17. An optical device, characterized in that: include: At least one VCSEL array, the VCSEL array comprising: two or more VCSEL light-emitting points, the VCSEL light-emitting points comprising: A light-emitting point body, the light-emitting point body comprising: substrate layer; A bottom mirror portion, the bottom mirror portion is formed on the substrate layer, the bottom mirror portion comprises a bottom N-DBR layer, a bottom confinement layer and a bottom tunnel junction; wherein the bottom N-DBR layer is formed on the substrate layer, the bottom confinement layer and the bottom tunnel junction are stacked on the bottom N-DBR layer; a top mirror portion, the top mirror portion comprising at least one top DBR layer; an active region located between the bottom mirror portion and the top mirror portion; a main confining layer located between the bottom mirror portion and the top mirror portion; and an electrode contact layer formed on the top mirror portion; A VCSEL anode, the VCSEL anode comprising a first N-type metal layer, wherein the first N-type metal layer is formed on the substrate layer; A VCSEL cathode, wherein the VCSEL cathode comprises an electrode metal layer, and the electrode metal layer is formed on the electrode contact layer; Wherein, the VCSEL anode of two or more VCSEL light-emitting points is shared.

18. A method for manufacturing a VCSEL device, characterized in that: include: A light-emitting point body is formed, the light-emitting point body comprising: a substrate layer, a bottom mirror portion, an active region, a main limiting layer, a top mirror portion and an electrode contact layer; wherein the bottom mirror portion is formed on the substrate layer, the bottom mirror portion comprises a bottom N-DBR layer, a bottom limiting layer and a bottom tunnel junction; the bottom N-DBR layer is formed on the substrate layer, the bottom limiting layer and the bottom tunnel junction are stacked on the bottom N-DBR layer; the top mirror portion comprises at least one top DBR layer; the active region is located between the bottom mirror portion and the top mirror portion; the main limiting layer is located between the bottom mirror portion and the top mirror portion; the electrode contact layer is formed on the top mirror portion; forming a VCSEL cathode, the VCSEL cathode comprising an electrode metal layer, the electrode metal layer being formed on the electrode contact layer; and A VCSEL anode is formed, wherein the VCSEL anode includes a first N-type metal layer formed on the substrate layer.

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