Control method, equipment, medium and device for improving overcurrent tolerance of power semiconductor device in circuit
By judging abnormal current in the circuit and adjusting the voltage distribution between transistors, the vicious cycle of temperature and power consumption caused by overcurrent in the circuit of power semiconductor devices is solved, and the device tolerance and stability are improved.
Patent Information
- Application Number
- CN202411877965.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-19
- Publication Date
- 2025-03-28
AI Technical Summary
Power semiconductor devices are prone to overcurrent in circuits, resulting in a vicious cycle of temperature and power consumption, affecting the device's tolerance and stability.
By determining whether there is an abnormal current in the circuit, the voltage between the first transistor and the second transistor is obtained, and the first voltage is adjusted according to the parameters to reduce or increase the voltage distribution to meet the equalization conditions, thereby preventing the increase in temperature and power consumption caused by overcurrent.
It effectively prevents the vicious cycle of temperature increase - voltage increase - power consumption increase - temperature increase, and improves the ability of power semiconductor devices to withstand overcurrent in the circuit.
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Figure CN119727347A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of power semiconductor devices, and in particular to a control method, equipment, medium and device for improving overcurrent tolerance of power semiconductor devices in circuits. Background Art
[0002] Power semiconductor devices are widely used in power supply, motor drive, new energy, energy storage and other fields. Commonly used power devices include silicon IGBT, silicon Mosfet, Sic Mosfet, etc. Cascade use is a common application method. Summary of the invention
[0003] Embodiments of the present invention provide a control method, device, medium and apparatus for improving the overcurrent tolerance of a power semiconductor device in a circuit, so as to prevent a vicious cycle of temperature increase - voltage increase - power consumption increase - temperature increase from occurring on a first transistor, or on other transistors cascaded with the first transistor.
[0004] In a first aspect, an embodiment of the present invention provides a control method for improving overcurrent tolerance of a power semiconductor device in a circuit, wherein the circuit includes a cascaded first transistor and an element, and the control method includes:
[0005] determining whether there is an abnormal current in the circuit;
[0006] When an abnormal current exists in the circuit, obtaining a first voltage between a first electrode and a second electrode of the first transistor;
[0007] The first voltage is adjusted according to a parameter; wherein the parameter includes the first voltage.
[0008] Optionally, the element comprises a second transistor;
[0009] After determining whether there is an abnormal current in the circuit, the control method further includes:
[0010] When an abnormal current exists in the circuit, obtaining a second voltage between the first electrode and the second electrode of the second transistor;
[0011] The parameters also include the second voltage.
[0012] Optionally, adjusting the first voltage according to a parameter includes:
[0013] Determining a magnitude relationship between the first voltage and the second voltage;
[0014] When the first voltage is greater than the second voltage, a first gate voltage of the control electrode of the first transistor is increased, and / or a second gate voltage of the control electrode of the second transistor is decreased, so as to reduce the first voltage.
[0015] Optionally, after adjusting the first voltage according to the parameter, the method further includes:
[0016] Determining whether the first voltage and the second voltage meet a balance condition;
[0017] When the first voltage and the second voltage do not meet the equilibrium condition, the steps of obtaining the first voltage, obtaining the second voltage, and adjusting the first voltage according to a parameter are repeated until the first voltage and the second voltage meet the equilibrium condition.
[0018] Optionally, the equilibrium condition includes:
[0019] A difference between the first voltage and the second voltage is smaller than a preset value.
[0020] Optionally, before determining whether the circuit has an abnormal current, the method further includes:
[0021] obtaining a first current of the first transistor;
[0022] Determining whether there is an abnormal current in the circuit includes:
[0023] It is determined whether abnormal current exists in the circuit according to the first current.
[0024] Optionally, the parameters further include a first junction temperature of the first transistor and / or a second junction temperature of the second transistor.
[0025] Optionally, before adjusting the first voltage according to a parameter, the control method further includes:
[0026] acquiring the first junction temperature according to the first voltage, the first current, and a first gate voltage of a control electrode of the first transistor;
[0027] The second junction temperature is acquired according to the second voltage, the first current, and a second gate voltage of a control electrode of the second transistor.
[0028] Optionally, the element includes at least one of an inductor, a capacitor and a resistor;
[0029] According to the parameter, adjusting the first voltage includes:
[0030] Increase a first gate voltage of a control electrode of the first transistor, and / or reduce a conduction time of the first transistor.
[0031] In a second aspect, an embodiment of the present invention provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the control method described in the first aspect when executing the program.
[0032] In a third aspect, an embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the control method as described in any one of claims 1 to 9.
[0033] In a fourth aspect, an embodiment of the present invention provides a control device for improving the overcurrent tolerance of a power semiconductor device in a circuit, comprising a control circuit for implementing the control method described in the first aspect.
[0034] The embodiment of the present invention provides a control method for improving the overcurrent tolerance of a power semiconductor device in a circuit, and determines whether there is an abnormal current in the circuit. When there is an abnormal current in the circuit, a first voltage between the first pole and the second pole of the first transistor is obtained. According to the parameter, the first voltage is adjusted. The voltage at both ends of the first transistor is thereby adjusted so that the voltage at both ends of the first transistor is reduced, thereby preventing a vicious cycle of temperature increase-voltage increase-power consumption increase-temperature increase from occurring on the first transistor; or, the voltage at both ends of the first transistor is adjusted so that the voltage at both ends of the first transistor is increased, thereby reducing the voltage at both ends of other transistors cascaded with the first transistor, thereby preventing a vicious cycle of temperature increase-voltage increase-power consumption increase-temperature increase from occurring on other transistors cascaded with the first transistor. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 is a schematic diagram of a cascade connection of a first transistor and a second transistor;
[0036] Figure 2 is a schematic diagram of another cascade connection of a first transistor and a second transistor;
[0037] Figure 3 A schematic diagram of a topological structure of a transistor cascade;
[0038] Figure 4 is a schematic diagram of a first transistor and an inductor cascade connection;
[0039] Figure 5 It is a schematic diagram of an output characteristic curve of a transistor when the junction temperature is 25 degrees Celsius;
[0040] Figure 6 It is a schematic diagram of an output characteristic curve of a transistor when the junction temperature is 175 degrees Celsius;
[0041] Figure 7A flow chart of a control method for improving overcurrent tolerance of a power semiconductor device in a circuit;
[0042] Figure 8 A flow chart of another control method for improving overcurrent tolerance of power semiconductor devices in a circuit;
[0043] Fig. 9 A flow chart of another control method for improving overcurrent tolerance of power semiconductor devices in a circuit;
[0044] Fig.10 A flow chart of another control method for improving overcurrent tolerance of power semiconductor devices in a circuit;
[0045] Fig.11 A schematic diagram of the structure of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0046] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.
[0047] Figure 1 is a schematic diagram of a cascade connection of a first transistor and a second transistor, referring to Figure 1 , the second electrode of the first transistor T1 is electrically connected to the first electrode of the second transistor T2, and the first transistor T1 and the second transistor T2 are connected in series. Figure 1 As shown, the first transistor T1 and the second transistor T2 are triodes (ie, IGBTs). Figure 2 is another schematic diagram of a first transistor and a second transistor cascaded, refer to Figure 2 , the first transistor T1 and the second transistor T2 can also be field effect transistors (i.e., Mosfet). In another embodiment, one of the first transistor T1 and the second transistor T2 can be a triode, and the other can be a field effect transistor. It can be understood that, for a triode, the first electrode and the second electrode of the transistor (the first transistor T1 and the second transistor T2) are respectively the collector and the emitter, and the control electrode of the transistor is the base. For a field effect transistor, the first electrode and the second electrode of the transistor are respectively the source and the drain, and the control electrode of the transistor is the gate.
[0048] Figure 3 This is a schematic diagram of a transistor cascade topology, see Figure 3, the topological structure includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6. The second electrode of the first transistor T1 is electrically connected to the first electrode of the second transistor T2, the second electrode of the second transistor T2 is electrically connected to the first electrode of the fourth transistor T4 and the first electrode of the sixth transistor T6. The first electrode of the first transistor T1 is electrically connected to the second electrode of the third transistor T3 and the first electrode of the fifth transistor T5. Figure 3 The topology shown includes Figure 1 The first transistor T1 and the second transistor T2 are cascaded as shown. It should be noted that: Figure 3 Only one topological structure of transistor cascade is given as an example, and in other implementations, there may be other topological structures. The topological structure may be used in applications such as motor controller, energy storage converter, photovoltaic inverter, etc.
[0049] Figure 4 1 is a schematic diagram of a first transistor and an inductor cascaded, wherein a second electrode of the first transistor T1 is electrically connected to a first end of the inductor L. The first transistor T1 and the inductor L are connected in series.
[0050] Figure 5 This is a schematic diagram of the output characteristic curve of a transistor when the junction temperature is 25 degrees Celsius. Figure 6 This is a schematic diagram of the output characteristic curve of a transistor when the junction temperature is 175 degrees Celsius. Figure 5 and Figure 6 , the horizontal axis is the source-drain voltage V DS , the vertical axis is the source-drain current I DS . Research has found that power semiconductor devices (such as motor controllers, energy storage converters, and photovoltaic inverters) may sometimes experience abnormal operating conditions during use, such as bridge arm direct conduction, excessive inductive load on-time or duty cycle, very small resistive load, and large capacitive load. At this time, a large current often appears. When the current reaches the set value (the set value can be the overcurrent protection set point, such as Figure 5 When the gate-source voltage is set to 18V (the middle arrow area), the voltage across the transistor in the on state will rise rapidly. Figure 5 As shown in DS In a relatively large case, a small increase in current will result in a large increase in voltage. Since power is the product of voltage and current, the loss on the transistor is very high at this moment, and the temperature of the transistor will rise rapidly. The temperature rise will cause its current output capacity to further decrease (the temperature rise will cause the output characteristic curve to follow the curve shown in Figure 2). Figure 6 The flow moves downward in the direction indicated by the arrow in the middle), thus forming a vicious cycle.
[0051] Figure 7This is a flow chart of a control method for improving the overcurrent tolerance of power semiconductor devices in circuits. Figure 1-Figure 7 The circuit includes a cascaded first transistor T1 and an element. The element may include, for example, at least one of a transistor, an inductor, a resistor, and a capacitor. The control method includes:
[0052] S101. Determine whether there is abnormal current in the circuit.
[0053] For example, reference Figure 1 , the element includes a transistor, a first transistor T1 and a second transistor T2 are cascaded. The working process of the circuit includes a state where one of the first transistor T1 and the second transistor T2 is turned on. And a state where both the first transistor T1 and the second transistor T2 are turned on. The state where both the first transistor T1 and the second transistor T2 are turned on is called an overcurrent state. In the overcurrent state, the currents of the first transistor T1 and the second transistor T2 may have abnormal currents.
[0054] For example, reference Figure 4 For inductive loads (inductance L), if the on-time is too long, the on-duty cycle is too large, or the magnetic material is saturated, the current may continue to increase, approaching or reaching the set point range of the transistor's current capability.
[0055] It should be noted that when the components include resistors or capacitors, scenarios with very small resistor loads and larger capacitor loads are also prone to generate fast and large currents, approaching or reaching the set point range of the current capability.
[0056] S102: When an abnormal current exists, obtain a first voltage between a first electrode and a second electrode of the first transistor.
[0057] Exemplarily, when an abnormal current exists in the circuit, the source-drain voltage of the first transistor T1 is obtained. The situation of the abnormal current exists, for example, the circuit has an abnormal current in an overcurrent state. The overcurrent state at least includes a short circuit state.
[0058] S103. Adjust the first voltage according to parameters; wherein the parameters include the first voltage.
[0059] The embodiment of the present invention provides a control method for improving the overcurrent tolerance of a circuit, and determines whether there is an abnormal current in the circuit. When there is an abnormal current in the circuit, a first voltage between the first pole and the second pole of the first transistor is obtained. According to the parameter, the first voltage is adjusted. The voltage across the first transistor is thereby adjusted so that the voltage across the first transistor is reduced, thereby preventing a vicious cycle of temperature increase-voltage increase-power consumption increase-temperature increase from occurring on the first transistor; or, the voltage across the first transistor is adjusted so that the voltage across the first transistor is increased, thereby reducing the voltage across the other transistors cascaded with the first transistor, thereby preventing a vicious cycle of temperature increase-voltage increase-power consumption increase-temperature increase from occurring on the other transistors cascaded with the first transistor.
[0060] The element includes a second transistor T2. When the cascaded first transistor T1 and second transistor T2 are in an overcurrent state and there is an abnormal current in the circuit, the higher the temperature of the transistor, the lower the carrier activity of the semiconductor at high temperature. Therefore, the transistor with the higher initial temperature tends to bear most of the voltage of the bus, resulting in the transistor with the higher initial temperature bearing the main energy, thus forming a vicious cycle.
[0061] Figure 8 For another control method flow chart to improve the overcurrent tolerance of power semiconductor devices in circuits, refer to Figure 1-Figure 6 ,as well as Figure 8 , the control method comprises:
[0062] S201. Determine whether there is abnormal current in the circuit.
[0063] S202: When an abnormal current exists, obtain a first voltage between a first electrode and a second electrode of a first transistor.
[0064] S203: When an abnormal current exists, obtain a second voltage between the first electrode and the second electrode of the second transistor.
[0065] Exemplarily, when an abnormal current exists in the circuit in an overcurrent state, the source-drain voltage of the second transistor T2 is obtained.
[0066] Exemplarily, the parameters include a first voltage and a second voltage. The first voltage is adjusted at least according to the first voltage and the second voltage.
[0067] S204: Determine the magnitude relationship between the first voltage and the second voltage.
[0068] If the first voltage is greater than the second voltage, then in the cascade circuit of the first transistor T1 and the second transistor T2, the first transistor T1 bears a higher voltage and the second transistor T2 bears a lower voltage. Conversely, the first transistor T1 bears a lower voltage and the second transistor T2 bears a higher voltage.
[0069] S205 . When the first voltage is greater than the second voltage, increase a first gate voltage of the control electrode of the first transistor, and / or decrease a second gate voltage of the control electrode of the second transistor, so as to decrease the first voltage.
[0070] refer to Figure 5 or Figure 6 , increasing the gate voltage of the control electrode of the transistor, for example, increasing the gate-source voltage, the curve moves upward, which is equivalent to reducing the equivalent resistance of the transistor, thereby reducing the voltage across the transistor.
[0071] When the first voltage is greater than the second voltage, in the cascade circuit of the first transistor T1 and the second transistor T2, the first transistor T1 bears a higher voltage, and the second transistor T2 bears a lower voltage. Thus, the first gate voltage of the control electrode of the first transistor T1 can be increased, and the voltage divided on the first transistor T1 can be reduced. Alternatively, the second gate voltage of the control electrode of the second transistor T2 can be reduced, the voltage divided on the second transistor T2 can be increased, and then the voltage divided on the first transistor T1 can be reduced. Alternatively, the first gate voltage of the control electrode of the first transistor T1 and the second gate voltage of the control electrode of the second transistor T2 can be increased to reduce the first voltage.
[0072] It can be understood that when the first voltage is less than the second voltage, the first gate voltage of the control electrode of the first transistor can be reduced, and / or the gate voltage of the second control electrode of the second transistor can be increased to increase the first voltage.
[0073] S206: Determine whether the first voltage and the second voltage meet a balance condition.
[0074] When the first voltage and the second voltage do not meet the equilibrium condition, the steps of obtaining the first voltage, obtaining the second voltage, and adjusting the first voltage according to the parameter are repeated until the first voltage and the second voltage meet the equilibrium condition. That is, when the first voltage and the second voltage do not meet the equilibrium condition, the execution returns to step S202.
[0075] In one embodiment, the equilibrium condition includes: the difference between the first voltage and the second voltage is less than a preset value, so that the first voltage is close to or equal to the second voltage. As an example, the first voltage is equal to the second voltage. At this time, the overcurrent energy is equally distributed to the first transistor T1 and the second transistor T2 of the cascade in the cascade circuit.
[0076] In an embodiment of the present invention, based on the above embodiment, the magnitude relationship between the first voltage and the second voltage is determined. When the first voltage is greater than the second voltage, the first gate voltage of the control electrode of the first transistor is increased, and / or the second gate voltage of the control electrode of the second transistor is reduced to reduce the first voltage. The voltage distribution of the cascaded first transistor T1 and the second transistor T2 is adjusted by the gate level value (i.e., the gate voltage, the gate voltage includes the first gate voltage and the second gate voltage). In the cascade circuit, the overcurrent energy is balanced to the cascaded first transistor T1 and the second transistor T2. In other embodiments, S203 in the above steps can also be located before step S202.
[0077] Fig. 9 For another control method flow chart to improve circuit overcurrent tolerance, refer to Figure 1-Figure 6 ,as well as Fig. 9 , the control method comprises:
[0078] S301. Obtain a first current of a first transistor.
[0079] S302: Determine whether there is an abnormal current in the circuit according to the first current.
[0080] S303: When an abnormal current exists, obtain a first voltage between the first electrode and the second electrode of the first transistor.
[0081] S304: When an abnormal current exists, obtain a second voltage between the first electrode and the second electrode of the second transistor.
[0082] S305 , obtaining a first junction temperature according to the first voltage, the first current, and a first gate voltage of a control electrode of the first transistor.
[0083] S306, acquiring a second node temperature according to the second voltage, the first current, and the second gate voltage of the control electrode of the second transistor.
[0084] S307, adjusting the first voltage according to the parameters; wherein the parameters include the first voltage, the second voltage, and the first node temperature and / or the second node temperature.
[0085] In an embodiment of the present invention, based on the above embodiment, a first junction temperature is obtained according to a first voltage, a first current and a first gate voltage of a control electrode of a first transistor. A second junction temperature is obtained according to a second voltage, a first current and a second gate voltage of a control electrode of a second transistor. The first voltage is adjusted according to the first voltage, the second voltage, and the first junction temperature and / or the second junction temperature. According to the junction temperature of the transistor (including the first junction temperature and the second junction temperature) and in combination with the voltage and current states, the voltage distribution of the cascade device is adjusted to achieve the purpose of balancing the temperature and voltage distribution.
[0086] Fig.10 For another control method flow chart to improve circuit overcurrent tolerance, refer to Figure 1-Figure 6 ,as well as Fig.10 , the element includes at least one of an inductor, a capacitor and a resistor. The control method includes:
[0087] S401. Determine whether there is abnormal current in the circuit.
[0088] S402: When an abnormal current exists, obtain a first voltage between a first electrode and a second electrode of a first transistor.
[0089] S403: Increase a first gate voltage of a control electrode of the first transistor, and / or reduce a conduction time of the first transistor.
[0090] In an embodiment of the present invention, based on the above embodiment, when the element includes at least one of an inductor, a capacitor and a resistor, the first gate voltage of the control electrode of the first transistor is increased, and / or the conduction time of the first transistor is reduced, and the current is quickly limited to before returning to the set point.
[0091] Fig.11 A schematic diagram of a computer device provided in an embodiment of the present invention, referring to Fig.11 The computer device 60 includes a memory 602, a processor 601, and a computer program stored in the memory 602 and executable on the processor. When the processor 601 executes the program, the method in the above embodiment is implemented. Fig.11 A block diagram of an exemplary computer device suitable for implementing embodiments of the present invention is shown. Fig.11 The computer device 60 shown is only an example and should not limit the functions and scope of use of the embodiments of the present invention. Fig.11 As shown, the computer device 60 is in the form of a general-purpose computing device. The components of the computer device 60 may include, but are not limited to: one or more processors 601, a system memory 602, and a bus 603 connecting different system components (including the system memory 602 and the processor 601).
[0092] Bus 603 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor or a local bus using any of a variety of bus structures. For example, these architectures include but are not limited to Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus and Peripheral Component Interconnect (PCI) bus.
[0093] The computer device 60 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the computer device 60, including volatile and non-volatile media, removable and non-removable media.
[0094] System memory 602 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 604 and / or cache memory 605. Computer device 60 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 606 may be used to read and write non-removable, non-volatile magnetic media ( Fig.11 not shown, usually called a "hard drive"). Although Fig.11 Not shown in the figure, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk"), and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, a DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to the bus 603 via one or more data medium interfaces. The system memory 602 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of the embodiments of the present invention.
[0095] A program / utility 608 having a set (at least one) of program modules 607 may be stored, for example, in system memory 602, such program modules 607 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment. Program modules 607 generally perform the functions and / or methods of the embodiments described herein.
[0096] The computer device 60 may also communicate with one or more external devices 609 (e.g., keyboard, pointing device, display 610, etc.), one or more devices that enable a user to interact with the device, and / or any device that enables the computer device 60 to communicate with one or more other computing devices (e.g., network card, modem, etc.). Such communication may be performed through an input / output (I / O) interface 611. Furthermore, the computer device 60 may also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN) and / or public network, such as the Internet) through a network adapter 612. Fig.11As shown, the network adapter 612 communicates with other modules of the computer device 60 via the bus 603. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with the computer device 60, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.
[0097] The processor 601 executes various functional applications and data processing by running programs stored in the system memory 602 .
[0098] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the method described in the above embodiment can be implemented.
[0099] The computer storage medium of the embodiment of the present invention can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to: an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.
[0100] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.
[0101] The program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
[0102] Computer program code for performing the operations of the present invention may be written in one or more programming languages or a combination thereof, including object-oriented programming languages such as Java, Smalltalk, C++, and conventional procedural programming languages such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).
[0103] An embodiment of the present invention further provides a control device for improving the overcurrent tolerance of a power semiconductor device in a circuit. The control device may include a control circuit.
[0104] The control circuit may include at least one element among an inductor, a capacitor, a resistor and a transistor, and the drive circuit may also include other elements besides the inductor, the capacitor, the resistor and the transistor to implement the control method in the above embodiment.
[0105] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims
1. A control method for improving overcurrent tolerance of a power semiconductor device in a circuit, the circuit comprising a cascaded first transistor and an element, characterized in that: The control method comprises: determining whether there is an abnormal current in the circuit; When an abnormal current exists in the circuit, obtaining a first voltage between a first electrode and a second electrode of the first transistor; The first voltage is adjusted according to a parameter; wherein the parameter includes the first voltage.
2. The control method according to claim 1, characterized in that: The element includes a second transistor; After determining whether there is an abnormal current in the circuit, the control method further includes: When an abnormal current exists in the circuit, obtaining a second voltage between the first electrode and the second electrode of the second transistor; The parameters also include the second voltage.
3. The control method according to claim 2, characterized in that: According to the parameter, adjusting the first voltage includes: Determining a magnitude relationship between the first voltage and the second voltage; When the first voltage is greater than the second voltage, a first gate voltage of the control electrode of the first transistor is increased, and / or a second gate voltage of the control electrode of the second transistor is decreased, so as to reduce the first voltage.
4. The control method according to claim 2, characterized in that: After adjusting the first voltage according to the parameter, the method further includes: Determining whether the first voltage and the second voltage meet a balance condition; When the first voltage and the second voltage do not meet the equilibrium condition, the steps of obtaining the first voltage, obtaining the second voltage, and adjusting the first voltage according to a parameter are repeated until the first voltage and the second voltage meet the equilibrium condition.
5. The control method according to claim 4, characterized in that: The equilibrium conditions include: A difference between the first voltage and the second voltage is smaller than a preset value.
6. The control method according to claim 2, characterized in that: Before determining whether the circuit has abnormal current, the method further includes: obtaining a first current of the first transistor; Determining whether there is an abnormal current in the circuit includes: It is determined whether abnormal current exists in the circuit according to the first current.
7. The control method according to claim 6, characterized in that: The parameters further include a first junction temperature of the first transistor and / or a second junction temperature of the second transistor.
8. The control method according to claim 7, characterized in that: Before adjusting the first voltage according to the parameter, the control method further includes: acquiring the first junction temperature according to the first voltage, the first current, and a first gate voltage of a control electrode of the first transistor; The second junction temperature is acquired according to the second voltage, the first current, and a second gate voltage of a control electrode of the second transistor.
9. The control method according to claim 1, characterized in that: The element includes at least one of an inductor, a capacitor and a resistor; According to the parameter, adjusting the first voltage includes: Increase a first gate voltage of a control electrode of the first transistor, and / or reduce a conduction time of the first transistor.
10. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the control method as described in any one of claims 1 to 9 is implemented.
11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the control method as described in any one of claims 1 to 9 is implemented.
12. A control device for improving overcurrent tolerance of a power semiconductor device in a circuit, characterized in that: The method comprises a control circuit for implementing the control method according to any one of claims 1 to 9.