DCDC chip soft start time-delay circuit of electricity utilization acquisition terminal and electric energy meter

Abstract

The invention discloses a DCDC chip soft start time delay circuit of an electricity utilization acquisition terminal and an electric energy meter, a DCDC chip is located in a conversion module, and the conversion module further comprises an inductor L1 and a capacitor C1; the DCDC chip soft start time-delay circuit further comprises a time-delay module, and the time-delay module comprises a resistor R3, a resistor R4, a resistor R5, a capacitor C2 and a diode V1. The influence quantity of the feedback end VFB is increased through the capacitor C2, so that the chip judges that the output is close to a set value and reduces the output duty ratio under the condition that the output voltage does not reach the set value, thereby reducing the average output current, reducing the rising slope of the output voltage VOUT and prolonging the establishment time. By adjusting the values of R4, R5 and C2, the soft start time can be freely set, and the requirements of different practical application scenes are met. The design and model selection difficulty is reduced, and the device has the advantages of being simple in structure, low in cost and the like.

Description

Technical Field

[0001] The invention relates to a soft-start delay circuit, in particular to a soft-start delay circuit of an electricity collection terminal and an electric energy meter. Background Art

[0002] The current soft start of DCDC converters mainly relies on the integrated circuit inside the chip. The internal circuit is designed with a fixed soft start time to ensure that the output voltage can rise smoothly when the power supply starts, prevent voltage overshoot and current surge, and protect the load and the power supply itself. This type of soft start solution simplifies the power supply design to a certain extent, allowing engineers to implement basic soft start functions without additional configuration.

[0003] However, since the soft start time is a fixed time determined by the internal circuit of the chip, it cannot be adjusted according to different product application scenarios. In a complex power supply architecture, different power modules may require different power-on timings, and the fixed soft start time cannot meet such diverse needs. Although some DCDC chips in the prior art allow the soft start time to be set through external components, the cost of these chips is relatively high, and the variety of products available is limited, which restricts the selection. In addition, as the power supply system becomes more and more complex, the requirements for power-on timing are becoming more and more stringent, which leads to a sharp increase in the difficulty of chip parameter selection design. Designers find it difficult to obtain a solution that meets performance requirements and is cost-effective within a limited selection range. Summary of the invention

[0004] The present invention proposes a DCDC chip soft start delay circuit for an electricity collection terminal and an electric energy meter, the purpose of which is to solve the problems of high cost and great design difficulty in customizing the DCDC chip soft start delay time through an external circuit.

[0005] The technical solution of the present invention is as follows: A DCDC chip soft-start delay circuit for an electricity collection terminal and an electric energy meter, wherein the DCDC chip is located in a conversion module, and the conversion module further includes an inductor L1 and a capacitor C1; the DCDC chip is powered by a voltage input terminal VIN, a switch pin SW of the DCDC chip is connected to one end of the inductor L1, a voltage pin VBST of the DCDC chip is connected to one end of the inductor L1 through the capacitor C1, and the other end of the inductor L1 is connected to the voltage output terminal VOUT, and the DCDC chip soft-start delay circuit further includes a delay module, and the delay module includes a resistor R3, a resistor R4, a capacitor R5, a capacitor C2 and a diode V1; The voltage output terminal VOUT is connected to the ground terminal GND through a series resistor R3 and a resistor R4, and a connection point between the resistor R3 and the resistor R4 is connected to a feedback voltage pin VFB of the DCDC chip; one end of the capacitor C2 is connected to the voltage output terminal VOUT, and the other end is connected to the ground terminal GND through a resistor R5; the positive electrode of the diode V1 is connected to the other end of the capacitor C2, and the negative electrode is connected to the feedback voltage pin VFB of the DCDC chip.

[0006] As a further improvement of the soft start delay circuit of the DCDC chip of the power collection terminal and the electric energy meter, the voltage boost process of the voltage output terminal VOUT is divided into three stages: The first stage is entered when power is turned on. At this time, the voltage of the voltage output terminal VOUT is 0V, and the feedback voltage received by the feedback voltage pin VFB is 0V. The DCDC chip adjusts the duty cycle of the switch pin SW to quickly increase the voltage of the voltage output terminal VOUT. At the same time, the voltage output terminal VOUT starts to charge the capacitor C2 through the resistor R5. Since the voltage rise speed of the voltage output terminal VOUT is greater than the charging speed of the RC circuit composed of the capacitor C2 and the resistor R5, the voltage at the other end of the capacitor C2 will rise synchronously with the voltage output terminal VOUT. When the voltage at the other end of capacitor C2 rises to a value greater than the voltage at the connection point between resistors R3 and R4, diode V1 is turned on, the first stage ends and the second stage begins. In the second stage, the feedback voltage received by the feedback voltage pin VFB is the voltage at the other end of the capacitor C2, which is greater than the voltage of the voltage output terminal VOUT after being divided by the resistors R3 and R4. Therefore, the DCDC chip slows down the increase speed of the voltage at the voltage output terminal VOUT by changing the duty cycle of the switch pin SW. In the second stage, since the voltage increase speed of the voltage output terminal VOUT is still greater than the charging speed of the RC circuit composed of the capacitor C2 and the resistor R5, the voltage at the other end of the capacitor C2 continues to increase synchronously with the voltage at the voltage output terminal VOUT. However, since the voltage increase speed of the voltage output terminal VOUT slows down and the charging ratio of the capacitor C2 increases, the voltage at the other end of the capacitor C2 increases more slowly than that in the first stage and gradually slows down. At the same time, the voltage at the connection point between the resistor R3 and the resistor R4 will increase synchronously with the voltage at the voltage output terminal VOUT. When the voltage at the connection point between the resistor R3 and the resistor R4 is greater than the voltage at the other end of the capacitor C2, the diode V1 is cut off, the second stage ends and the third stage begins; In the third stage, the feedback voltage received by the feedback voltage pin VFB is the voltage of the voltage output terminal VOUT divided by the resistors R3 and R4. The DCDC chip adjusts the duty cycle of the switch pin SW to quickly increase the voltage of the voltage output terminal VOUT to the set value. At the same time, the capacitor C2 continues to charge, and as the charging current through the resistor R5 decreases, the voltage at the other end of the capacitor C2 gradually decreases until the charging is completed. The voltage at one end of the capacitor C2 is equal to the voltage at the voltage output terminal VOUT, and the voltage at the other end is 0.

[0007] As a further improvement of the DCDC chip soft start delay circuit of the power collection terminal and the electric energy meter: it also includes a reset module, and the reset module includes a voltage regulator diode V2, a PNP transistor V3 and a resistor R6; The cathode of the voltage zener diode V2 is connected to the voltage input terminal VIN, and the anode is connected to the ground terminal GND through the resistor R6; the anode of the voltage zener diode V2 is connected to the base of the PNP transistor V3; the emitter of the PNP transistor V3 is connected to the voltage output terminal VOUT, and the collector is connected to the other end of the capacitor C2.

[0008] As a further improvement of the DCDC chip soft start delay circuit of the power collection terminal and the power meter: the reset module also includes a diode V4, the anode of the diode V4 is connected to the base of the PNP transistor V3, and the cathode is connected to the anode of the voltage regulator diode V2.

[0009] As a further improvement of the DCDC chip soft-start delay circuit of the electricity collection terminal and the electric energy meter: when the voltage at the voltage input terminal VIN is normal, the PNP transistor V3 is cut off; when the voltage input terminal VIN is abnormally powered off and the voltage becomes 0V, the DCDC chip no longer outputs voltage, and the voltage at the voltage output terminal VOUT remains unchanged under the action of the capacitor in the subsequent device, so the PNP transistor V3 is turned on, short-circuiting the capacitor C2, so that the capacitor C2 is quickly discharged to the initial state, ensuring that when the voltage at the voltage input terminal VIN returns to normal, the voltage difference across the capacitor C2 is 0V.

[0010] Compared with the prior art, the present invention has the following positive effects: 1. The present invention increases the influence of the feedback terminal VFB through capacitor C2, so that the chip determines that the output is close to the set value and reduces the output duty cycle when the output voltage does not reach the set value, thereby reducing the average output current, reducing the rising slope of the output voltage VOUT, and extending the establishment time. At the same time, by adjusting the values ​​of R4, R5, and C2, the soft start time can be freely set to meet the needs of different practical application scenarios, and the power-on timing of different power domains can be optimized and controlled, which greatly reduces the difficulty of design selection. At the same time, this circuit also has the advantages of simple structure and low cost, and can achieve low-cost and rapid development.

[0011] 2. In the instantaneous large load application scenario, the output end is usually connected to a large number of capacitors. In the traditional DCDC circuit, at the moment of output opening, since the voltage across the connected capacitor cannot change suddenly and is equivalent to a short circuit, an instantaneous current exceeding the chip overcurrent protection threshold will be generated, thereby triggering the overcurrent protection, causing the chip to enter the hiccup protection, and even causing the chip to enter an infinite loop of "output opening - triggering the overcurrent protection to shut down - output opening again after the protection setting time - triggering the overcurrent protection again", making the chip unable to start. The present invention can reduce the rising slope of the output voltage VOUT and extend the establishment time. When the capacitance on the output side of the chip is constant, it can be seen from the formula I=C*(dV / dt) that the extension of the establishment time can effectively reduce the charging current of the load capacitance on the output side of the chip. Therefore, when the chip starts, the total current demand of the subsequent circuit is reduced, so that the chip output current will not exceed the overcurrent protection threshold, thereby effectively avoiding the problem of abnormal chip startup caused by excessive capacitance on the output side of the DCDC triggering the chip overcurrent protection.

[0012] 3. After the system starts normally, the diode V1 is in a reverse cut-off state, and the capacitor C2 is disconnected from the feedback circuit, thereby preventing the capacitor C2 from being introduced into the feedback loop and affecting the dynamic response of the system during normal operation.

[0013] 4. The present invention realizes the rapid discharge of capacitor C2 in the power-off state through the reset module, thereby ensuring that capacitor C2 is in an uncharged state when power is restored and can still effectively play a delay role. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a circuit diagram of the present invention. DETAILED DESCRIPTION

[0015] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments.

[0016] like Figure 1 , a DCDC chip soft start delay circuit for an electricity collection terminal and an electric energy meter, wherein the DCDC chip is located in a conversion module, and includes a switch pin SW, a voltage pin VBST, and a feedback voltage pin VFB. To reduce the circuit area, the DCDC chip is packaged in SOT23-6. The conversion module also includes an inductor L1 and a capacitor C1. The DCDC chip is powered by a voltage input terminal VIN, a switch pin SW of the DCDC chip is connected to one end of the inductor L1, a voltage pin VBST of the DCDC chip is connected to one end of the inductor L1 through a capacitor C1, and the other end of the inductor L1 is connected to a voltage output terminal VOUT.

[0017] The switch pin SW is the output terminal of the MOSFET tube inside the chip D1. The periodic switching of the MOSFET tube generates a periodic fluctuating voltage. The voltage pin VBST is used as the power input of the internal upper arm MOSFET tube drive circuit. Through capacitor C1, the voltage of capacitor C1 on the VBST side is periodically raised and exceeds the input voltage by utilizing the periodic change of the switch pin SW and the characteristic that the voltage across capacitor C1 cannot change suddenly, thereby generating a high voltage that can drive the upper arm. The feedback voltage pin VFB is used as the output voltage feedback. The input voltage is compared with the internal voltage reference value to adjust the on and off time of the MOSFET tube to adjust the output voltage.

[0018] The DCDC chip soft start delay circuit further includes a delay module, and the delay module includes a resistor R3, a resistor R4, a capacitor R5, a capacitor C2 and a diode V1.

[0019] The voltage output terminal VOUT is connected to the ground terminal GND through the series resistor R3 and the resistor R4, and the connection point between the resistor R3 and the resistor R4 is connected to the feedback voltage pin VFB of the DCDC chip. One end of the capacitor C2 is connected to the voltage output terminal VOUT, and the other end is connected to the ground terminal GND through the resistor R5. The positive electrode of the diode V1 is connected to the other end of the capacitor C2, and the negative electrode is connected to the feedback voltage pin VFB of the DCDC chip.

[0020] If the system operates in a high temperature environment, it is not recommended to use a Schottky type diode V1. At high temperatures, the reverse leakage current of the Schottky diode increases rapidly, and the impact of capacitor C2 on the feedback loop cannot be ignored.

[0021] The voltage boost process of the voltage output terminal VOUT is divided into three stages: The first stage is entered when power is turned on. At this time, the voltage of the voltage output terminal VOUT is 0V, and the feedback voltage received by the feedback voltage pin VFB is 0V. The DCDC chip adjusts the duty cycle of the switch pin SW to quickly increase the voltage of the voltage output terminal VOUT. At the same time, the voltage output terminal VOUT starts to charge the capacitor C2 through the resistor R5. Since the voltage rise speed of the voltage output terminal VOUT is greater than the charging speed of the RC circuit composed of the capacitor C2 and the resistor R5, the voltage at the other end of the capacitor C2 will increase synchronously with the voltage output terminal VOUT.

[0022] When the voltage at the other end of the capacitor C2 rises to a value greater than the voltage at the connection point between the resistors R3 and R4, the diode V1 is turned on, the first stage ends, and the second stage begins.

[0023] In the second stage, the feedback voltage received by the feedback voltage pin VFB is the voltage at the other end of the capacitor C2, which is greater than the voltage at the voltage output terminal VOUT divided by the resistors R3 and R4, so that the DCDC chip determines that the output voltage is close to the set value, so the DCDC chip slows down the increase speed of the voltage at the voltage output terminal VOUT by changing the duty cycle of the switch pin SW. In the second stage, since the voltage rise speed of the voltage output terminal VOUT is still greater than the charging speed of the RC circuit composed of the capacitor C2 and the resistor R5, the voltage at the other end of the capacitor C2 continues to rise synchronously with the voltage at the voltage output terminal VOUT, but since the voltage rise speed of the voltage output terminal VOUT slows down and the charging ratio of the capacitor C2 increases, the voltage at the other end of the capacitor C2 rises more slowly than in the first stage and gradually slows down; at the same time, the voltage at the connection point between the resistor R3 and the resistor R4 will rise synchronously with the voltage at the voltage output terminal VOUT.

[0024] When the voltage at the connection point between the resistor R3 and the resistor R4 is greater than the voltage at the other end of the capacitor C2, the diode V1 is turned off, the second stage ends, and the third stage begins.

[0025] In the third stage, the feedback voltage received by the feedback voltage pin VFB is the voltage of the voltage output terminal VOUT divided by the resistors R3 and R4. The DCDC chip adjusts the duty cycle of the switch pin SW to quickly increase the voltage of the voltage output terminal VOUT to the set value. At the same time, the capacitor C2 continues to charge, and as the charging current through the resistor R5 decreases, the voltage at the other end of the capacitor C2 gradually decreases until the charging is completed. The voltage at one end of the capacitor C2 is equal to the voltage at the voltage output terminal VOUT, and the voltage at the other end is 0.

[0026] Among the three stages, the first and third stages are very short, and the second stage occupies most of the time, so the voltage rise time can be effectively extended. During design, the soft start time can be freely set by adjusting the values ​​of R4, R5, and C2 according to the specific usage scenario.

[0027] Since the resistance of resistor R5 is relatively large, capacitor C2 discharges very slowly through R5, and it cannot be ensured that capacitor C2 has completed discharging when the voltage input terminal VIN returns to normal, and it cannot guarantee the normal operation of the delay function at the next power-on. Therefore, this circuit also adds a reset module, which includes a voltage stabilizing diode V2, a PNP transistor V3 and a resistor R6.

[0028] The cathode of the voltage zener diode V2 is connected to the voltage input terminal VIN, and the anode is connected to the ground terminal GND through the resistor R6. The anode of the voltage zener diode V2 is connected to the base of the PNP transistor V3. The emitter of the PNP transistor V3 is connected to the voltage output terminal VOUT, and the collector is connected to the other end of the capacitor C2.

[0029] When the voltage at the voltage input terminal VIN is normal, the voltage zener diode V2 is turned on and the PNP transistor V3 is turned off. When the voltage input terminal VIN is abnormally powered off and the voltage becomes 0V, the DCDC chip no longer outputs voltage, while the voltage at the voltage output terminal VOUT remains unchanged under the action of the capacitor in the subsequent device. At the same time, the voltage zener diode V2 is turned off, so the base of the PNP transistor V3 is pulled down to 0V and turned on, short-circuiting the capacitor C2, so that the capacitor C2 is quickly discharged to the initial state, ensuring that when the voltage at the voltage input terminal VIN returns to normal, the voltage difference across the capacitor C2 is 0V.

[0030] The voltage value of the voltage stabilizing diode V2 should not be too large, otherwise the soft start delay circuit will fail.

[0031] Furthermore, the reset module also includes a diode V4, the positive electrode of which is connected to the base of the PNP transistor V3, and the negative electrode is connected to the positive electrode of the voltage-stabilizing diode V2. The diode V4 can effectively prevent the transistor V3 from breaking down in reverse. It is not recommended to add V4 in applications without the risk of breakdown, because the presence of V4 will affect the rapid discharge of the capacitor C2. The diode V4 preferably uses a Schottky diode, which can effectively reduce the voltage at the node connecting the capacitor C2 and the resistor R5 during rapid discharge, and shorten the recovery time of the soft-start delay circuit.

[0032] It should be noted that it is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. The scope of the present invention is defined by the claims rather than the above description.

Claims

1. A DCDC chip soft-start delay circuit for an electricity collection terminal and an electric energy meter, wherein the DCDC chip is located in a conversion module, and the conversion module further comprises an inductor L1 and a capacitor C1; the DCDC chip is powered by a voltage input terminal VIN, a switch pin SW of the DCDC chip is connected to one end of the inductor L1, a voltage pin VBST of the DCDC chip is connected to one end of the inductor L1 through the capacitor C1, and the other end of the inductor L1 is connected to a voltage output terminal VOUT, characterized in that: The DCDC chip soft start delay circuit also includes a delay module, and the delay module includes a resistor R3, a resistor R4, a capacitor R5, a capacitor C2 and a diode V1; The voltage output terminal VOUT is connected to the ground terminal GND through a series resistor R3 and a resistor R4, and a connection point between the resistor R3 and the resistor R4 is connected to a feedback voltage pin VFB of the DCDC chip; one end of the capacitor C2 is connected to the voltage output terminal VOUT, and the other end is connected to the ground terminal GND through a resistor R5; the positive electrode of the diode V1 is connected to the other end of the capacitor C2, and the negative electrode is connected to the feedback voltage pin VFB of the DCDC chip.

2. The DCDC chip soft start delay circuit of the power collection terminal and the electric energy meter as claimed in claim 1, characterized in that: The voltage boost process of the voltage output terminal VOUT is divided into three stages: The first stage is entered when power is turned on. At this time, the voltage of the voltage output terminal VOUT is 0V, and the feedback voltage received by the feedback voltage pin VFB is 0V. The DCDC chip adjusts the duty cycle of the switch pin SW to quickly increase the voltage of the voltage output terminal VOUT. At the same time, the voltage output terminal VOUT starts to charge the capacitor C2 through the resistor R5. Since the voltage rise speed of the voltage output terminal VOUT is greater than the charging speed of the RC circuit composed of the capacitor C2 and the resistor R5, the voltage at the other end of the capacitor C2 will rise synchronously with the voltage output terminal VOUT. When the voltage at the other end of capacitor C2 rises to a value greater than the voltage at the connection point between resistors R3 and R4, diode V1 is turned on, the first stage ends and the second stage begins. In the second stage, the feedback voltage received by the feedback voltage pin VFB is the voltage at the other end of the capacitor C2, which is greater than the voltage of the voltage output terminal VOUT after being divided by the resistors R3 and R4. Therefore, the DCDC chip slows down the increase speed of the voltage at the voltage output terminal VOUT by changing the duty cycle of the switch pin SW. In the second stage, since the voltage increase speed of the voltage output terminal VOUT is still greater than the charging speed of the RC circuit composed of the capacitor C2 and the resistor R5, the voltage at the other end of the capacitor C2 continues to increase synchronously with the voltage at the voltage output terminal VOUT. However, since the voltage increase speed of the voltage output terminal VOUT slows down and the charging ratio of the capacitor C2 increases, the voltage at the other end of the capacitor C2 increases more slowly than that in the first stage and gradually slows down. At the same time, the voltage at the connection point between the resistor R3 and the resistor R4 will increase synchronously with the voltage at the voltage output terminal VOUT. When the voltage at the connection point between the resistor R3 and the resistor R4 is greater than the voltage at the other end of the capacitor C2, the diode V1 is cut off, the second stage ends and the third stage begins; In the third stage, the feedback voltage received by the feedback voltage pin VFB is the voltage of the voltage output terminal VOUT divided by the resistors R3 and R4. The DCDC chip adjusts the duty cycle of the switch pin SW to quickly increase the voltage of the voltage output terminal VOUT to the set value. At the same time, the capacitor C2 continues to charge, and as the charging current through the resistor R5 decreases, the voltage at the other end of the capacitor C2 gradually decreases until the charging is completed. The voltage at one end of the capacitor C2 is equal to the voltage at the voltage output terminal VOUT, and the voltage at the other end is 0.

3. The DCDC chip soft start delay circuit of the power collection terminal and the electric energy meter as claimed in claim 1 or 2, characterized in that: It also includes a reset module, which includes a voltage regulator diode V2, a PNP transistor V3 and a resistor R6; The cathode of the voltage zener diode V2 is connected to the voltage input terminal VIN, and the anode is connected to the ground terminal GND through the resistor R6; the anode of the voltage zener diode V2 is connected to the base of the PNP transistor V3; the emitter of the PNP transistor V3 is connected to the voltage output terminal VOUT, and the collector is connected to the other end of the capacitor C2.

4. The DCDC chip soft start delay circuit of the power collection terminal and the power meter as claimed in claim 3, characterized in that: The reset module also includes a diode V4, the anode of the diode V4 is connected to the base of the PNP transistor V3, and the cathode of the diode V4 is connected to the anode of the voltage regulator diode V2.

5. The DCDC chip soft start delay circuit of the power collection terminal and the power meter as claimed in claim 3 or 4, characterized in that: When the voltage at the voltage input terminal VIN is normal, the PNP transistor V3 is cut off; when the voltage input terminal VIN is abnormally powered off and the voltage becomes 0V, the DCDC chip no longer outputs voltage, and the voltage at the voltage output terminal VOUT remains unchanged under the action of the capacitor in the subsequent device, so the PNP transistor V3 is turned on, short-circuiting the capacitor C2, so that the capacitor C2 is quickly discharged to the initial state, ensuring that when the voltage at the voltage input terminal VIN returns to normal, the voltage difference across the capacitor C2 is 0V.

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