Dead zone circuit capable of adjusting dead zone time

Abstract

The invention relates to a dead zone circuit capable of adjusting dead zone time. The circuit is formed by connecting an enable signal end EN, a power end VDD, a dead time control port DTC, an external resistor RD, a resistor R3, a resistor R4, an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN3, an NMOS tube MN4, an NMOS tube MN5, a capacitor C1, a capacitor C2, a current mirror assembly, an IN signal end, an IN-signal end, a PMOS tube MP1, a PMOS tube MP2, a first phase inverter INV1, a second phase inverter INV2, a third phase inverter INV3, an adjustable dead time output signal end OUT1 and an adjustable dead time output signal end OUT2. According to the dead zone circuit capable of adjusting the dead zone time, the current value of the current mirror assembly can be changed by changing the resistance value of the external resistor RD, then the delay time of the circuit is changed, and the purpose of adjusting the dead zone time is achieved.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic circuits, and in particular relates to a dead zone circuit with adjustable dead zone time. Background Art

[0002] In the field of power drive circuits, such as motor drives, inverters and other application scenarios, dead zone circuits play a vital role. Traditional drive circuits use a fixed dead zone time design, and this fixed value is usually determined based on estimates of various working conditions and with a certain margin.

[0003] However, in actual operation, this fixed dead time setting method has significant disadvantages. For most working conditions, the dead time is set to a fixed value with a margin, which causes a large amount of dead time "overflow", resulting in a longer reverse conduction time for the power device. Due to the continuous action of the current and reverse voltage inside the power device, greater reverse conduction losses are caused, which not only reduces the working efficiency of the entire circuit, but also affects the service life of the power device and the reliability of the system due to excessive heat generation, increasing the difficulty and cost of heat dissipation design.

[0004] Therefore, the present invention provides a dead zone circuit with adjustable dead zone time to solve the above technical problem. Summary of the invention

[0005] In view of the above problems, the purpose of the present invention is to provide a dead zone circuit with adjustable dead zone time, which changes the current value of the current mirror component by changing the resistance value of the external resistor, thereby changing the delay time of the dead zone circuit, thereby achieving the purpose of adjustable dead zone time.

[0006] The present invention provides a dead zone circuit with adjustable dead zone time, comprising an enable signal terminal EN, a power supply terminal VDD, a dead zone time control port DTC, an external resistor R D, resistor R3, resistor R4, NMOS tube MN1, NMOS tube MN2, NMOS tube MN3, NMOS tube MN4, NMOS tube MN5, capacitor C1, capacitor C2, current mirror component, IN signal terminal, IN-signal terminal, PMOS tube MP1, PMOS tube MP2, first inverter INV1, second inverter INV2, third inverter INV3, adjustable dead time output signal terminal OUT1 and adjustable dead time output signal terminal OUT2; the enable signal terminal EN is connected to the gate of the NMOS tube MN2 and the input terminal of the first inverter INV1 at the same time. The drain of the NMOS tube MN2 is connected to the first end of the resistor R4, the source of the NMOS tube MN2 is simultaneously connected to the drain of the NMOS tube MN1, the first end of the capacitor C1 and the first input end of the current mirror component, the second end of the resistor R4 is connected to the first end of the resistor R3, the second end of the resistor R3 is connected to the first end of the dead time control port DTC, the second end of the dead time control port DTC is connected to the external resistor R D The first end of the external resistor R D The second end of the first inverter INV1 is connected to the power supply terminal VDD, the output end of the first inverter INV1 is simultaneously connected to the gate of the NMOS tube MN1 and the gate of the NMOS tube MN3, the source of the NMOS tube MN1 is simultaneously connected to the second end of the capacitor C1 and the second input end of the current mirror component, the first output end of the current mirror component is simultaneously connected to the source of the NMOS tube MN5, the source of the NMOS tube MN4 and the drain of the NMOS tube MN3, the second output end of the current mirror component is connected to the source of the NMOS tube MN3, the gate of the NMOS tube MN4 is simultaneously connected to the IN- signal terminal and the gate of the PMOS tube MP2, the drain of the NMOS tube MN4 is simultaneously connected to the PMOS The source of the S transistor MP2, the first end of the capacitor C2 and the input end of the second inverter INV2 are connected, the drain of the PMOS transistor MP2 is connected to the power supply terminal VDD, the output end of the second inverter INV2 is connected to the adjustable dead time output signal terminal OUT1, the gate of the NMOS transistor MN5 is connected to the IN signal terminal and the gate of the PMOS transistor MP1 at the same time, the drain of the NMOS transistor MN5 is connected to the source of the PMOS transistor MP1, the second end of the capacitor C2 and the input end of the third inverter INV3 at the same time, the output end of the third inverter INV3 is connected to the adjustable dead time output signal terminal OUT2, and the drain of the PMOS transistor MP1 is connected to the power supply terminal VDD.

[0007] Preferably, the current mirror component includes a first current mirror and a second current mirror, and the current I1 flowing through the first current mirror is equal to the current I2 flowing through the second current mirror; the first input end of the first current mirror is simultaneously connected to the drain of the NMOS tube MN1, the first end of the capacitor C1 and the source of the NMOS tube MN2, the second input end of the first current mirror is simultaneously connected to the source of the NMOS tube MN1 and the second end of the capacitor C1, the first output end of the first current mirror is connected to the first input end of the second current mirror, the second output end of the first current mirror is connected to the second input end of the second current mirror, the first output end of the second current mirror is simultaneously connected to the source of the NMOS tube MN5, the source of the NMOS tube MN4 and the drain of the NMOS tube MN3, and the second output end of the second current mirror is connected to the source of the NMOS tube MN3.

[0008] Preferably, the first current mirror includes an NMOS tube M1 and a resistor R1, and the second current mirror includes an NMOS tube M2 and a resistor R2, the source of the NMOS tube M1 is simultaneously connected to the drain of the NMOS tube MN1, the first end of the capacitor C1, the source of the NMOS tube MN2, the gate of the NMOS tube M1, and the gate of the NMOS tube M2, the drain of the NMOS tube M1 is connected to the first end of the resistor R1, the second end of the resistor R1 is simultaneously connected to the source of the NMOS tube MN1, the second end of the capacitor C1, the first end of the resistor R2, and the source of the NMOS tube MN3, the second end of the resistor R2 is connected to the source of the NMOS tube M2, and the drain of the NMOS tube M2 is simultaneously connected to the source of the NMOS tube MN5, the source of the NMOS tube MN4, and the drain of the NMOS tube MN3.

[0009] Preferably, the model of the NMOS tube M1 is the same as the model of the NMOS tube M2, the resistance of the resistor R1 is the same as the resistance of the resistor R2, and the temperature coefficients of the resistor R3 and the resistor R4 are complementary; the calculation formulas of the current I1 and the current I2 are as follows: Among them, the V M1 is the voltage value of the NMOS tube M1, and the R MN2 is the resistance value of the NMOS tube MN2.

[0010] Compared with the related art, the dead time circuit provided by the present invention is composed of an enable signal terminal EN, a power supply terminal VDD, a dead time control port DTC, an external resistor R D, resistor R3, resistor R4, NMOS tube MN1, NMOS tube MN2, NMOS tube MN3, NMOS tube MN4, NMOS tube MN5, capacitor C1, capacitor C2, current mirror component, IN signal terminal, IN- signal terminal, PMOS tube MP1, PMOS tube MP2, first inverter INV1, second inverter INV2, third inverter INV3, adjustable dead time output signal terminal OUT1 and adjustable dead time output signal terminal OUT2 are connected to form. In the above circuit, by changing the external resistor R D The resistance value of the current mirror component is changed to change the current value, thereby changing the delay time of the dead zone circuit, achieving the purpose of adjustable dead zone time; by connecting an external resistor R D Adjusting the dead time is flexible and convenient, and can reduce power consumption and improve performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of the circuit structure of a dead zone circuit with adjustable dead zone time according to the present invention;

[0012] Figure 2 A simulation curve diagram of a dead zone circuit with adjustable dead zone time according to the present invention;

[0013] Figure 3 The external resistor R D A simulation curve diagram of the dead zone circuit with adjustable dead time when the resistance value of is 0;

[0014] Figure 4 The external resistor R D When the resistance value of is 100, a simulation curve diagram of the dead zone circuit with adjustable dead time. DETAILED DESCRIPTION

[0015] The present invention provides a dead zone circuit with adjustable dead zone time, aiming to solve the problem that the dead zone time of the existing dead zone circuit is fixed, resulting in increased power consumption and reduced energy efficiency.

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] Please see attached Figure 1-4 As shown, the present invention provides a dead zone circuit with adjustable dead time, which includes an enable signal terminal EN, a power supply terminal VDD, a dead time control port DTC, an external resistor R D, resistor R3, resistor R4, NMOS tube MN1, NMOS tube MN2, NMOS tube MN3, NMOS tube MN4, NMOS tube MN5, capacitor C1, capacitor C2, current mirror component 1, IN signal terminal, IN- signal terminal, PMOS tube MP1, PMOS tube MP2, first inverter INV1, second inverter INV2, third inverter INV3, adjustable dead time output signal terminal OUT1 and adjustable dead time output signal terminal OUT2; the enable signal terminal EN is simultaneously connected to the NMOS tube MN The gate of the NMOS tube MN2 is connected to the input end of the first inverter INV1, the drain of the NMOS tube MN2 is connected to the first end of the resistor R4, the source of the NMOS tube MN2 is simultaneously connected to the drain of the NMOS tube MN1, the first end of the capacitor C1 and the first input end of the current mirror component 1, the second end of the resistor R4 is connected to the first end of the resistor R3, the second end of the resistor R3 is connected to the first end of the dead time control port DTC, and the second end of the dead time control port DTC is connected to the external resistor R D The first end of the external resistor R D The second end of the first inverter INV1 is connected to the power supply terminal VDD, the output end of the first inverter INV1 is simultaneously connected to the gate of the NMOS tube MN1 and the gate of the NMOS tube MN3, the source of the NMOS tube MN1 is simultaneously connected to the second end of the capacitor C1 and the second input end of the current mirror component, the first output end of the current mirror component is simultaneously connected to the source of the NMOS tube MN5, the source of the NMOS tube MN4 and the drain of the NMOS tube MN3, the second output end of the current mirror component is connected to the source of the NMOS tube MN3, the gate of the NMOS tube MN4 is simultaneously connected to the IN- signal terminal and the gate of the PMOS tube MP2, the drain of the NMOS tube MN4 is simultaneously connected to the PMOS The source of the S transistor MP2, the first end of the capacitor C2 and the input end of the second inverter INV2 are connected, the drain of the PMOS transistor MP2 is connected to the power supply terminal VDD, the output end of the second inverter INV2 is connected to the adjustable dead time output signal terminal OUT1, the gate of the NMOS transistor MN5 is connected to the IN signal terminal and the gate of the PMOS transistor MP1 at the same time, the drain of the NMOS transistor MN5 is connected to the source of the PMOS transistor MP1, the second end of the capacitor C2 and the input end of the third inverter INV3 at the same time, the output end of the third inverter INV3 is connected to the adjustable dead time output signal terminal OUT2, and the drain of the PMOS transistor MP1 is connected to the power supply terminal VDD.

[0018] Specifically, the current mirror component 1 includes a first current mirror 11 and a second current mirror 12, and the current I1 flowing through the first current mirror 11 is equal to the current I2 flowing through the second current mirror 12; the first input end of the first current mirror 11 is simultaneously connected to the drain of the NMOS tube MN1, the first end of the capacitor C1 and the source of the NMOS tube MN2, the second input end of the first current mirror 11 is simultaneously connected to the source of the NMOS tube MN1 and the second end of the capacitor C1, the first output end of the first current mirror 11 is connected to the first input end of the second current mirror 12, the second output end of the first current mirror 11 is connected to the second input end of the second current mirror 12, the first output end of the second current mirror 12 is simultaneously connected to the source of the NMOS tube MN5, the source of the NMOS tube MN4 and the drain of the NMOS tube MN3, and the second output end of the second current mirror 12 is connected to the source of the NMOS tube MN3.

[0019] In this embodiment, the first current mirror 11 includes an NMOS transistor M1 and a resistor R1, and the second current mirror 12 includes an NMOS transistor M2 and a resistor R2. The source of the NMOS transistor M1 is simultaneously connected to the drain of the NMOS transistor MN1, the first end of the capacitor C1, the source of the NMOS transistor MN2, the gate of the NMOS transistor M1, and the gate of the NMOS transistor M2. The drain of the NMOS transistor M1 is connected to the first end of the resistor R1. The second end of the resistor R1 is simultaneously connected to the source of the NMOS transistor MN1, the second end of the capacitor C1, the first end of the resistor R2, and the source of the NMOS transistor MN3. The second end of the resistor R2 is connected to the source of the NMOS transistor M2. The drain of the NMOS transistor M2 is simultaneously connected to the source of the NMOS transistor MN5, the source of the NMOS transistor MN4, and the drain of the NMOS transistor MN3.

[0020] It is worth mentioning that the model of the NMOS tube M1 is the same as the model of the NMOS tube M2, the resistance of the resistor R1 is the same as the resistance of the resistor R2, and the temperature coefficients of the resistor R3 and the resistor R4 are complementary; the calculation formulas of the current I1 and the current I2 are as follows: Among them, the V M1 is the voltage value of the NMOS tube M1, and the R MN2 is the resistance value of the NMOS tube MN2.

[0021] To further illustrate the present invention, a point Y is set at a position between the source of the PMOS tube MP1 and the drain of the NMOS tube MN5, and a point X is set at a position between the source of the PMOS tube MP2 and the drain of the NMOS tube MN4.

[0022] It should be noted that the voltage value of the power supply terminal VDD is 5V; the IN signal terminal and IN - The signal end is a signal end with opposite phases on both sides. There is a dead zone between their output signals, and the size of the rising edge dead zone time is basically the same as the size of the falling edge dead zone time. When the dead zone circuit is in an abnormal working state, the enable signal end EN is low level, and becomes high level after passing through the first inverter INV1, the NMOS tube MN2 is turned off, the NMOS tube MN1 and the NMOS tube MN3 are turned on, the NMOS tube M1 and the NMOS tube M2 are short-circuited, and the dead zone time will not be generated. When the dead zone circuit is in a normal working state, the enable signal end EN is high level, at this time the NMOS tube MN2 is turned on, the NMOS tube MN1 and the NMOS tube MN3 are turned off, and the external resistor R of the dead zone time control port DTC can be used. D And the resistance value R of the resistor R3, resistor R4, and NMOS tube MN2 in the loop MN2 , NMOS tube M1 and resistor R1 to adjust the current I1 on the NMOS tube M1, wherein the resistor R3 and the resistor R4 are resistors with complementary temperature coefficients, the NMOS tube M1 and the NMOS tube M2 are of the same model, the resistor R1 and the resistor R2 are also the same in resistance, the current I1 of the NMOS tube M1 and the current I2 of the NMOS tube M2 are equal, and the calculation formula is as follows: In addition, the PMOS tube MP2 is turned on, causing the voltage at point X to be pulled up to the voltage value of the power supply terminal VDD, and the NMOS tube MN5 will be turned on. Affected by the current I2, the capacitor C1 is slowly discharged and gradually decreases to 0V at point Y, forming a triangular wave, and the falling dead time is IN - The signal end recovers the voltage at point X through the second inverter INV2 and delays it slightly, and the third inverter INV3 converts the triangular wave generated by point Y into a delayed rectangular wave form. The rising edge of the IN signal at the IN signal end will have a certain delay, and IN - Signal terminal IN - Similarly, when the input signal IN at the IN signal terminal jumps from a high level to a low level, IN - Signal terminal input signal IN - From low level to high level, PMOS tube MP1 and NMOS tube MN4 are turned on, PMOS tube MP2 and NMOS tube MN5 are turned off, resulting in the falling edge of IN signal end not changing, while IN - The rising edge of the signal end produces a certain delay time.

[0023] The above dead zone circuit has good symmetry, so that the difference between the rising edge dead zone time and the falling edge dead zone time of the circuit is very small, and the dead zone time can be adjusted by changing the external resistor RD The resistance value is used to change the current I2 of the NMOS tube M2, thereby changing the delay time of the dead zone circuit, achieving the purpose of adjustable dead zone. Figure 3-4 It can be seen that the size of the dead zone also changes with the external resistance R D The dead time increases with the increase of resistance value, thus achieving the purpose of adjustable dead time.

[0024] Compared with the related art, the dead time circuit provided by the present invention is composed of an enable signal terminal EN, a power supply terminal VDD, a dead time control port DTC, an external resistor R D , resistor R3, resistor R4, NMOS tube MN1, NMOS tube MN2, NMOS tube MN3, NMOS tube MN4, NMOS tube MN5, capacitor C1, capacitor C2, current mirror component, IN signal terminal, IN- signal terminal, PMOS tube MP1, PMOS tube MP2, first inverter INV1, second inverter INV2, third inverter INV3, adjustable dead time output signal terminal OUT1 and adjustable dead time output signal terminal OUT2 are connected to form. In the above circuit, by changing the external resistor R D The resistance value of the current mirror component is changed to change the current value, thereby changing the delay time of the dead zone circuit, achieving the purpose of adjustable dead zone time; by connecting an external resistor R D Adjusting the dead time is flexible and convenient, and can reduce power consumption and improve performance.

[0025] It should be noted that the above-described embodiments should be understood as illustrative rather than limiting the scope of protection of the present invention, and the scope of protection of the present invention shall be subject to the claims. For those skilled in the art, some non-essential improvements and adjustments made to the present invention still fall within the scope of protection of the present invention without departing from the essence and scope of the present invention.

Claims

1. A dead zone circuit with adjustable dead zone time, characterized in that: The dead zone circuit includes an enable signal terminal EN, a power supply terminal VDD, a dead zone time control port DTC, an external resistor R D , resistor R3, resistor R4, NMOS tube MN1, NMOS tube MN2, NMOS tube MN3, NMOS tube MN4, NMOS tube MN5, capacitor C1, capacitor C2, current mirror component, IN signal terminal, IN- signal terminal, PMOS tube MP1, PMOS tube MP2, first inverter INV1, second inverter INV2, third inverter INV3, adjustable dead time output signal terminal OUT1 and adjustable dead time output signal terminal OUT2; the enable signal terminal EN is simultaneously connected to the NMOS tube MN The gate of the NMOS tube MN2 is connected to the input end of the first inverter INV1, the drain of the NMOS tube MN2 is connected to the first end of the resistor R4, the source of the NMOS tube MN2 is simultaneously connected to the drain of the NMOS tube MN1, the first end of the capacitor C1 and the first input end of the current mirror component, the second end of the resistor R4 is connected to the first end of the resistor R3, the second end of the resistor R3 is connected to the first end of the dead time control port DTC, and the second end of the dead time control port DTC is connected to the external resistor R D The first end of the external resistor R D The second end of the first inverter INV1 is connected to the power supply terminal VDD, the output end of the first inverter INV1 is simultaneously connected to the gate of the NMOS tube MN1 and the gate of the NMOS tube MN3, the source of the NMOS tube MN1 is simultaneously connected to the second end of the capacitor C1 and the second input end of the current mirror component, the first output end of the current mirror component is simultaneously connected to the source of the NMOS tube MN5, the source of the NMOS tube MN4 and the drain of the NMOS tube MN3, the second output end of the current mirror component is connected to the source of the NMOS tube MN3, the gate of the NMOS tube MN4 is simultaneously connected to the IN- signal terminal and the gate of the PMOS tube MP2, the drain of the NMOS tube MN4 is simultaneously connected to the PMOS The source of the S transistor MP2, the first end of the capacitor C2 and the input end of the second inverter INV2 are connected, the drain of the PMOS transistor MP2 is connected to the power supply terminal VDD, the output end of the second inverter INV2 is connected to the adjustable dead time output signal terminal OUT1, the gate of the NMOS transistor MN5 is connected to the IN signal terminal and the gate of the PMOS transistor MP1 at the same time, the drain of the NMOS transistor MN5 is connected to the source of the PMOS transistor MP1, the second end of the capacitor C2 and the input end of the third inverter INV3 at the same time, the output end of the third inverter INV3 is connected to the adjustable dead time output signal terminal OUT2, and the drain of the PMOS transistor MP1 is connected to the power supply terminal VDD.

2. The dead zone circuit with adjustable dead zone time according to claim 1, characterized in that: The current mirror component includes a first current mirror and a second current mirror, and the current I1 flowing through the first current mirror is equal to the current I2 flowing through the second current mirror; the first input end of the first current mirror is simultaneously connected to the drain of the NMOS tube MN1, the first end of the capacitor C1 and the source of the NMOS tube MN2, the second input end of the first current mirror is simultaneously connected to the source of the NMOS tube MN1 and the second end of the capacitor C1, the first output end of the first current mirror is connected to the first input end of the second current mirror, the second output end of the first current mirror is connected to the second input end of the second current mirror, the first output end of the second current mirror is simultaneously connected to the source of the NMOS tube MN5, the source of the NMOS tube MN4 and the drain of the NMOS tube MN3, and the second output end of the second current mirror is connected to the source of the NMOS tube MN3.

3. The dead zone circuit with adjustable dead zone time according to claim 2, characterized in that: The first current mirror includes an NMOS tube M1 and a resistor R1, and the second current mirror includes an NMOS tube M2 and a resistor R2. The source of the NMOS tube M1 is simultaneously connected to the drain of the NMOS tube MN1, the first end of the capacitor C1, the source of the NMOS tube MN2, the gate of the NMOS tube M1, and the gate of the NMOS tube M2. The drain of the NMOS tube M1 is connected to the first end of the resistor R1. The second end of the resistor R1 is simultaneously connected to the source of the NMOS tube MN1, the second end of the capacitor C1, the first end of the resistor R2, and the source of the NMOS tube MN3. The second end of the resistor R2 is connected to the source of the NMOS tube M2. The drain of the NMOS tube M2 is simultaneously connected to the source of the NMOS tube MN5, the source of the NMOS tube MN4, and the drain of the NMOS tube MN3.

4. The dead zone circuit with adjustable dead zone time according to claim 3, characterized in that: The model of the NMOS tube M1 is the same as the model of the NMOS tube M2, the resistance of the resistor R1 is the same as the resistance of the resistor R2, and the temperature coefficients of the resistor R3 and the resistor R4 are complementary; the calculation formulas of the current I1 and the current I2 are as follows: Among them, the V M1 is the voltage value of the NMOS tube M1, and the R MN2 is the resistance value of the NMOS tube MN2.

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