A digital load current estimation method applied to a buck power supply

Abstract

The application discloses a digital load current estimation method applied to a buck power supply, comprising a power stage module, an ADC voltage sampling module, a switch node voltage comparator, a switch cycle counting module and a digital filter module; the ADC voltage sampling module quantifies analog quantities of input voltage and output voltage of the power stage module into input voltage digital quantity and output voltage digital quantity as input parameters of the digital filter module; the switch node voltage comparator compares a switch node voltage of the power stage module with a constant direct current voltage to obtain a switch pulse signal, and obtains duty cycle information of the switch pulse through the switch cycle counting module as input parameters of the digital filter module; the digital filter module estimates inductance current according to the input voltage digital quantity, the output voltage digital quantity and the duty cycle information, estimates capacitance current according to the output voltage digital quantity, obtains an expression of the load current in a z domain, and carries out discretization through a bilinear transformation.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of switching power supply, and particularly relates to a digital load current estimation method applied to a buck power supply. BACKGROUND

[0002] In recent years, in order to further reduce the power consumption of microprocessors and enhance their computing capacity, the power supply demand of microprocessors is developing towards low voltage and large current, and therefore low-voltage large-current Buck converters have gradually become one of the research hotspots. As the power supply of microprocessors, when a large current step change occurs, the low-voltage large-current Buck converter must maintain a low output voltage and good dynamic performance within a strict voltage window tolerance. In addition, with the continuous reduction of the output voltage, how to reduce the output voltage window tolerance has become an important challenge that the low-voltage large-current Buck converter has to face.

[0003] However, the transient current of the Buck converter during load switching can reach tens or even hundreds of amperes. At such a low operating voltage, the window tolerance of voltage change will be small, so that the chip is more likely to fail during the load current transient period. When the load is switched from light load to heavy load, the inductance current cannot immediately increase, so the output capacitor voltage needs to provide part of the energy for the load to use, which will cause the output voltage to drop. At the same time, when the load is switched from heavy load to light load, the inductance current cannot immediately decrease, so it must charge part of the energy to the output capacitor, thereby causing the output voltage to rise. The traditional output voltage operating point is fixed, so when the load is switched from light load to heavy load, it takes a period of time to restore the dropped output voltage to the set reference voltage value, and when the load is switched from heavy load to light load, it takes a period of time to restore the overshoot voltage to the set fixed voltage value. In this way, the system can only use half of the range of the variable window of the output voltage. When the output voltage regulation performance is met, a large output capacitor is needed, and the response time is also slow, and the dynamic performance becomes very poor. Therefore, improving the dynamic performance of the Buck converter is of great significance to the research of the Buck converter power supply system.

[0004] The AVP control technology can make full use of the voltage window tolerance specified in the standard, improve the dynamic characteristics of the system, reduce the requirement for the output filter capacitor, and reduce the size and cost of the converter. The principle is to control the output voltage level according to the load current being higher than the minimum value at heavy load and lower than the maximum value at light load, and then to construct a voltage tolerance window. The AVP control technology makes the voltage tolerance window be fully utilized, and is more suitable for application in the research of reducing the output voltage window tolerance to improve the dynamic performance of the Buck converter. However, the AVP control technology needs to sample the output voltage and the output current, and for the traditional Rdroop resistance sampling, the method brings additional power loss, affecting the efficiency, or a wideband amplifier is needed, which has very high requirements for CMOS production. Moreover, the current information required by the existing AVP control mostly adopts the inductor current, and the inductor current cannot change immediately at the transient state, so there is a certain efficiency problem in the implementation of the AVP control by using the inductor current. SUMMARY

[0005] The application aims to provide a digital load current estimation method applied to a Buck power supply, to improve the regulation ability of the AVP, and to provide load current information for the AVP control, so as to solve the technical problems mentioned in the background art.

[0006] To solve the above technical problems, the specific technical solutions of the application are as follows:

[0007] A digital load current estimation method applied to a Buck power supply, characterized in that it comprises a power stage module, an ADC voltage sampling module, a switching node voltage comparator, a switching period counting module, and a digital filter module.

[0008] The power stage module comprises two switching tubes MOS1 and MOS2, an ideal filter inductor L and its equivalent series resistance R L , an ideal filter capacitor C and its equivalent series resistance R C , and an equivalent series inductor L C , the source electrode of MOS1 is connected to an input voltage V in , the drain electrode of MOS1 is connected to the source electrode of MOS2, the connection point of the drain electrode of MOS1 and the source electrode of MOS2 is a switching node of the power stage module, the drain electrode of MOS2 is grounded, the ideal filter inductor L and the equivalent series resistance R L are connected in series between the switching node and an output voltage V out , the ideal filter capacitor C, the equivalent series resistance R C , and the equivalent series inductor L C are connected in series between the output voltage V out and the ground.

[0009] The ADC voltage sampling module quantifies the analog quantities of the input voltage and the output voltage of the power stage module into input voltage digital quantity and output voltage digital quantity as input parameters of the digital filter module;

[0010] The switch node voltage comparator is an analog input and digital output comparator, which compares the switch node voltage of the power stage module with a constant DC voltage to obtain an actual switch pulse signal, and obtains the duty cycle information of the switch pulse through the switch cycle counting module as the input parameter of the digital filter module.

[0011] The digital filter module estimates the inductor current according to the input voltage digital quantity, the output voltage digital quantity and the duty cycle information, and estimates the capacitor current according to the output voltage digital quantity, and obtains the expression of the load current in the z domain on this basis, and then discretizes it through bilinear transformation.

[0012] Further, the switch cycle counting module counts the number of times of the internal switch signal SW being 1 in a fixed period T s and outputs the duty cycle d once per period. The switch cycle counting module calculates more accurate duty cycle d information through a delay line-based structure, so as to obtain more accurate inductor current information, including average value and peak-to-peak value

[0013] Further, the load current is represented as the difference between the inductor current and the capacitor current, and the load current estimation is composed of inductor current estimation and capacitor current estimation, both of which are realized by the digital controller; in a multi-phase system, i L is represented as the sum of the inductor currents of each phase, and SW represents the interleaved switch node signal; the interleaved switch node signal SW is obtained by performing or logic on the switch node signals SW1 to SWN of each phase, so that the sum of the inductor currents in the interleaved phase is estimated; the estimated inductor current is shown in formula (1), wherein V L is the voltage difference between the switch node V SW and the output voltage V out , k represents the kth estimation period, and r is the sum of the on-resistance of the switch tube and the equivalent series resistance R L : I L_est (k) = -D3i L_est (k-1) + N2[V L (k) + V L (k-1)] (1).

[0014] Further, the digital filter module is designed based on bilinear transformation, and the realization of the digital controller is completed by designing the z-domain expression of the inductance current and the capacitance current transfer function; first, the current is converted from the time domain to the s-domain expression through Laplace transform, and then the z-domain expression is converted through bilinear transform to realize continuous time discretization; the expression of the load current in the z-domain is shown as formula (2), wherein r is the on-resistance of the switch tube and R L and:

[0015]

[0016] The digital load current estimation method applied to the buck power supply has the following advantages:

[0017] 1. The method is purely digital control, only the voltage signal is sampled, and a complex current sampling circuit is not needed, so that the cost of current sampling is greatly reduced.

[0018] 2. The current inner loop is not needed in the loop control, and the entire loop bandwidth only depends on the voltage loop, so that high bandwidth control can be realized.

[0019] 3. The digital estimation method is not sensitive to sampling noise, and the loop control is more stable.

[0020] 4. The load current is directly used as the current information instead of inductance current feedback, so that the transient speed is improved. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is the system structure block diagram of the buck power supply digital load current estimation method of the application;

[0022] Figure 2 is the switch node voltage sampling situation of the application through the analog input and digital output comparator;

[0023] Figure 3 is the circuit structure diagram of the load current estimation concept of the application;

[0024] Figure 4 is the waveform schematic diagram of the load current estimation concept of the application;

[0025] Figure 5 is the function block diagram of the high-resolution duty cycle sampling method based on the delay line of the application;

[0026] Figure 6 is the digital filter block diagram of the application;

[0027] Fig. 7 (a) is a test diagram of the output voltage and the actual current and the estimated current when light load is cut heavy load;

[0028] Figure 7(b) is a test graph of output voltage and actual current and estimated current when heavy load is cut light load. DETAILED DESCRIPTION

[0029] In order to better understand the purpose, structure and function of the present application, the following will be further described in detail in combination with the drawings.

[0030] Figure 1 The system structure block diagram of the application of the digital load current estimation method in the Buck converter includes a power stage module, an ADC voltage sampling module, a switch node voltage comparator, a switch period counting module, and a digital filter module. The input voltage V in and the output voltage V out of the power stage module are processed by the ADC voltage sampling module and output to the digital filter module. The switch node voltage V sw of the power stage module and a constant reference voltage 1.25V are input to the switch node voltage comparator and output to the switch period calculation module, which is then transmitted to the digital filter module for unified processing and calculation. The synchronous rectification Buck converter controls the duty cycle signal V sw of the switch node by controlling the on and off time of the upper switch MOS1 and the lower switch MOS2, thereby controlling the output voltage. L is the filter inductance of the Buck converter, R L is the equivalent series resistance of the filter inductance, C is the ideal filter capacitance, and R C is the series equivalent resistance of the filter capacitance. In order to predict more accurate information, the equivalent series inductance (ESL) L C of the filter capacitance is considered in the design of the digital filter. L C is the equivalent series inductance of the filter capacitance. The input voltage V in and the output voltage V out of the Buck power supply are input to the ADC voltage sampling module to convert the analog voltage to digital quantity and transmit to the digital filter. The switch node voltage V sw between the upper switch MOS1 and the lower switch MOS2 is compared with the reference voltage 1.25V by the comparator, and the actual switch signal SW is output. When the upper switch MOS1 is turned on and the lower switch MOS2 is turned off, the switch node voltage is approximately equal to V in , which is greater than the reference voltage 1.25V, and the comparator output switch signal SW is high. When the upper switch MOS1 is turned off and the lower switch MOS2 is turned on, the switch node voltage is approximately equal to 0V, which is less than the reference voltage 1.25V, and the comparator output switch signal SW is low. The switch period counting module counts a fixed period Ts The number of times the inner switch signal SW is 1, the duty cycle d is output once per cycle. The digital filter calculates the estimated inductor current according to the digital quantity information of the input voltage, output voltage and duty cycle, and estimates the capacitor current according to the output voltage, on the basis of which the expression of the load current in the z domain is obtained, which is discretized by bilinear transformation.

[0031] Figure 2 In order to sample the voltage of the switching node of the analog input and digital output comparator, since the voltage of the switching node V sw Has serious ringing effect and switching noise, so the voltage of the switching node V sw Is compared with the constant DC reference voltage 1.25V, so the output signal SW is a digital signal not affected by noise.

[0032] Figure 3 The circuit structure diagram of the load current estimation concept, Figure 4 The waveform schematic diagram of the load current estimation concept, the two diagrams clearly show the principle of load current estimation. The load current can be represented as the difference between the inductor current and the capacitor current, which can be represented as formula (1):

[0033] i out = i L - i C (1)

[0034] Where, i out is the load current, i L is the inductor current, and i C is the capacitor current. Therefore, the load current estimation is composed of inductor current estimation and capacitor current estimation, both of which are realized by the digital controller. In a multi-phase system, i L Should be represented as the sum of the inductor currents of each phase, and SW should be represented as the interleaved switching node signal. Therefore, the interleaved switching node signal SW is obtained by performing or logic on the switching node signals SW1 to SWN of each phase, which is performed in the digital controller, so that the sum of the inductor currents in the multi-phase interleaved time can be estimated. In steady state, the average value of the inductor current is equal to the load current, and the average value of the capacitor current is 0, and the ripples of the two are cancelled out. In the process of load transient, the inductor current cannot change immediately, so the moment of load step is presented by the capacitor current.

[0035] Figure 5 The function block diagram of the high-resolution switching period counting module based on delay line, the switching period counting module counts a fixed period T sThe number of times the inner switch signal SW is 1, the duty cycle d is output once per cycle. It calculates more accurate duty cycle d information based on the delay line structure, so as to obtain more accurate inductor current information, including the average value and the peak-to-peak value. The digital filter calculates the estimated inductor current according to the input voltage V in , the output voltage V out and the digital quantity information of the duty cycle d, as shown in formula (2), wherein V L is the voltage difference between the switch node V SW and the output voltage V out , k represents the kth estimation period: r is the sum of the on-resistance of the switch tube and R L .

[0036] I L_est (k)=-D3i L_est (k-1)+N2[V L (k)+V L (k-1)] (2)。

[0037] Figure 6 is the block diagram of the digital filter. The corresponding transfer function expression i C (s) of the capacitor current in the s domain is shown in formula (3). When estimating the inductor current and the capacitor current, first, the bilinear transformation is used to discretize them, so that the s domain frequency response method can be used for digital filter design. Based on formula (2) and formula (3), the expression of the load current in the z domain is shown in formula (4). Wherein

[0038]

[0039]

[0040]

[0041] In formula (4), the first polynomial is the inductor current estimation, and the second polynomial is the capacitor current estimation. The expression of the load current in the z domain can be executed in the digital controller.

[0042] Fig. 7(a) and Fig. 7(b) show the test graphs of the actual load current and the estimated load current when the load transient occurs. Fig. 7(a) is the transient state of light load cutting heavy load, and Fig. 7(b) is the transient state of heavy load cutting light load. The blue waveform is the output voltage, the green waveform is the actual current, and the red waveform is the estimated current. It can be seen that the actual load current value can be restored through the load current estimation.

[0043] The application can accurately estimate real-time inductance current and capacitance current information and obtain load current information in the case of sampling input voltage and output voltage only. The application does not need to add additional analog sampling circuits such as resistors, capacitors, operational amplifiers and high-speed ADC sampling much higher than the switching frequency, thereby greatly reducing the cost.

[0044] It can be understood that the application is described by some embodiments, and those skilled in the art can make various changes or equivalent replacements to the features and embodiments without departing from the spirit and scope of the application. In addition, the features and embodiments can be modified to adapt to specific conditions and materials under the guidance of the application without departing from the spirit and scope of the application. Therefore, the application is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the application are within the scope of the application.

Claims

1. A method for digital load current estimation applied to a buck power supply, characterized in that, The power stage module, the ADC voltage sampling module, the switch node voltage comparator, the switch cycle counting module, and the digital filter module are included. The power stage module comprises two switching transistors MOS1 and MOS2, an ideal filter inductor L and its equivalent series resistance R L , an ideal filter capacitor C and its equivalent series resistance R C , and an equivalent series inductor L C The source of MOS1 is connected to an input voltage V in The drain of MOS1 is connected to the source of MOS2, the connection point of the drain of MOS1 and the source of MOS2 is a switching node of the power stage module, the drain of MOS2 is connected to ground, the ideal filter inductor L and the equivalent series resistance R L are connected in series between the switching node and an output voltage V out , the ideal filter capacitor C, the equivalent series resistance R C , and the equivalent series inductor L C are connected in series between the output voltage V out and ground; The ADC voltage sampling module quantifies the analog quantities of the input voltage and the output voltage of the power stage module into input voltage digital quantity and output voltage digital quantity as input parameters of the digital filter module. The switch node voltage comparator is an analog input and digital output comparator, which compares the switch node voltage of the power stage module with a constant DC voltage to obtain an actual switch pulse signal, and obtains the duty cycle information of the switch pulse through the switch cycle counting module as input parameters of the digital filter module. The digital filter module estimates the inductor current according to the input voltage digital quantity, the output voltage digital quantity and the duty cycle information, and estimates the capacitor current according to the output voltage digital quantity, and obtains the expression of the load current in the z domain on this basis, and discretizes it through bilinear transformation. The load current is represented as the difference between the inductor current and the capacitor current, the load current estimation is composed of the inductor current estimation and the capacitor current estimation, both of which are realized by the digital controller; in a multi-phase system, i L is represented as the sum of the inductor currents of each phase, and SW represents the interleaved switching node signal; the interleaved switching node signal SW is obtained by performing OR logic on the switching node signals SW1 to SWN of each phase, so that the sum of the inductor currents in the multi-phase interleaving is estimated; The estimated inductance current is shown in equation (1), where T s is a fixed period, V L is the voltage difference between the switching node V SW and the output voltage V out , k represents the kth estimated period, and r is the sum of the on-resistance of the switching transistor and the equivalent series resistance R L . I L_est (k) = -D3i L_est (k-1) + N2[V L (k) + V L (k-1)] (1); The digital filter module is designed based on bilinear transformation, and the realization of the digital controller is completed by designing the z-domain expression of the inductance current and the capacitance current transfer function. First, the current is converted from the time domain to the s-domain expression through Laplace transformation, and then the z-domain expression is converted through bilinear transformation to realize continuous time discretization. The expression of the load current in the z-domain is shown in equation (2), wherein 2. The method for digital load current estimation for buck power supply according to claim 1, wherein, The switch cycle counting module counts a fixed cycle T through a high frequency counter s The number of times the internal switch signal SW is 1, and the duty cycle d is output once per cycle.

Images