A seven-level inverter topology and a control method thereof

Abstract

The application discloses a seven-level inverter topology and a control method thereof, and relates to the technical field of multi-level structure. The topology comprises mutually symmetrical upper bridge arms and lower bridge arms except for diode directions. A plurality of switch tubes, a direct current bus capacitor and a flying capacitor of the topology are connected according to specific rules, and the working modes of seven different output voltages are realized by controlling the conduction states of the switch tubes. The topology realizes voltage division through the direct current bus capacitor, and realizes intermediate level transition through the flying capacitor. In combination with an optimized circuit structure and a control strategy, the topology has the advantages of simple circuit design, high efficiency, stable output voltage and the like, and is widely applicable to high-voltage and high-power inverter systems.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of multi-level structure, and in particular to a seven-level inverter topology and a control method thereof. BACKGROUND

[0002] Three-level and multi-level converters have become one of the hotspots of research and application at home and abroad in recent years due to their outstanding advantages in high voltage, high quality and high efficiency, etc. Among them, the neutral point clamped (NPC) three-level structure has been most widely researched and applied due to its simple structure and high reliability.

[0003] In addition to MMC, typical medium-voltage inverters include diode clamped (Neutral Point Clamped, NPC) and H-bridge cascaded (Cascaded H-Bridge, CHB) multi-level inverters. Ansalda, ABB, Siemens, GE and other companies have shipboard medium-voltage high-power converter products based on NPC and CHB. Generally speaking, the main topology structure used in systems below 6kV is the diode clamped three-level converter topology, such as ABB's PCS6000 series products (power 32MW) and ACS6000 series products (power 27MW). In order to improve the conversion performance of multi-level inverter circuits, ABB has also launched 5L-NPC products (ACS5000 series, etc.). CHB or NPC+CHB hybrid topology can be used in systems above 6kV.

[0004] In the shipboard integrated power system of direct current voltage 4kV level, NPC three-level inverters can select 3300V IGBT devices to achieve high-voltage and high-power output without device series connection. However, as the power demand of ships gradually increases, the shipboard power system is developing towards 10kV, and the existing NPC topology and power device level cannot meet the requirements. SUMMARY

[0005] The purpose of the present application is to provide a seven-level inverter topology and a control method thereof to achieve high-voltage and high-power output while improving circuit efficiency and output voltage stability.

[0006] The technical solution of the present application is to provide a seven-level inverter topology, which includes an upper bridge arm and a lower bridge arm; the upper bridge arm and the lower bridge arm are connected to a bus at one end and to an inverter at the other end, and the bus voltage is U dc ;

[0007] The upper bridge arm includes a direct current bus capacitor C d1 , a flying capacitor C f1Diodes D1, D3, switch tubes S1, S2, S5, S6, S7; the lower bridge arm includes a DC bus capacitor C d2 , flying capacitor C f2 Diodes D2, D4, switch tubes S3, S4, S8, S9, S 10 ;

[0008] For the upper bridge arm: the negative pole of the DC bus capacitor C d1 is grounded, and the positive pole is connected to the inverter in turn through switch tubes S5, S6, S7, and the negative pole of the DC bus capacitor C d1 is also connected to the flying capacitor C f1 positive pole in turn through switch tubes S2, S1; the positive pole of the flying capacitor C f1 is also connected between switch tubes S5, S6; the negative pole of the flying capacitor C f1 is connected to the anode of diode D1, and the cathode of diode D1 is connected between switch tubes S1, S2; the negative pole of the flying capacitor C f1 is also connected to the anode of diode D3, and the cathode of diode D3 is connected between switch tubes S6, S7;

[0009] For the lower bridge arm: the positive pole of the DC bus capacitor C d2 is grounded, and the negative pole is connected to the inverter in turn through switch tubes S 10 , S9, S8, and the positive pole of the DC bus capacitor C d2 is also connected to the flying capacitor C f2 negative pole in turn through switch tubes S3, S4; the negative pole of the flying capacitor C f2 is also connected between switch tubes S 10 , S9; the positive pole of the flying capacitor C f2 is connected to the cathode of diode D2, and the anode of diode D2 is connected between switch tubes S3, S4; the positive pole of the flying capacitor C f2 is also connected to the cathode of diode D4, and the anode of diode D4 is connected between switch tubes S8, S9;

[0010] For the connection of the upper and lower bridge arms: the negative pole of the DC bus capacitor C d1 is connected to the positive pole of the DC bus capacitor C d2 , the negative pole of the flying capacitor C f1 is connected to the positive pole of the flying capacitor C f2 , the anode of diode D1 is connected to the cathode of diode D2, the anode of diode D3 is connected to the cathode of diode D4, switch tube S2 is connected to switch tube S3, and switch tube S7 is connected to switch tube S8.

[0011] In any of the above technical solutions, further, the DC bus capacitors C d1 and C d2 are respectively located at the positive and negative ends of the DC bus, and Cd1 and C d2 The voltages are all half of the bus voltage, i.e., U dc / 2; Two flying capacitors C f1 and C f2 Located between the bus capacitors, in U dc An intermediate voltage is generated between / 2 and 0, C f1 and C f2 The voltage is 1 / 3 of the DC bus voltage, i.e., U dc / 3; Each switch only needs to withstand the voltage of a flying capacitor or the voltage difference between adjacent levels, and the maximum voltage stress of each switch and diode is U. dc / 3.

[0012] A seven-level inverter topology control method based on any of the seven-level inverter topologies described above is also provided. The control method includes: controlling the switching state of each switching transistor to form several operating schemes with a total of 7 different output voltages, and outputting different voltages to the subsequent inverters.

[0013] In any of the above technical solutions, the topology further outputs 1 / 2U to the subsequent inverter. dc The work plan is as follows:

[0014] Switches S5, S6, and S7 are turned on, while all other switches are turned off. The flying capacitor C... f1 C f2 Neither charging nor discharging is performed, and the output level is 1 / 2U. dc .

[0015] In any of the above technical solutions, the topology further outputs 1 / 3U to the subsequent inverter. dc There are four work plans, in the following order:

[0016] Switches S3, S6, and S7 are turned on, all other switches are turned off, diode D2 is turned on, and flying capacitor C is turned on. f1 Discharge occurs, current flows out to the inverter, and the output level is 1 / 3U. dc ;

[0017] Switches S2, S6, and S7 are turned on, all other switches are turned off, diode D1 is turned on, and flying capacitor C is turned on. f1 During charging, current flows into the inverter, and the output level is 1 / 3U. dc ;

[0018] Switches S3, S4, and S7 are turned on, all other switches are turned off, diode D3 is turned on, and flying capacitor C is turned on. f2 Discharge occurs, current flows out to the inverter, and the output level is 1 / 3U. dc ;

[0019] Switching tubes S3, S4, S8 are turned on, other switching tubes are turned off, diode D4 is turned on, flying capacitor C f2 Charging, current flows into the inverter, output level is 1 / 3U dc .

[0020] In any of the above technical solutions, further, the topology outputs 1 / 6U to the subsequent inverter dc There are three working schemes, in turn:

[0021] Switching tubes S5, S7 are turned on, other switching tubes are turned off, diode D3 is turned on, flying capacitor C f1 Charging, current flows into the inverter, output level is 1 / 3U dc ;

[0022] Switching tubes S5, S8 are turned on, other switching tubes are turned off, diode D4 is turned on, flying capacitor C f1 Discharging, current flows into the inverter, output level is 1 / 3U dc ;

[0023] Switching tubes S6, S7, S 10 are turned on, other switching tubes are turned off, flying capacitors C f1 , C f2 do not charge and discharge, output level is 1 / 6U dc .

[0024] In any of the above technical solutions, further, the topology outputs 1 / 6U to the subsequent inverter

[0025] Switching tubes S3, S7 are turned on, other switching tubes are turned off, diodes D2, D3 are turned on, flying capacitors C f1 , C f2 discharge, current flows into the inverter, output level is 0;

[0026] Switching tubes S2, S8 are turned on, other switching tubes are turned off, diodes D1, D4 are turned on, flying capacitors C f1 , C f2 charge, current flows into the inverter, output level is 0.

[0027] In any of the above technical solutions, further, the topology outputs 1 / 6U to the subsequent inverter dc There are three working schemes, in turn:

[0028] Switching tubes S7, S 10 are turned on, other switching tubes are turned off, diode D3 is turned on, flying capacitor C f2 discharge, current flows into the inverter, output level is -1 / 6U dc ;

[0029] Switching tubes S8, S 10 Turn on, other switching tubes are all turned off, diode D4 is turned on, flying capacitor Cf1 is charged, current flows out to the inverter, and the output level is -1 / 6U f2 Charging, current flows from the inverter, and the output level is -1 / 6U dc ;

[0030] Switching tubes S5, S8 and S9 are turned on, other switching tubes are all turned off, flying capacitor Cf2 is charged, current flows out to the inverter, and the output level is -1 / 6U f1 , C f2 Do not charge and discharge, and the output level is -1 / 6U dc .

[0031] In any of the above technical solutions, further, the topology outputs -1 / 3U dc to the subsequent inverter, and the working scheme has four kinds, which are as follows:

[0032] Switching tubes S1, S2 and S7 are turned on, other switching tubes are all turned off, diode D3 is turned on, flying capacitor Cf1 is charged, current flows out to the inverter, and the output level is -1 / 3Udc;

[0033] Switching tubes S1, S2 and S8 are turned on, other switching tubes are all turned off, diode D4 is turned on, flying capacitor Cf1 is discharged, current flows from the inverter, and the output level is -1 / 3Udc;

[0034] Switching tubes S3, S8 and S9 are turned on, other switching tubes are all turned off, diode D2 is turned on, flying capacitor Cf2 is charged, current flows out to the inverter, and the output level is -1 / 3Udc;

[0035] Switching tubes S2, S8 and S9 are turned on, other switching tubes are all turned off, diode D1 is turned on, flying capacitor Cf2 is discharged, current flows from the inverter, and the output level is -1 / 3Udc.

[0036] In any of the above technical solutions, further, the topology outputs 1 / 2U dc to the subsequent inverter, and the working scheme is as follows:

[0037] Switching tubes S8, S9 and S 10 are turned on, other switching tubes are all turned off, flying capacitor C f1 , C f2 do not charge and discharge, and the output level is -1 / 2U dc .

[0038] The beneficial effects of the present application are:

[0039] The technical solution in this invention constructs a seven-level inverter topology and utilizes DC bus capacitor voltage division and flying capacitor intermediate level transition to achieve precise output voltage grading. It has the advantages of simple circuit structure, high efficiency, good voltage stability, and high power device utilization, and is suitable for high voltage and high power application scenarios. Attached Figure Description

[0040] The advantages of the above and additional aspects of the present invention will become apparent and readily understood in the description of the embodiments in conjunction with the following drawings, wherein:

[0041] Figure 1 This is a schematic diagram of a seven-level inverter topology according to an embodiment of the present invention;

[0042] Figure 2 It is a 1 / 2U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0043] Figure 3 This is the first 1 / 3U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0044] Figure 4 This is the second 1 / 3U type of seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0045] Figure 5 This is the third 1 / 3U of a seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0046] Figure 6 This is the fourth 1 / 3U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0047] Figure 7 This is the first 1 / 6U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0048] Figure 8 This is the second 1 / 6U type of seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0049] Figure 9 This is the third 1 / 6U of a seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0050] Figure 10 This is a schematic diagram of the first zero-output voltage equivalent circuit of a seven-level inverter topology according to an embodiment of the present invention;

[0051] Figure 11 This is a schematic diagram of the second zero-output voltage equivalent circuit of a seven-level inverter topology according to an embodiment of the present invention;

[0052] Figure 12 This is the first type -1 / 6U of a seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0053] Figure 13 This is the second type -1 / 6U of a seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0054] Figure 14 This is the third -1 / 6U of a seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0055] Figure 15 This is the first -1 / 3U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0056] Figure 16 This is the second -1 / 3U type of seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0057] Figure 17 This is the third -1 / 3U of a seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0058] Figure 18 This is the fourth -1 / 3U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram;

[0059] Figure 19 It is a -1 / 2U seven-level inverter topology according to an embodiment of the present invention. dc Equivalent circuit diagram. Detailed Implementation

[0060] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other.

[0061] In the following description, many specific details are set forth in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0062] like Figure 1 As shown, this embodiment provides a seven-level inverter topology and its control method, the topology including:

[0063] Two DC bus capacitors C d1 C d2 Two flying capacitors C f1 C f2 10 switching transistors S1 to S2 10 And four diodes D1 to D4.

[0064] Two DC bus capacitors C d1 and C d2 Located at the positive and negative terminals of the DC bus, they act as a voltage divider, causing the bus voltage U to... dc It remains stable under different voltage levels. d1 and C d2 The voltages are all half of the bus voltage (i.e., U). dc / 2), thereby providing graded support for the circuit's output voltage.

[0065] Two flying capacitors C f1 and C f2 The intermediate level transition is achieved by charging and discharging the capacitors, with two flying capacitors C. f1 and C f2 Located between the bus capacitors, in U dc An intermediate voltage is generated between / 2 and 0. In this voltage divider topology, C f1 and C f2 The voltage is 1 / 3 of the DC bus voltage (i.e., U). dc / 3), to achieve voltage grading between different levels.

[0066] Furthermore, the voltage stress on the switching transistor and diode is determined by the maximum voltage difference across their terminals. Each switching transistor only needs to withstand the voltage of a flying capacitor or the voltage difference between adjacent voltage levels. Since the voltage across the flying capacitor is U... dc / 3, therefore the maximum voltage stress of each switch and diode is U dc / 3. Effectively improves the maximum voltage withstand range of this topology.

[0067] Each switch in the circuit is controlled by a gate signal to control its on or off state, thereby changing the current flow and output level. These switches form multiple different paths according to their connection positions, resulting in a total of seven voltage output levels.

[0068] Diodes D1 to D4 are connected in different branches of the circuit to control the direction of current and prevent the generation of reverse current.

[0069] The circuit is divided into an upper bridge arm and a lower bridge arm, which are symmetrical to each other except for the direction of the diodes. The upper bridge arm includes the DC bus capacitor C. d1 Flying capacitor C f1 Diodes D1 and D3; switching transistors S1, S2, S5, S6, and S7; the lower bridge arm includes the DC bus capacitor C. d2 Flying capacitor C f2 Diodes D2 and D4, switching transistors S3, S4, S8, S9, S 10 .

[0070] Specifically, for the upper bridge arm: DC bus capacitor C d1 The negative terminal is grounded, and the positive terminal is connected to the inverter in sequence through switching transistors S5, S6, and S7. The DC bus capacitor C d1 The negative terminal is also connected to the flying capacitor C in sequence through switching transistors S2 and S1. f1 Positive terminal, flying capacitor C f1 The positive terminal is simultaneously connected between switching transistors S5 and S6; the flying capacitor C f1 The negative terminal of diode D1 is connected to the anode of diode D1, and the cathode of diode D1 is connected between switching transistors S1 and S2; the flying capacitor C f1 The negative terminal is also connected to the anode of diode D3, and the cathode of diode D3 is connected between switching transistors S6 and S7.

[0071] For the lower bridge arm: DC bus capacitance C d2 The positive terminal is grounded, and the negative terminal passes through the switching transistor S in sequence. 10 S9 and S8 are connected to the inverter, and the DC bus capacitor C d2 The positive terminal is also connected to the flying capacitor C in sequence through switching transistors S3 and S4. f2 Negative terminal, flying capacitor C f2 The negative terminal is simultaneously connected to the switching transistor S. 10 Between S9; flying capacitor C f2 The positive terminal of diode D2 is connected to the cathode of diode D2, and the anode of diode D2 is connected between switching transistors S3 and S4; the flying capacitor C f2 The positive terminal is also connected to the cathode of diode D4, and the anode of diode D4 is connected between switching transistors S8 and S9.

[0072] For the connection of the upper and lower bridge arms: DC bus capacitor Cd1 The negative terminal is connected to the DC bus capacitor C. d2 The positive terminal, the flying capacitor C f1 The negative terminal is connected to the flying capacitor C. f2 The positive terminal of diode D1 is connected to the cathode of diode D2, the anode of diode D3 is connected to the cathode of diode D4, switch S2 is connected to switch S3, and switch S7 is connected to switch S8.

[0073] By controlling the switching states of each transistor, 18 voltage output schemes are generated, as shown in Table 1 below:

[0074] Table 1 18 Voltage Output Schemes

[0075]

[0076] like Figures 2 to 19 As shown in the attached diagram, the equivalent circuit of each of the above schemes is illustrated. There are a total of 7 different output levels across the 18 schemes: 1 / 2U dc 1 / 3U dc 1 / 6U dc 0, -1 / 6U dc -1 / 3U dc -1 / 2U dc .

[0077] like Figure 2 As shown, switching transistors S5, S6, and S7 are turned on, while all other switching transistors are turned off. The flying capacitor C... f1 C f2 Neither charging nor discharging is performed, and the output level is 1 / 2U. dc .

[0078] like Figure 3 As shown, switches S3, S6, and S7 are turned on, all other switches are turned off, diode D2 is turned on, and flying capacitor C... f1 Discharge occurs, current flows out to the inverter, and the output level is 1 / 3U. dc .

[0079] like Figure 4 As shown, switches S2, S6, and S7 are turned on, all other switches are turned off, diode D1 is turned on, and flying capacitor C... f1 During charging, current flows into the inverter, and the output level is 1 / 3U. dc .

[0080] like Figure 5 As shown, switches S3, S4, and S7 are turned on, all other switches are turned off, diode D3 is turned on, and flying capacitor C is turned on. f2 Discharge occurs, current flows out to the inverter, and the output level is 1 / 3U. dc .

[0081] like Figure 6 As shown, switches S3, S4, and S8 are turned on, all other switches are turned off, diode D4 is turned on, and flying capacitor C... f2 During charging, current flows into the inverter, and the output level is 1 / 3U. dc .

[0082] like Figure 7 As shown, switching transistors S5 and S7 are turned on, all other switching transistors are turned off, diode D3 is turned on, and flying capacitor C... f1 During charging, current flows out to the inverter, and the output level is 1 / 6U. dc .

[0083] like Figure 8 As shown, switching transistors S5 and S8 are turned on, all other switching transistors are turned off, diode D4 is turned on, and flying capacitor C is turned on. f1 Discharge occurs when current flows into the inverter, resulting in an output level of 1 / 6U. dc .

[0084] like Figure 9 As shown, the switching transistors S6, S7, and S... 10 With the circuit turned on, all other switching transistors are turned off, and the flying capacitor C... f1 C f2 Neither charging nor discharging is performed, and the output level is 1 / 6U. dc .

[0085] like Figure 10 As shown, switching transistors S3 and S7 are turned on, all other switching transistors are turned off, diodes D2 and D3 are turned on, and the flying capacitor C... f1 C f2 When both are discharged, current flows out to the inverter, and the output level is 0.

[0086] like Figure 11 As shown, switching transistors S2 and S8 are turned on, all other switching transistors are turned off, diodes D1 and D4 are turned on, and the flying capacitor C... f1 C f2 When both are charging, current flows into the inverter, and the output level is 0.

[0087] like Figure 12 As shown, switching transistors S7 and S... 10 With the circuit turned on, all other switching transistors are turned off, diode D3 is turned on, and the flying capacitor C... f2 Discharge occurs, current flows out to the inverter, and the output level is -1 / 6U. dc .

[0088] like Figure 13 As shown, switching transistors S8 and S... 10 With the circuit turned on, all other switching transistors are turned off, diode D4 is turned on, and the flying capacitor C... f2During charging, current flows into the inverter, and the output level is -1 / 6U. dc .

[0089] like Figure 14 As shown, switching transistors S5, S8, and S9 are turned on, while all other switching transistors are turned off. The flying capacitor C... f1 C f2 Neither charging nor discharging is performed; the output level is -1 / 6U. dc .

[0090] like Figure 15 As shown, switching transistors S1, S2, and S7 are turned on, all other switching transistors are turned off, diode D3 is turned on, and flying capacitor C... f1 During charging, current flows out to the inverter, and the output level is -1 / 3U. dc .

[0091] like Figure 16 As shown, switching transistors S1, S2, and S8 are turned on, all other switching transistors are turned off, and diode D4 is turned on. Flying capacitor C... f1 Discharge occurs when current flows into the inverter, resulting in an output level of -1 / 3U. dc .

[0092] like Figure 17 As shown, switching transistors S3, S8, and S9 are turned on, all other switching transistors are turned off, diode D2 is turned on, and flying capacitor C... f2 During charging, current flows out to the inverter, and the output level is -1 / 3U. dc .

[0093] like Figure 18 As shown, switches S2, S8, and S9 are turned on, all other switches are turned off, diode D1 is turned on, and flying capacitor C... f2 Discharge occurs when current flows into the inverter, resulting in an output level of -1 / 3U. dc .

[0094] like Figure 19 As shown, the switching transistors S8, S9, and S... 10 With the circuit turned on, all other switching transistors are turned off, and the flying capacitor C... f1 C f2 Neither charging nor discharging is performed, and the output level is -1 / 2U. dc .

[0095] In summary, this invention provides a seven-level inverter topology and its control method. The topology includes an upper bridge arm and a lower bridge arm; both the upper and lower bridge arms are connected to a bus at one end and to an inverter at the other end, with the bus voltage being U. dc .

[0096] The upper bridge arm includes the DC bus capacitor C. d1 Flying capacitor Cf1 Diodes D1 and D3; switching transistors S1, S2, S5, S6, and S7; the lower bridge arm includes the DC bus capacitor C. d2 Flying capacitor C f2 Diodes D2 and D4, switching transistors S3, S4, S8, S9, S 10 .

[0097] For the upper bridge arm: DC bus capacitance C d1 The negative terminal is grounded, and the positive terminal is connected to the inverter in sequence through switching transistors S5, S6, and S7. The DC bus capacitor C d1 The negative terminal is also connected to the flying capacitor C in sequence through switching transistors S2 and S1. f1 Positive terminal, flying capacitor C f1 The positive terminal is simultaneously connected between switching transistors S5 and S6. Flying capacitor C f1 The negative terminal of diode D1 is connected to the anode of diode D1, and the cathode of diode D1 is connected between switching transistors S1 and S2; the flying capacitor C f1 The negative terminal is also connected to the anode of diode D3, and the cathode of diode D3 is connected between switching transistors S6 and S7.

[0098] For the lower bridge arm: DC bus capacitance C d2 The positive terminal is grounded, and the negative terminal passes through the switching transistor S in sequence. 10 S9 and S8 are connected to the inverter, and the DC bus capacitor C d2 The positive terminal is also connected to the flying capacitor C in sequence through switching transistors S3 and S4. f2 Negative terminal, flying capacitor C f2 The negative terminal is simultaneously connected to the switching transistor S. 10 Between S9; flying capacitor C f2 The positive terminal of diode D2 is connected to the cathode of diode D2, and the anode of diode D2 is connected between switching transistors S3 and S4; the flying capacitor C f2 The positive terminal is also connected to the cathode of diode D4, and the anode of diode D4 is connected between switching transistors S8 and S9.

[0099] For the connection of the upper and lower bridge arms: DC bus capacitor C d1 The negative terminal is connected to the DC bus capacitor C. d2 The positive terminal, the flying capacitor C f1 The negative terminal is connected to the flying capacitor C. f2 The positive terminal of diode D1 is connected to the cathode of diode D2, the anode of diode D3 is connected to the cathode of diode D4, switch S2 is connected to switch S3, and switch S7 is connected to switch S8.

[0100] By controlling the switching states of each switching transistor, several operating schemes with a total of 7 different output voltages are formed, which output different voltages to the subsequent inverters.

[0101] The steps in this invention can be adjusted, combined, or deleted according to actual needs.

[0102] The units in the device of the present invention can be merged, divided, or reduced according to actual needs.

[0103] Although the invention has been disclosed in detail with reference to the accompanying drawings, it should be understood that these descriptions are merely exemplary and not intended to limit the application of the invention. The scope of protection of the invention is defined by the appended claims and may include various modifications, alterations, and equivalents made to the invention without departing from the scope and spirit of the invention.

Claims

1. A seven-level inverter topology, characterized in that, The topology includes an upper bridge arm and a lower bridge arm; both the upper and lower bridge arms are connected to the bus at one end and to the inverter at the other end, with the bus voltage being U. dc ; The upper bridge arm includes the DC bus capacitor C. d1 Flying capacitor C f1 Diodes D1 and D3; switching transistors S1, S2, S5, S6, and S7; the lower bridge arm includes the DC bus capacitor C. d2 Flying capacitor C f2 Diodes D2 and D4, switching transistors S3, S4, S8, S9, S 10 ; For the upper bridge arm: DC bus capacitance C d1 The negative terminal is grounded, and the positive terminal is connected to the inverter in sequence through switching transistors S5, S6, and S7. The DC bus capacitor C d1 The negative terminal is also connected to the flying capacitor C in sequence through switching transistors S2 and S1. f1 Positive terminal, flying capacitor C f1 The positive terminal is simultaneously connected between switching transistors S5 and S6; the flying capacitor C f1 The negative terminal of diode D1 is connected to the anode of diode D1, and the cathode of diode D1 is connected between switching transistors S1 and S2; the flying capacitor C f1 The negative terminal is also connected to the anode of diode D3, and the cathode of diode D3 is connected between switching transistors S6 and S7; For the lower bridge arm: DC bus capacitance C d2 The positive terminal is grounded, and the negative terminal passes through the switching transistor S in sequence. 10 S9 and S8 are connected to the inverter, and the DC bus capacitor C d2 The positive terminal is also connected to the flying capacitor C in sequence through switching transistors S3 and S4. f2 Negative terminal, flying capacitor C f2 The negative terminal is simultaneously connected to the switching transistor S. 10 Between S9; flying capacitor C f2 The positive terminal of diode D2 is connected to the cathode of diode D2, and the anode of diode D2 is connected between switching transistors S3 and S4; the flying capacitor C f2 The positive terminal is also connected to the cathode of diode D4, and the anode of diode D4 is connected between switching transistors S8 and S9; For the connection of the upper and lower bridge arms: DC bus capacitor C d1 The negative terminal is connected to the DC bus capacitor C. d2 The positive terminal, the flying capacitor C f1 The negative terminal is connected to the flying capacitor C. f2 The positive terminal of diode D1 is connected to the cathode of diode D2, the anode of diode D3 is connected to the cathode of diode D4, switch S2 is connected to switch S3, and switch S7 is connected to switch S8.

2. The seven-level inverter topology as described in claim 1, characterized in that, The DC bus capacitor C d1 and C d2 Located at the positive and negative terminals of the DC bus, C d1 and C d2 The voltages are all half of the bus voltage, i.e., U dc / 2; Two flying capacitors C f1 and C f2 Located between the bus capacitors, in U dc An intermediate voltage is generated between / 2 and 0, C f1 and C f2 The voltage is 1 / 3 of the DC bus voltage, i.e., U dc / 3; Each switch only needs to withstand the voltage of a flying capacitor or the voltage difference between adjacent levels, and the maximum voltage stress of each switch and diode is U. dc / 3.

3. A seven-level inverter topology control method based on the seven-level inverter topology according to any one of claims 1 and 2, characterized in that, The control method includes controlling the switching state of each switching transistor to form several operating schemes with a total of 7 different output voltages, and outputting different voltages to the subsequent inverter.

4. The seven-level inverter topology control method as described in claim 3, characterized in that, The topology outputs 1 / 2U to the subsequent inverter. dc The work plan is as follows: Switches S5, S6, and S7 are turned on, while all other switches are turned off. The flying capacitor C... f1 C f2 Neither charging nor discharging is performed, and the output level is 1 / 2U. dc .

5. The seven-level inverter topology control method as described in claim 3, characterized in that, The topology outputs 1 / 3U to the subsequent inverter. dc There are four work plans, in the following order: Switches S3, S6, and S7 are turned on, all other switches are turned off, diode D2 is turned on, and flying capacitor C is turned on. f1 Discharge occurs, current flows out to the inverter, and the output level is 1 / 3U. dc ; Switches S2, S6, and S7 are turned on, all other switches are turned off, diode D1 is turned on, and flying capacitor C is turned on. f1 During charging, current flows into the inverter, and the output level is 1 / 3U. dc ; Switches S3, S4, and S7 are turned on, all other switches are turned off, diode D3 is turned on, and flying capacitor C is turned on. f2 Discharge occurs, current flows out to the inverter, and the output level is 1 / 3U. dc ; Switches S3, S4, and S8 are turned on, all other switches are turned off, diode D4 is turned on, and flying capacitor C is turned on. f2 During charging, current flows into the inverter, and the output level is 1 / 3U. dc .

6. The seven-level inverter topology control method as described in claim 3, characterized in that, The topology outputs 1 / 6U to the subsequent inverter. dc There are three work plans, in the following order: Switches S5 and S7 are turned on, all other switches are turned off, diode D3 is turned on, and flying capacitor C is turned on. f1 During charging, current flows out to the inverter, and the output level is 1 / 6U. dc ; Switches S5 and S8 are turned on, all other switches are turned off, diode D4 is turned on, and flying capacitor C is turned on. f1 Discharge occurs when current flows into the inverter, resulting in an output level of 1 / 6U. dc ; Switching transistors S6, S7, S 10 With the circuit turned on, all other switching transistors are turned off, and the flying capacitor C... f1 C f2 Neither charging nor discharging is performed, and the output level is 1 / 6U. dc .

7. The seven-level inverter topology control method as described in claim 3, characterized in that, There are two operating schemes for the topology to output 0 to the subsequent inverter, as follows: Switches S3 and S7 are turned on, all other switches are turned off, diodes D2 and D3 are turned on, and the flying capacitor C... f1 C f2 When all components are discharged, current flows out to the inverter, and the output level is 0. Switches S2 and S8 are turned on, all other switches are turned off, diodes D1 and D4 are turned on, and the flying capacitor C is turned on. f1 C f2 When both are charging, current flows into the inverter, and the output level is 0.

8. The seven-level inverter topology control method as described in claim 3, characterized in that, The topology outputs -1 / 6U to the subsequent inverter. dc There are three work plans, in the following order: Switching transistors S7 and S 10 With the circuit turned on, all other switching transistors are turned off, diode D3 is turned on, and the flying capacitor C... f2 Discharge occurs, current flows out to the inverter, and the output level is -1 / 6U. dc ; Switching transistors S8 and S 10 With the circuit turned on, all other switching transistors are turned off, diode D4 is turned on, and the flying capacitor C... f2 During charging, current flows into the inverter, and the output level is -1 / 6U. dc ; Switches S5, S8, and S9 are turned on, while all other switches are turned off. The flying capacitor C... f1 C f2 Neither charging nor discharging is performed; the output level is -1 / 6U. dc .

9. The seven-level inverter topology control method as described in claim 3, characterized in that, The topology outputs -1 / 3U to the subsequent inverter. dc There are four work plans, in the following order: When switching transistors S1, S2, and S7 are turned on, all other switching transistors are turned off, diode D3 is turned on, flying capacitor Cf1 is charged, current flows out to the inverter, and the output level is -1 / 3Udc. When switching transistors S1, S2, and S8 are turned on, all other switching transistors are turned off, diode D4 is turned on, flying capacitor Cf1 is discharged, current flows into the inverter, and the output level is -1 / 3Udc. When switching transistors S3, S8, and S9 are turned on, all other switching transistors are turned off, diode D2 is turned on, flying capacitor Cf2 is charged, current flows out to the inverter, and the output level is -1 / 3Udc. Switches S2, S8, and S9 are turned on, all other switches are turned off, diode D1 is turned on, flying capacitor Cf2 is discharged, current flows into the inverter, and the output level is -1 / 3Udc.

10. The seven-level inverter topology control method as described in claim 3, characterized in that, The topology outputs 1 / 2U to the subsequent inverter. dc The work plan is as follows: Switching transistors S8, S9, S 10 With the circuit turned on, all other switching transistors are turned off, and the flying capacitor C... f1 C f2 Neither charging nor discharging is performed, and the output level is -1 / 2U. dc .

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