Slew rate controllable system for powering electric machine

Abstract

A slew rate controllable system for powering an electric machine. The system may include a plurality of power transistors operable to convert a direct current (DC) input into an alternating current (AC) output adapted to power the electric machine. The system may further include a gate drive system operable to control a slew rate associated with transitioning the power transistor between open and closed states.

Description

Technical Field

[0001] The present disclosure relates to systems configured for powering an electric machine, such as, but not necessarily limited to, a slew rate controllable system configured for managing transitions of a power switch that operates to provide electrical power to a traction motor of an electric vehicle. Background Art

[0002] In the power inversion process, pulse width modulation, pulse density modulation, delta-sigma modulation, pulse frequency modulation or other application-appropriate binary (on / off) switching control signals can be used to facilitate the transition of switches between different states for the purpose of powering the motor. The control signal can, for example, alternate the conduction state of the switch to generate electrical power with an AC voltage waveform. Some of the more common switches used in higher power applications (such as those used to power traction motors of electric vehicles) can be voltage and / or current controlled between states. Wide bandgap (WBG), GaN, SiC and other semiconductors (such as metal oxide field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBT) semiconductors) can form a class of switches that can support many kinds of switching events. The rate, speed, timing, etc. of the transition of a switching event or more specifically a switch between on and off or open and closed states can be characterized as a conversion rate. Depending on the type of motor being powered (such as, for example, when powering a traction motor used to propel an electric vehicle), the ability to finely select and control the slew rate can be beneficial in minimizing second order effects such as overvoltage spikes, electromagnetic interference (EMI) bearing currents, voltage overshoot, etc. Summary of the invention

[0003] One non-limiting aspect of the present disclosure relates to a slew rate control system configured for fine selection and control of slew rates for switches used in powering an electric motor. The slew rate control system can be particularly beneficial in accurately controlling slew rates of power switches, transistors, etc. used in facilitating powering traction motors of the type commonly employed for propelling electric vehicles. The slew rate control system can dynamically adjust and precisely control slew rates based on a variety of operational and performance and considerations to provide different switching speeds that can balance high switching slew rates against performance advantages and operating environment.

[0004] One non-limiting aspect of the present disclosure relates to a slew rate controllable system for powering a motor. The system may include: a plurality of power transistors operable to convert a direct current (DC) input into an alternating current (AC) output suitable for powering the motor. The power transistor may be operable between an open state and a closed state to facilitate generating the AC output. The system may further include: a gate drive system operable to control a slew rate associated with transitioning the power transistor between an open and a closed state. The gate drive system may include: a plurality of gate drive circuits, each connected to a gate terminal of a corresponding one of the power transistors.

[0005] The gate drive system may include a gate driver operable to provide a control signal to the gate drive circuit adapted to optimize a slew rate of a power transistor associated therewith. The gate driver may control the power switch to generate the AC output.

[0006] The control signal may be operable to direct the gate drive circuit to control a gate-source voltage (Vgs) between a gate terminal and a source terminal of a power transistor associated therewith such that the Vgs controls the power transistor between open and closed states.

[0007] The control signal is operable to direct the gate drive circuit to control a gate current (Ig) to a gate terminal of a power transistor associated therewith such that the Ig controls the power transistor between open and closed states.

[0008] The slew rate controllable system may include: a DC link capacitor connected between the power transistor and a DC source providing the DC input, optionally wherein the control signal optimizes the discharge speed of the DC link capacitor to avoid or minimize voltage overshoot of the power transistor when transitioning between open and closed states.

[0009] The gate driver may be configured to generate the control signal as a function of one or more of: a DC voltage of the DC source, a temperature of the DC link capacitor, a current of one or more of the AC outputs, and a junction temperature, a maximum discharge time, a drain-source voltage (Vds), a voltage threshold (Vth) of one or more of the power transistors.

[0010] The gate drive circuit may include an upper drive switch, an upper resistor, a lower resistor and a lower switch, wherein the upper resistor and the lower resistor are connected in series between the upper drive switch and the lower drive switch, optionally with the gate terminal associated therewith connected between the lower side of the upper resistor and the upper side of the lower resistor.

[0011] The gate drive system may comprise an upper voltage source and a lower voltage source for each of the gate drive circuits, optionally wherein the upper voltage source is connected to the upper switch and the lower voltage source is connected to the lower switch associated therewith.

[0012] The gate drive circuit provides a gate voltage to a gate terminal associated therewith, optionally wherein the gate voltage is proportional to a voltage difference between upper and lower voltage sources and the resistance of upper and lower resistors.

[0013] The control signal may be configured to selectively control the upper and lower switches between open and closed states to set the gate voltage and thereby the slew rate of the power transistor associated therewith.

[0014] The control signal may be a pulse width modulation (PWM) signal operable between a high voltage and a low voltage, optionally wherein the high voltage transitions an upper or lower switch receiving it to the open state, and the low voltage transitions an upper or lower switch receiving it to the closed state.

[0015] The gate driver may selectively vary a duty cycle for the PWM signal to control a switching rate of a power transistor associated therewith.

[0016] The gate drive circuit may include an upper voltage source, a lower voltage source, an upper switch, a lower switch and an upper resistor, optionally wherein the upper switch is connected in series with the upper voltage source and connected to the upper side of the upper resistor, the lower switch is connected in series with the lower voltage source and the lower side of the upper resistor, and the gate terminal associated therewith is connected to the lower side of the upper resistor.

[0017] The gate drive circuit may include an upper voltage source, a lower voltage source, an upper switch, a lower switch and a lower resistor, optionally, wherein the upper switch is connected in series with the upper voltage source and connected to the upper side of the lower resistor, the lower switch is connected in series with the lower voltage source and the lower side of the lower resistor, and the gate terminal associated with it is connected to the upper side of the lower resistor.

[0018] One non-limiting aspect of the present disclosure relates to a slew rate controllable system for powering a traction motor of a vehicle. The system may include: a plurality of power switches operable to convert a direct current (DC) input into an alternating current (AC) output suitable for powering the traction motor. The power switch may be operable between an open state and a closed state to facilitate generating the AC output. The system may further include: a gate drive system operable to control a slew rate associated with transitioning the power switch between an open and a closed state, optionally wherein a plurality of gate drive circuits are respectively connected to gate terminals of corresponding ones of the power switches and operable to control a gate-source voltage (Vgs) between a gate terminal and a source terminal of the power switch associated therewith, wherein the Vgs controls the power switch between an open and a closed state.

[0019] The gate drive circuit may include an upper voltage source, a lower voltage source, an upper switch, an upper resistor and a lower resistor, wherein the upper switch is connected in series with the upper voltage source, the upper resistor, the lower resistor and the lower voltage source, optionally wherein the gate terminal associated therewith is connected between a lower side of the upper resistor and an upper side of the lower resistor.

[0020] The gate drive system may be configured to generate control signals for setting the Vgs of each gate drive circuit by controlling the upper and lower switches between open and closed states, respectively.

[0021] The gate drive system may be configured to determine the control signal as a function of one or more of: a DC voltage of the DC input, a temperature of a DC link capacitor connected across the DC source, a current of one or more of the AC outputs, and a junction temperature, a maximum discharge time, a drain-source voltage (Vds), or a voltage threshold (Vth) of one or more of the power switches.

[0022] One non-limiting aspect of the present disclosure relates to a slew rate controllable system for powering a traction motor of a vehicle. The system may include: a plurality of power switches operable to convert a direct current (DC) input into an alternating current (AC) output suitable for powering the traction motor. The power switch may be operable between an open state and a closed state to facilitate generating the AC output. The system may include: a gate drive system operable to control a slew rate associated with transitioning the power switch between an open state and a closed state, optionally wherein a plurality of gate drive circuits are respectively connected to gate terminals of corresponding ones of the power switches, the gate drive circuits being operable to control a gate current (Ig) to a gate terminal of the power switch associated therewith, wherein the Ig controls the power switch between an open state and a closed state.

[0023] The slew rate controllable system may include: a DC link capacitor connected between the power switch and a DC source providing the DC input, so that the gate drive system is operable to control the slew rate of the power switch to optimize the discharge speed of the DC link capacitor to avoid or minimize voltage overshoot when transitioning between open and closed states.

[0024] These features and advantages, along with other features and advantages of the present teachings, may be apparent from the following detailed description of modes for implementing the present teachings when taken in conjunction with the accompanying drawings. It should be understood that although the following drawings and embodiments may be described separately, their individual features may be combined into additional embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which may be incorporated in and constitute a part of this specification, illustrate implementations of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0026] Figure 1 A partial schematic diagram of a slew rate controllable system according to one non-limiting aspect of the present disclosure is illustrated.

[0027] Figure 2 A partial schematic diagram of a gate drive circuit according to one non-limiting aspect of the present disclosure is illustrated.

[0028] Figure 3 A graph illustrating a controlled slew rate according to one non-limiting aspect of the present disclosure is illustrated.

[0029] Figure 4 A partial schematic diagram of one of the gate drive circuits omitting the lower resistor according to one non-limiting aspect of the present disclosure is illustrated.

[0030] Figure 5A partial schematic diagram of one of the gate drive circuits omitting the upper resistor according to one non-limiting aspect of the present disclosure is illustrated. DETAILED DESCRIPTION

[0031] As required, detailed embodiments of the present disclosure may be disclosed herein; however, it is understood that the disclosed embodiments may merely exemplify the present disclosure that may be embodied in various and alternative forms. The figures may not necessarily be drawn to scale; some features may be exaggerated or minimized to show details of particular components. Therefore, the specific structural and functional details disclosed herein may not necessarily be construed as limiting, but rather merely as a representative basis for teaching those skilled in the art to employ the present disclosure in various ways.

[0032] Figure 1 A partial schematic diagram of a slew rate controllable system 10 according to one non-limiting aspect of the present disclosure is illustrated. The system 10 may include a gate drive system 12 operable to power an electric machine 14, which for exemplary purposes is primarily described as an electric motor 14, typically referred to as a traction motor 14. The electric motor 14 may be of the type employed within a vehicle, such as an electric vehicle, to provide mechanical traction operable to propel the vehicle or otherwise perform work. As described in more detail below, the gate drive system 12 may be operable to: finely select and control slew rates for a plurality of power switches, transistors, etc. S1, S2, ... S6 used as part of a power inverter module (PIM) 16 to facilitate powering the electric machine 14. The system 12 may dynamically adjust and precisely control slew rates based on a variety of operational and performance considerations to provide different switching speeds capable of balancing high switching slew rates relative to performance advantages and operating environments. Although primarily described with respect to selectively controlling switching rates for switches S1, S2, ... S6 used in an electric vehicle, those skilled in the art should readily recognize that the capabilities of system 12 are advantageous in facilitating powering other types of motors 14 that would similarly benefit from minimizing second order effects (such as overvoltage spikes, electromagnetic interference (EMI) bearing currents, voltage overshoots, etc.).

[0033] The vehicle may include a rechargeable energy storage system (RESS) 20 for storing and supplying electrical power for various systems included on the vehicle. The RESS 20 may be a battery or other energy storage device capable of selectively supplying electrical power to and receiving electrical power from the motor 14 via the PIM 16. When powering the motor 14, the RESS 20 may be configured as a source for providing a direct current (DC) input 22 to the PIM 16. A DC link capacitor 24 may be provided therebetween to smooth, filter, and otherwise process the DC input 22 for use by the PIM 16. The PIM 16 is shown to include six power transistors / switches S1, S2, ... S6, each having a gate terminal G, a drain terminal D, and a source terminal S. The gate terminal G of each switch S1, S2, ... S6 may be separately and independently connected to one of a plurality of gate drive circuits 26. The switches S1, S2, ... S6 may correspond to a wide range of switches S1, S2, ... S6, including wide bandgap (WBG), GaN, SiC and other similar semiconductors, such as metal oxide field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs) semiconductors. The gate drive system 12 may include: a gate controller 30, operable to separately and specifically control the gate drive circuit 26 to control the rate, speed, timing, etc. of switching events for the switches S1, S2, ... S6, that is, to control the transition of the switches S1, S2, ... S6 between on and off or open and closed states. The transition of the switches S1, S2, ... S6 between states may be characterized as a slew rate, wherein the gate drive circuit 26 is operable to select the slew rate for each of the switches S1, S2, ... S6, respectively, according to a corresponding control signal 32 provided from the gate controller 30. One non-limiting aspect of the present disclosure contemplates that the gate drive circuit 26 is operable to provide a gate voltage and / or a gate current to a gate terminal G associated therewith, wherein the corresponding gate voltage or gate current is operable to transition the associated switches S1, S2, ... S6 between open and closed states, i.e., to control whether the corresponding switches S1, S2, ... S6 are active or inactive.

[0034] The gate controller 30 may include a gate driver 34 configured to provide a control signal 32 to each of the gate drive circuits 26, respectively. The gate driver 34 may be used in this manner to facilitate switching events for the switches S1, S2, ... S6, whereby the DC input 22 may be converted to an alternating current (AC) output 38. The AC output 38 may be generated in the illustrated manner to provide a multi-phase output having a plurality of AC signals 40, 42, 44 suitable for use in powering the motor 14, which for non-limiting purposes are shown as corresponding to a three-phase implementation in which the three-phase AC output 38 is provided to an AC bus or winding of the motor 14, such as via corresponding input terminals for the associated AC input. As noted above, the use of the gate drive system 12 to facilitate a controllable slew rate based method for controlling switching events and thereby facilitating conversion of the DC input 22 to an AC output 38 suitable for powering the motor 14 is presented for non-limiting purposes, as the present disclosure fully contemplates that the gate drive system 12 may be operated in other environments and for other purposes. Thus, in addition to the illustrated use case where the switches S1, S2, ... S6 may be configured to operate as a unidirectional or bidirectional DC / AC converter, the present disclosure also fully contemplates the use of the gate drive system 12 to control the slew rate for the switches S1, S2, ... S6 or other devices.

[0035] The gate controller 30 may include a non-transitory computer-readable storage medium having a plurality of non-transitory instructions stored thereon, which when executed with an associated one or more processors may be operable in accordance with the present disclosure to facilitate generating control signals 32 in a manner that provides a desired slew rate while also managing the AC output required for proper powering of the motor 14. Although not shown in individual detail, a plurality of sensors or other features may be employed to facilitate measuring or otherwise determining the DC voltage of the DC source 20, the temperature of the DC link capacitor 24, the current of one or more of the AC outputs 38, and the junction temperature, maximum discharge time, drain-source voltage (Vds), voltage threshold (Vth) of one or more of the switch / power transistors S1, S2, ... S6. The gate controller 30 may process sensor measurements, metrics, etc. to determine the desired slew rate for each of the switches S1, S2, ... S6, which may include: selecting the control signal 32 to optimize the discharge speed of the DC link capacitor 24 to avoid or minimize voltage overshoot for the switches S1, S2, ... S6 when transitioning between open and closed states. The gate controller 30 may be used in this manner to vary the slew rates of the switches S1 , S2 , . . . S6 in real time within and between switching events, and may optionally be used in an isolated manner to alter the slew rate to be selected based on operating conditions, desired performance, etc.

[0036] Figure 2 A partial schematic diagram of one of the gate drive circuits 26 according to one non-limiting aspect of the present disclosure is illustrated. Although the connection will be repeated separately for each switch S1, S2, ... S6, the gate drive circuit 26 is shown as connected to the gate terminal G of the switch S1 for exemplary purposes. In this way, the gate drive circuit 26 is shown as being connectable to the gate terminal G due to the switch S1 being configured as a voltage and / or current control type of the switch S1, whereby the gate voltage and / or gate current provided to the gate terminal G can be used to transform the switch S1 between the open and closed states, i.e., to control the switching event. In the case where the switch S1 adopts an alternative configuration, the gate drive circuit 26 can be similarly adapted to provide a voltage and / or current to the corresponding terminal. The gate drive circuit 26 may include an upper gate switch 46, an upper resistor 48, a lower resistor 50, and a lower gate switch 52, wherein the upper gate switch 46 is driven by an upper voltage source 58 and the lower gate switch 52 is driven by a lower voltage source 60. The upper gate switch 46 is shown to be connected in series with the upper voltage source 58, the upper resistor 48, the lower resistor 50 and the lower voltage source 60, wherein the upper gate switch 46 is connected between the upper voltage source 58 and the upper side of the upper resistor 48, the gate terminal G is connected between the lower side of the upper resistor 48 and the upper side of the lower resistor 50, the upper side of the lower resistor 50 is connected to the lower side of the upper resistor 48, and the lower gate switch 52 is connected between the lower voltage source 60 and the lower side of the lower resistor 50.

[0037] The gate driver 34 can be configured to generate a control signal 32 having separate control signals 62, 64, which are suitable for selectively opening and closing the upper and lower gate switches 46, 52 and thereby controlling the gate voltage and / or current provided to the gate terminal G. The control signals 62, 64 can correspond to a pulse width modulation (PWM) signal that can operate between a high voltage H and a low voltage L to control the upper and lower gate switches 46, 52 to a closed state and an open state, respectively. The duty cycle of the control signal 32 can be varied to finely adjust the gate voltage and / or current at a precise level depending on the desired conversion rate, for example, to facilitate real-time adjustment of the conversion rate according to the desired operation of the motor 14. PWM duty cycle control can be used to change the output current in and out of the gate G (capacitor) of the switch. The fastest gate speed and conversion rate can be preferred for switching due to hysteresis and energy considerations. The method of controlling the PWM duty cycle can be based on the DC bus voltage and current to allow optimal efficiency and reliability. For a 400-800V system 12, for example, the present disclosure may be used to adapt the PIM 16 for each bus. In the illustrated configuration, the control signals 62, 64 may be operable to direct the gate drive circuit 26 to control a gate-source voltage (Vgs) between a gate terminal G and a source terminal of the switch S1, wherein Vgs controls the power transistor between an open and closed state, and / or the control signals 62, 64 may be operable to direct the gate drive circuit 26 to control a gate current (Ig) to the gate terminal G, wherein Ig controls the power transistor between an open and closed state. The Vgs and Ig provided to the gate terminal G may be proportional to a voltage difference between the upper and lower voltage sources 58, 60 and the resistance of the upper and lower resistors 48, 50.

[0038] The gate driver 34 may be configured to provide different control signals 32 to the upper and lower gate switches 46, 52 (such as, in the illustrated manner), whereby the control signals 32 may have different duty cycles. This ability to vary the duty cycle or other aspects of the control signals 32 used to transition the upper and lower gate switches 46, 52 between states, respectively, may be beneficial in enabling the gate controller 30 to control Vgs and / or Ig with a very fine and precise level of granularity, wherein the resulting voltages and currents are set based on the resistivity of the upper and lower voltage sources 58, 60 and the upper or lower resistors 48, 50. The gate controller 30 may optionally control the voltages provided with each of the upper and lower voltage sources 58, 60 to further enhance its ability to finely select the voltage and / or current provided to the gate terminal G. In some cases, for example, the control signal 32 can be used to selectively open or deactivate either of the upper and lower gate switches 46, 52, optionally in concert with varying the voltages of the upper and lower voltage sources 58, 60, so as to thereby even further increase specificity in selecting and achieving a desired conversion rate.

[0039] Figure 3A graph 70 of a method of controlling a slew rate according to one non-limiting aspect of the present disclosure is illustrated. The graph 70 is shown as including a vertical axis 72 for voltage and current and a horizontal axis 74 for time. A first waveform 78 represents a voltage between drain and source terminals (Vds), a second waveform 80 represents a current through the drain terminal (Id), a third waveform 82 represents Vgs, and a fourth waveform 84 represents Ig. The graph 70 illustrates an exemplary scenario whereby the slew rate of switch S1, i.e., dV / dt and / or dI / dt, can be selectively controlled based on the transition characteristics of switch S1. The period occurring before time T0 can correspond to switch S1 being off or active, after which at time T0, the gate drive circuit 26 begins to power gate terminal G at an initial slew rate. From time T0 to time T1, the initial slew rate can be maintained as Id increases. At approximately time T1 or slightly thereafter as the slope of Vgs decreases and / or as Vds drops, the D drive circuit can begin to power the gate terminal G at an intermediate slew rate, which can be useful in controlling the slope or rate at which Vds correspondingly drops. At approximately time T2 or once Vds reaches or approaches its minimum value, a final or greater transition can be achieved. The ability to selectively control Vgs and / or Ig during the transition of switch S1 can be beneficial in maximizing performance or more particularly maximizing the slew rate, since switch S1 progresses through various states associated with transitioning from an open state to a closed state. The method can continue in this manner, whereby a slew rate for the drive circuit 26 and the ensuing transitions of the switches S1, S2, ... S6 to which it is connected can be achieved to control the DC to AC conversion required to power the motor 14.

[0040] Figure 4 A partial schematic diagram of one of the gate drive circuits 26 with the lower resistor 50 omitted according to one non-limiting aspect of the present disclosure is illustrated. Figure 5 A partial schematic diagram of one of the gate drive circuits 26 omitting the upper resistor 48 according to one non-limiting aspect of the present disclosure is illustrated. These alternative configurations for the gate drive circuit 26 can illustrate the ability of the present disclosure to minimize or reduce the number of circuit components while still maintaining a desired level of slew rate control. Although not shown, the present disclosure additionally contemplates similarly omitting the upper and / or lower switches 46, 52. Figure 2 , 4 5, for example, some of the switches S1, S2, ... S6 can be connected to one type of drive circuit 26, while one or more of the other switches S1, S2, ... S6 are connected to a drive circuit 26 having a different configuration. This capability can further enhance the beneficial control of the slew rate in the manner contemplated herein.

[0041] As supported above, the present disclosure relates to a system and method for implementing real-time slew rate (SR) control of power transistors for inverters and converters. It can include a minimum amount of hardware as a voltage / current source and a low voltage switch, with pulse modulation to control the gate current to achieve many slew rates. This can equivalently transform the gate drive circuit into a charge pump for the gate capacitor, thereby enabling an advantageous control method of a variable speed gate drive circuit that allows fine tuning of switching performance to be optimized between losses, overshoot, EMI, and bearing currents. In this way, the gate drive circuit can be operable to optionally utilize faster switching, minimal switching losses, and improved maximum power capabilities, turning on / off the power switch to convert electrical power between DC and AC, thereby limiting the effects of electrical stress on the power switch, ringing, conductive and radiated EMI, and motor terminal voltage overshoot (PDIV) and bearing currents. The gate drive system may include the following design features: pulse modulation control for varying transistor switching slew rate in real time and between and within switching events; applicability for voltage source and current source based or hybrid gate drivers; feed forward control using a look up table (LUT) to alter slew rate based on operating conditions (i.e., Vdc, current, Vth, and junction temperature); feedback control based on operating conditions, transistor signal sensing, and component-to-component variations and degradation; tuned pulse modulation control at maximum junction temperature for turn-on transients and minimum junction temperature for turn-off transients; slew rate control to compensate for transistor / switch component-to-component variations, i.e., Vth, gate resistor, stray inductance; feedback control based on operating conditions, transistor signal sensing, and component-to-component variations and degradation; Class D topology for pulse modulated gate drive system; modulation control for controlling slew rate to achieve capacitor discharge while managing I / V overshoot; slew rate control for switching on / off solid state relays (SSRs) / e-fuses to manage I / V overshoot and protect caps and batteries; slew rate control for increasing losses for BEV-HEAT and reducing soft turn-off time when the switch is shorted; control for regulating dI / dt to prevent secondary effects that change dV / dt; making EMI frequency characteristics constant; and / or high voltage discharge by keeping one side of the switch on and PWMing the other side of the switch on that side (high side or low side) using PWM-based slew rate control to manage voltage overshoot.

[0042] The terms "comprise", "include" and "have" are inclusive and thus specify the presence of the claimed features, steps, operations, elements or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements or parts. The order of steps, processes and operations can be changed when possible, and additional or replaceable steps can be adopted. As used in this specification, the term "or" includes any and all combinations of the associated listed items. The term "any of..." is understood to include any possible combination of the cited items, including "any of" the cited items. "One", "one", "the", "at least one" and "one or more" are used interchangeably to indicate that at least one of the items exists. A plurality of such items may exist unless the context clearly indicates otherwise. Unless otherwise clearly or clearly indicated in view of the context including the attached claims, all values ​​of parameters (e.g., quantity or condition) should be understood to be modified by the term "about" in all instances, regardless of whether "about" actually appears before the value. A component "configured to" perform a specified function is able to perform the specified function without modification, rather than only having the possibility to perform the specified function after further modification. In other words, the described hardware, when expressly configured to perform the specified function, is specifically selected, created, implemented, utilized, programmed, and / or designed for the purpose of performing the specified function.

[0043] Although various embodiments have been described, the description is intended to be illustrative rather than limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations within the scope of the embodiments are possible. Any feature of any embodiment may be used in combination with any other feature or element in any other embodiment, or any feature of any embodiment may be substituted for any other feature or element in any other embodiment, unless specifically constrained. Accordingly, the embodiments should not be constrained except in accordance with the appended claims and their equivalents. Moreover, various modifications and changes may be made within the scope of the appended claims. Although several modes for implementing many aspects of this teaching have been described in detail, those skilled in the art of these teachings should recognize various alternative aspects for practicing this teaching within the scope of the appended claims. It is intended that all the subjects contained in the above description or shown in the accompanying drawings should be interpreted as illustrating and illustrating the entire scope of the alternative embodiments, and those skilled in the art should recognize that the alternative embodiments are implied by the included content, structurally and / or functionally equivalent to the included content, or otherwise made obvious based on the included content, and are not limited to those embodiments that are explicitly depicted and / or described.

Claims

1. A controllable conversion rate system for powering a motor, comprising: a plurality of power transistors operable to convert a direct current (DC) input into an alternating current (AC) output suitable for powering the motor, the power transistors being operable between an open state and a closed state to facilitate generating the AC output; as well as A gate drive system operable to control a slew rate associated with transitioning the power transistor between open and closed states, the gate drive system comprising: a plurality of gate drive circuits respectively connected to gate terminals of corresponding ones of the power transistors.

2. The slew rate controllable system according to claim 1, wherein: The gate drive system includes a gate driver operable to provide a control signal suitable for optimizing the slew rate to the gate drive circuit and control the power switch to generate the AC output.

3. The slew rate controllable system according to claim 2, wherein: The control signal is operable to direct the gate drive circuit to control a gate-source voltage (Vgs) between a gate terminal and a source terminal of a power transistor associated therewith, the Vgs controlling the power transistor between open and closed states.

4. The slew rate controllable system according to claim 2, wherein: The control signal is operable to direct the gate drive circuit to control a gate current (Ig) to a gate terminal of a power transistor associated therewith, the Ig controlling the power transistor between open and closed states.

5. The slew rate controllable system according to claim 2, further comprising: A DC link capacitor is connected between the power transistor and a DC source providing the DC input, and the control signal optimizes the discharge speed of the DC link capacitor to avoid or minimize voltage overshoot of the power transistor when transitioning between open and closed states.

6. A slew rate controllable system according to claim 5, wherein: The gate driver is configured to generate the control signal as a function of one or more of: a DC voltage of the DC source, a temperature of the DC link capacitor, a current of one or more of the AC outputs, and a junction temperature, a maximum discharge time, a drain-source voltage (Vds), a voltage threshold (Vth) of one or more of the power transistors.

7. The slew rate controllable system according to claim 2, wherein: The gate drive circuit includes an upper drive switch, an upper resistor, a lower resistor and a lower switch, wherein the upper resistor and the lower resistor are connected in series between the upper drive switch and the lower drive switch, wherein the gate terminal associated therewith is connected between the lower side of the upper resistor and the upper side of the lower resistor.

8. The slew rate controllable system according to claim 7, wherein: The gate drive system includes an upper voltage source and a lower voltage source for each of the gate drive circuits, wherein the upper voltage source is connected to the upper switch and the lower voltage source is connected to the lower switch associated therewith.

9. The slew rate controllable system according to claim 2, wherein: The gate drive circuit includes an upper voltage source, a lower voltage source, an upper switch, a lower switch and an upper resistor, wherein the upper switch is connected in series with the upper voltage source and connected to the upper side of the upper resistor, the lower switch is connected in series with the lower voltage source and the lower side of the upper resistor, and the gate terminal associated with it is connected to the lower side of the upper resistor.

10. The slew rate controllable system according to claim 2, wherein: The gate drive circuit includes an upper voltage source, a lower voltage source, an upper switch, a lower switch and a lower resistor, wherein the upper switch is connected in series with the upper voltage source and connected to the upper side of the lower resistor, the lower switch is connected in series with the lower voltage source and the lower side of the lower resistor, and the gate terminal associated with it is connected to the upper side of the lower resistor.

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