Compensation circuit

Abstract

The embodiment of the invention discloses a compensating circuit which is used for calibrating offset voltage of an operational amplifier. The compensation circuit comprises an INREF, an isolation operational amplifier U1, an output isolation operational amplifier circuit, an OUTREF, an output acquisition ADC, a VOS imbalance compensation circuit and a resistance error compensation circuit. The isolation operational amplifier U1 is connected with the INREF, the output isolation operational amplifier circuit is connected with the isolation operational amplifier U1, the OUTREF is connected with the output isolation operational amplifier circuit, the output acquisition ADC is connected with the OUTREF, the VOS imbalance compensation circuit is connected with the output acquisition ADC, and the VOS imbalance compensation circuit is connected with the output isolation operational amplifier circuit. And the output acquisition ADC is used for acquiring an output value of the OUTREF and feeding back the output value to the VOS imbalance compensation circuit and the resistance error compensation circuit.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of compensation circuits, and in particular, to a compensation circuit. Background Art

[0002] In the process of cell dotting, generally 120 signal power supplies are needed. In previous designs, we usually provide a separate DAC for each power supply, so that each power supply can be configured with any voltage separately. In the actual dotting process, these 120 power supplies will only use less than 8 different voltages, and most of the channels have the same output voltage. In order to save costs, we share 8 REF voltages for these 120 power supplies, which means that one REF voltage needs to be provided to 120 channels. Although each channel is implemented using the same circuit, the offset voltage of the op amp used in the circuit is inconsistent, and the resistor accuracy also has a certain deviation, resulting in a large error when different channels output the same voltage. In order to solve this problem, we added a compensation calibration circuit to each REF parallel circuit to calibrate the op amp offset voltage and resistor accuracy in the parallel circuit. Summary of the invention

[0003] An embodiment of the present application provides a compensation circuit that can calibrate the offset voltage of an operational amplifier.

[0004] An embodiment of the present application provides a compensation circuit, including: IN_REF, isolation amplifier U1, output isolation amplifier circuit, OUT_REF, output acquisition ADC, VOS offset compensation circuit and resistance error compensation circuit; The isolation op amp U1 is connected to the IN_REF, the output isolation op amp circuit is connected to the isolation op amp U1, the OUT_REF is connected to the output isolation op amp circuit, the output acquisition ADC is connected to the OUT_REF, the VOS offset compensation circuit is connected to the output acquisition ADC, and the VOS offset compensation circuit is connected to the output isolation op amp circuit; the output acquisition ADC is used to collect the output value of the OUT_REF and feed it back to the VOS offset compensation circuit and the resistance error compensation circuit.

[0005] Optionally, the resistance error compensation circuit includes a resistor R1, a resistor R2, a resistor R3 and a MUX multiplexer; One end of the resistor R1 is connected to the isolation amplifier U1, and the other end is connected to the output isolation amplifier circuit; One end of the resistor R2 is connected between the resistor R1 and the output isolation amplifier circuit, and the other end is connected to the resistor R3; The resistor R3 is grounded; One end of the MUX multiplexer is connected between the resistor R2 and the resistor R3, and the other end is grounded, connected in parallel with the resistor R3, and is used to receive the output value of the OUT_REF collected by the output collection ADC; the resistance of the MUX multiplexer is adjustable; The VOS offset compensation circuit is connected between the resistor R2 and the resistor R3 and is connected in parallel with the resistor R3.

[0006] Optionally, the MUX multiplexer includes resistor R4, resistor R5, resistor R6 and resistor R7; the resistor R4, the resistor R5, the resistor R6 and the resistor R7 are connected in parallel; the MUX multiplexer controls the on and off of the resistor R4, the resistor R5, the resistor R6 and the resistor R7 respectively through 4 separate selection switches.

[0007] Optionally, the VOS offset compensation circuit includes an operational amplifier U3 and a DAC; The DAC, the output end is connected to the input end of the operational amplifier U3, and receives the output value of the OUT_REF collected by the output collection ADC; The output terminal of the operational amplifier U3 is connected between the resistor R2 and the resistor R3.

[0008] Optionally, the output isolation operational amplifier circuit includes an operational amplifier U2, a resistor R8 and a resistor R9; One input terminal of the operational amplifier U2 is connected to the resistor R1, and the output terminal is connected to the OUT_REF; one end of the resistor R8 is connected between the operational amplifier U2 and the OUT_REF, and the other end is connected to the resistor R9; the other input terminal of the operational amplifier U2 is connected between the resistor R8 and the resistor R9; one end of the resistor R9 is connected to the resistor R8, and the other end is grounded.

[0009] Optionally, the MUX multiplexer is connected in parallel with the resistor R3, and the MUX multiplexer is used to achieve a linear adjustment of the resistance value of the resistor R3 by 16 thousandths.

[0010] Optionally, the IN_REF is set to 0V.

[0011] Optionally, the sum of the resistance values ​​of the resistor R2 and the resistor R3 is 1008 thousandths of the resistance value of the resistor R1.

[0012] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages: The compensation circuit in the embodiment of the present application can effectively eliminate the output reference voltage (OUT_REF) deviation caused by the VOS offset voltage and resistance error of the op amp through the VOS offset compensation circuit and the resistance error compensation circuit. By outputting the output value of OUT_REF collected in real time by the output acquisition ADC, the system can detect the error caused by the VOS offset or resistance error, and adjust it through the compensation circuit so that OUT_REF always remains at the expected ideal value. This dynamic adjustment not only improves the accuracy of the output voltage, but also enhances the stability and robustness of the system, ensuring that OUT_REF is always stable and reliable under different working conditions, thereby improving the performance of the entire system, and is particularly suitable for applications requiring high voltage accuracy. And it can play the role of resistance adjustment, which plays a key role in the compensation circuit, used to compensate for the output voltage deviation caused by the resistance error. The resistance error compensation circuit in the circuit can detect the change or mismatch of the resistance value in real time, and compensate by adjusting the resistance value in the circuit or by other means, thereby reducing the influence of the resistance error on the output reference voltage (OUT_REF). This resistance adjustment mechanism ensures that the output voltage of the circuit is closer to the ideal value and improves the voltage accuracy. Especially in applications where resistance accuracy is more important, it can significantly improve the stability and overall performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic diagram of the structure of an embodiment of a compensation circuit in an embodiment of the present application; Figure 2 Schematic diagram of the structure of another embodiment of the compensation circuit in the embodiment of the present application. DETAILED DESCRIPTION

[0014] An embodiment of the present application provides a compensation circuit for calibrating an operational amplifier offset voltage.

[0015] The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0016] See also Figure 1 to Figure 2 In the embodiment of the present application, one embodiment of the compensation circuit includes: IN_REF, isolation amplifier U1, output isolation amplifier circuit, OUT_REF, output acquisition ADC, VOS offset compensation circuit and resistance error compensation circuit; The isolation op amp U1 is connected to IN_REF, the output isolation op amp circuit is connected to the isolation op amp U1, OUT_REF is connected to the output isolation op amp circuit, the output acquisition ADC is connected to OUT_REF, the VOS offset compensation circuit is connected to the output acquisition ADC, and the VOS offset compensation circuit is connected to the output isolation op amp circuit; the output acquisition ADC is used to collect the output value of OUT_REF and feed it back to the VOS offset compensation circuit and the resistance error compensation circuit.

[0017] Circuit composition and connection relationship: IN_REF and isolation amplifier U1: Connection: IN_REF is the input reference voltage, which is directly connected to the input of the isolation amplifier U1.

[0018] Function: The isolation amplifier U1 is used to isolate the IN_REF signal from other parts of the circuit to prevent external interference from affecting the input signal and ensure the stability of the input voltage.

[0019] Isolation amplifier U1 and output isolation amplifier circuit: Connections: The output of the isolation amplifier U1 is connected to the input of the output isolation amplifier circuit.

[0020] Function: The output isolation amplifier circuit further amplifies or adjusts the signal from U1 to generate the required output reference voltage (OUT_REF).

[0021] Output isolation amplifier circuit and OUT_REF: Connections: The output of the output isolation op amp circuit is connected to OUT_REF.

[0022] Function: OUT_REF is the output reference voltage of the circuit, which usually needs to be accurate and stable for use by subsequent circuits.

[0023] Output acquisition ADC and OUT_REF: Connection: Output reference voltage (OUT_REF) input to output acquisition ADC.

[0024] Function: ADC collects the output voltage of OUT_REF, converts it into a digital signal, and feeds the value back to the compensation circuit. This signal is used to calculate and adjust the error in the circuit.

[0025] Output acquisition ADC and VOS offset compensation circuit: Connection: The output signal of the ADC is connected to the VOS offset compensation circuit.

[0026] Function: The VOS offset compensation circuit calculates the required adjustment based on the output signal fed back from the ADC in order to correct the error caused by the op amp input offset voltage (VOS).

[0027] VOS offset compensation circuit and output isolation amplifier circuit: Connection: VOS offset compensation circuit connected to output isolation op amp circuit.

[0028] Function: The compensation circuit adjusts the output isolation amplifier circuit according to the result of VOS offset compensation to reduce or eliminate the deviation caused by VOS and ensure the accuracy of OUT_REF.

[0029] Output acquisition ADC and resistance error compensation circuit: Connection: The output signal of the ADC is also fed back to the resistor error compensation circuit.

[0030] Function: The resistance error compensation circuit is used to correct the signal deviation caused by the resistance error and further improve the accuracy of the output voltage.

[0031] Circuit working principle: IN_REF input signal processing: The circuit isolates the IN_REF signal through the isolation amplifier U1 and transmits it to the output isolation amplifier circuit. The output isolation amplifier circuit generates the required output reference voltage OUT_REF.

[0032] Output acquisition and feedback: The output acquisition ADC is responsible for acquiring the actual output voltage of OUT_REF and feeding it back to the VOS offset compensation circuit and the resistance error compensation circuit.

[0033] Compensation circuit adjustment: The VOS offset compensation circuit calculates and adjusts the output isolation amplifier circuit based on the information fed back by the ADC to compensate for the deviation caused by the amplifier input offset voltage (VOS). At the same time, the resistor error compensation circuit adjusts based on the feedback to eliminate the impact of the resistor error.

[0034] Feedback regulation: By adjusting the working state of the output isolation amplifier circuit, the output voltage of OUT_REF is ultimately ensured to be consistent with the expected value, thereby ensuring the accuracy and stability of the circuit.

[0035] The compensation circuit can effectively eliminate the output reference voltage (OUT_REF) deviation caused by the VOS offset voltage and resistance error of the op amp through the VOS offset compensation circuit and the resistance error compensation circuit. By real-time sampling the output value of OUT_REF through the output acquisition ADC, the system can detect the error caused by VOS offset or resistance error, and adjust it through the compensation circuit so that OUT_REF always remains at the expected ideal value. This dynamic adjustment not only improves the accuracy of the output voltage, but also enhances the stability and robustness of the system, ensuring that OUT_REF is always stable and reliable under different working conditions, thereby improving the performance of the entire system, and is particularly suitable for applications requiring high voltage accuracy. And it can play the role of resistance adjustment. Resistance adjustment plays a key role in this compensation circuit, which is used to compensate for the output voltage deviation caused by resistance error. The resistance error compensation circuit in the circuit can detect the change or mismatch of the resistance value in real time, and compensate by adjusting the resistance value in the circuit or by other means, thereby reducing the influence of the resistance error on the output reference voltage (OUT_REF). This resistance adjustment mechanism ensures that the output voltage of the circuit is closer to the ideal value and improves the voltage accuracy. Especially in applications where resistance accuracy is more important, it can significantly improve the stability and overall performance of the system.

[0036] Optionally, the resistance error compensation circuit includes a resistor R1, a resistor R2, a resistor R3 and a MUX multiplexer; One end of the resistor R1 is connected to the isolation amplifier U1, and the other end is connected to the output isolation amplifier circuit; One end of the resistor R2 is connected between the resistor R1 and the output isolation amplifier circuit, and the other end is connected to the resistor R3; Resistor R3 is grounded; One end of the MUX multiplexer is connected between the resistor R2 and the resistor R3, and the other end is grounded and connected in parallel with the resistor R3, and is used to receive the output value of OUT_REF collected by the output acquisition ADC; the resistance of the MUX multiplexer is adjustable; The VOS offset compensation circuit is connected between the resistor R2 and the resistor R3 and is connected in parallel with the resistor R3.

[0037] The design of the resistance error compensation circuit includes resistors R1, R2, R3 and MUX multiplexers to accurately adjust the resistance value and eliminate the output voltage deviation caused by the resistance error. Specifically, resistor R1 is connected between the isolation amplifier U1 and the output isolation amplifier circuit, resistor R2 is connected between resistor R1 and the output isolation amplifier circuit, and resistor R3 is grounded. The MUX multiplexer is used to select between resistor R2 and resistor R3, and its resistance is adjustable. The resistance value is dynamically adjusted by receiving the OUT_REF output value collected by the output acquisition ADC. The VOS offset compensation circuit is also connected between resistor R2 and resistor R3 to further optimize the adjustment of the circuit. Through this configuration, the circuit can adjust the resistance value according to the actual collected output voltage value, effectively compensate for the resistance error, and thus ensure the accuracy and stability of the output reference voltage (OUT_REF).

[0038] Optionally, the MUX multiplexer includes resistor R4, resistor R5, resistor R6 and resistor R7; resistor R4, resistor R5, resistor R6 and resistor R7 are connected in parallel; the MUX multiplexer controls the on and off of resistor R4, resistor R5, resistor R6 and resistor R7 respectively through 4 separate selection switches.

[0039] The MUX multiplexer accurately realizes dynamic adjustment of the resistors by including parallel resistors R4, R5, R6 and R7, and corresponding 4 selection switches. Each selection switch controls the on-off state of resistors R4, R5, R6 and R7 respectively, and the equivalent resistance value of the MUX multiplexer is adjusted by changing the parallel combination of resistors. This design enables the circuit to flexibly select different resistor combinations according to the OUT_REF value fed back by the output acquisition ADC, thereby realizing accurate compensation of the output reference voltage, further reducing the influence of the resistance error on the circuit output, and improving the adjustment range and accuracy of the compensation circuit.

[0040] Optionally, the VOS offset compensation circuit includes op amp U3 and DAC; The output of DAC is connected to the input of the operational amplifier U3, and receives the output value of OUT_REF collected by the output acquisition ADC; The output terminal of the operational amplifier U3 is connected between the resistor R2 and the resistor R3.

[0041] The VOS offset compensation circuit includes an op amp U3 and a DAC to accurately calibrate the error caused by the op amp offset voltage (VOS). Specifically, the output of the DAC is connected to the input of the op amp U3 to receive the output value of OUT_REF fed back by the output acquisition ADC, and to generate a corresponding compensation voltage signal based on the value. The output of the op amp U3 is connected between resistors R2 and R3 to directly introduce the compensation signal into the circuit, thereby dynamically adjusting the error caused by the op amp offset voltage to ensure the accuracy and stability of the OUT_REF output voltage. Through this design, the deviation caused by the op amp VOS is effectively eliminated, further improving the circuit performance and output accuracy.

[0042] Optionally, the output isolation operational amplifier circuit includes an operational amplifier U2, a resistor R8 and a resistor R9; One input terminal of the operational amplifier U2 is connected to the resistor R1, and the output terminal is connected to OUT_REF; one end of the resistor R8 is connected between the operational amplifier U2 and OUT_REF, and the other end is connected to the resistor R9; the other input terminal of the operational amplifier U2 is connected between the resistor R8 and the resistor R9; one end of the resistor R9 is connected to the resistor R8, and the other end is grounded.

[0043] The output isolation op amp circuit ensures the stability and accuracy of the output reference voltage (OUT_REF) through the precise design of op amp U2, resistor R8 and resistor R9. One input terminal of op amp U2 is connected to the isolation op amp U1 through resistor R1, and its output terminal is directly connected to OUT_REF. One end of resistor R8 is connected between the output terminal of op amp U2 and OUT_REF, and the other end is connected to resistor R9. One end of resistor R9 is connected to resistor R8, and the other end is grounded. The other input terminal of op amp U2 is connected to the connection point of resistor R8 and resistor R9. The feedback loop of the op amp is formed by the resistor network structure, which not only realizes the isolation and amplification of the output voltage, but also accurately controls and stabilizes the voltage output, further reduces the output fluctuation caused by circuit interference or load changes, and improves the stability and linearity of OUT_REF.

[0044] Optionally, a MUX multiplexer is connected in parallel with the resistor R3, and the MUX multiplexer is used to achieve a linear adjustment of the resistance value of the resistor R3 by 16 thousandths.

[0045] The MUX multiplexer is designed in parallel with the resistor R3, so that the circuit can achieve a linear adjustment of the resistance value of the resistor R3 by 16 thousandths. Specifically, by adjusting the combination state of each parallel resistor in the MUX multiplexer (such as resistors R4, R5, R6 and R7), the equivalent resistance value of the MUX multiplexer can be changed, thereby forming a precise adjustment mechanism with the parallel combination of resistor R3. Such a design greatly improves the accuracy of the resistance adjustment in the circuit, so that the output reference voltage (OUT_REF) can be slightly linearly compensated according to the output acquisition ADC feedback value, effectively reducing the impact of the resistance error on the circuit performance, ensuring the high-precision output of OUT_REF, and meeting the needs of precision circuit adjustment.

[0046] Optionally, IN_REF is set to 0V.

[0047] IN_REF is set to 0V, which simplifies the reference setting of the circuit and provides a clear reference point for subsequent compensation operations. When IN_REF is 0V, OUT_REF should also be 0V in theory, but due to problems such as VOS and resistance errors in the op amp, the actual output may deviate from 0V. By monitoring the deviation value of OUT_REF in real time through the output acquisition ADC, and combining the VOS offset compensation circuit and the resistance error compensation circuit for precise adjustment, these deviations can be effectively eliminated, and ultimately OUT_REF is consistent with IN_REF. This design further enhances the compensation effect and output stability of the circuit, and is particularly suitable for application scenarios of high-precision reference circuits.

[0048] Optionally, the sum of the resistance values ​​of the resistor R2 and the resistor R3 is 1008 thousandths of the resistance value of the resistor R1.

[0049] The sum of the resistances of resistors R2 and R3 is precisely set to 1008 thousandths of the resistance of resistor R1. This precise resistance ratio design is designed to optimize the feedback characteristics and compensation performance of the circuit, ensuring that the circuit has a high degree of linearity and stability when performing voltage regulation and error compensation. Through this specific resistance configuration, the voltage distribution and feedback response in the circuit can be effectively balanced, further improving the control accuracy of the compensation circuit on the OUT_REF output voltage, meeting the performance requirements of high-precision circuits, and reducing the compensation error caused by the resistance ratio deviation.

[0050] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0051] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0052] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0053] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0054] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, read-only memory), random access memory (RAM, random access memory), disk or optical disk and other media that can store program code.

Claims

1. A compensation circuit, characterized in that: include: IN_REF, isolation amplifier U1, output isolation amplifier circuit, OUT_REF, output acquisition ADC, VOS offset compensation circuit and resistance error compensation circuit; The isolation op amp U1 is connected to the IN_REF, the output isolation op amp circuit is connected to the isolation op amp U1, the OUT_REF is connected to the output isolation op amp circuit, the output acquisition ADC is connected to the OUT_REF, the VOS offset compensation circuit is connected to the output acquisition ADC, and the VOS offset compensation circuit is connected to the output isolation op amp circuit; the output acquisition ADC is used to collect the output value of the OUT_REF and feed it back to the VOS offset compensation circuit and the resistance error compensation circuit.

2. The compensation circuit according to claim 1, characterized in that: The resistance error compensation circuit includes a resistor R1, a resistor R2, a resistor R3 and a MUX multiplexer; One end of the resistor R1 is connected to the isolation amplifier U1, and the other end is connected to the output isolation amplifier circuit; One end of the resistor R2 is connected between the resistor R1 and the output isolation amplifier circuit, and the other end is connected to the resistor R3; The resistor R3 is grounded; One end of the MUX multiplexer is connected between the resistor R2 and the resistor R3, and the other end is grounded, connected in parallel with the resistor R3, and is used to receive the output value of the OUT_REF collected by the output collection ADC; the resistance of the MUX multiplexer is adjustable; The VOS offset compensation circuit is connected between the resistor R2 and the resistor R3 and is connected in parallel with the resistor R3.

3. The compensation circuit according to claim 2, characterized in that: The MUX multiplexer includes resistor R4, resistor R5, resistor R6 and resistor R7; the resistor R4, the resistor R5, the resistor R6 and the resistor R7 are connected in parallel; the MUX multiplexer controls the on and off of the resistor R4, the resistor R5, the resistor R6 and the resistor R7 respectively through 4 separate selection switches.

4. The compensation circuit according to claim 2, characterized in that: The VOS offset compensation circuit includes an operational amplifier U3 and a DAC; The DAC, the output end is connected to the input end of the operational amplifier U3, and receives the output value of the OUT_REF collected by the output collection ADC; The output terminal of the operational amplifier U3 is connected between the resistor R2 and the resistor R3.

5. The compensation circuit according to claim 2, characterized in that: The output isolation operational amplifier circuit includes an operational amplifier U2, a resistor R8 and a resistor R9; One input terminal of the operational amplifier U2 is connected to the resistor R1, and the output terminal is connected to the OUT_REF; one end of the resistor R8 is connected between the operational amplifier U2 and the OUT_REF, and the other end is connected to the resistor R9; the other input terminal of the operational amplifier U2 is connected between the resistor R8 and the resistor R9; one end of the resistor R9 is connected to the resistor R8, and the other end is grounded.

6. The compensation circuit according to claim 2, characterized in that: The MUX multiplexer is connected in parallel with the resistor R3, and the MUX multiplexer is used to achieve a linear adjustment of the resistance value of the resistor R3 by 16 thousandths.

7. The compensation circuit according to any one of claims 1 to 6, characterized in that: The IN_REF is set to 0V.

8. The compensation circuit according to any one of claims 2 to 6, characterized in that: The sum of the resistance values ​​of the resistor R2 and the resistor R3 is 1008 thousandths of the resistance value of the resistor R1.

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