Radio frequency amplifier with reconfigurable gain slope, transceiver and communication equipment

Abstract

The invention discloses a gain slope reconfigurable radio frequency amplifier, a transceiver and communication equipment wherein the gain slope reconfigurable radio frequency amplifier comprises an input matching circuit, a first-stage amplifying circuit, a gain slope reconfiguration circuit, a second-stage amplifying circuit, an output matching circuit and a power supply and filter circuit. The power supply and filter circuit is respectively connected with the first-stage amplification circuit and the second-stage amplification circuit, the input matching circuit, the first-stage amplification circuit, the gain slope reconstruction circuit, the second-stage amplification circuit and the output matching circuit are sequentially connected in series, and a first capacitor, a second capacitor, a third capacitor and a fourth capacitor are sequentially arranged between the front stage and the rear stage; and the gain slope reconstruction circuit can change the output load impedance of the first-stage amplification circuit and / or the source impedance of the second-stage amplification circuit, so that the gain of the first-stage amplification circuit and / or the second-stage amplification circuit is changed, and a reconfigurable gain slope is presented after the gains of the first-stage amplification circuit and the second-stage amplification circuit are superposed.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency circuits, and in particular to a radio frequency amplifier, a transceiver and a communication device with reconfigurable gain slope. Background Art

[0002] RF transceivers usually include power amplifier circuits, low-noise amplifier circuits, amplitude control circuits, phase control circuits, frequency conversion circuits, power synthesis / distribution circuits, driver amplifier circuits, RF switches, etc. In order to achieve low noise in the receiver, the low-noise amplifier must achieve sufficient gain under power consumption constraints while maintaining good input matching and linearity; in the transmitter, the design of the power amplifier needs to optimize output power, power efficiency and linearity; and the amplitude control circuit and phase control circuit need to achieve high-precision amplitude and phase adjustment and control at the lowest possible power consumption.

[0003] In amplifier design, due to process and key indicator constraints, the designed gain is usually a negative slope; if process deviation occurs, the amplifier gain slope in the manufactured circuit will vary greatly; especially when the channel contains multiple gain units, when there are PVT (process, voltage, temperature) fluctuations, the flatness deterioration of the total channel gain is difficult to predict. Summary of the invention

[0004] In order to solve the above problems, the present invention proposes a gain slope reconfigurable RF amplifier, transceiver and communication equipment. By introducing a gain slope reconstruction circuit between the first-stage amplifier circuit and the second-stage amplifier circuit, the RF amplifier gain slope can be reconstructed after the integrated circuit is manufactured, thereby improving the adverse effects of PVT changes on the gain flatness of the RF transceiver channel. The present invention has good engineering practicality, universal and standardized circuit design, simple circuit structure, and easy chip integration.

[0005] The technical solution adopted by the present invention is as follows:

[0006] A gain slope reconfigurable radio frequency amplifier comprises an input matching circuit, a first-stage amplifying circuit, a gain slope reconstruction circuit, a second-stage amplifying circuit, an output matching circuit, and a power supply and a filtering circuit, wherein the power supply and the filtering circuit are respectively connected to the first-stage amplifying circuit and the second-stage amplifying circuit, the input matching circuit, the first-stage amplifying circuit, the gain slope reconstruction circuit, the second-stage amplifying circuit, and the output matching circuit are sequentially connected in series, and a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor are sequentially arranged between the front and rear stages; the gain slope reconstruction circuit can change the output load impedance of the first-stage amplifying circuit and / or the source impedance of the second-stage amplifying circuit, thereby changing the gain of the first-stage amplifying circuit and / or the second-stage amplifying circuit, so that the gains of the first-stage amplifying circuit and the second-stage amplifying circuit are superimposed to present a reconfigurable gain slope.

[0007] Furthermore, the gain slope reconstruction circuit includes a first adjustable capacitor, a second adjustable capacitor, a first coupled inductor and a second coupled inductor; the first adjustable capacitor and the first coupled inductor are connected in parallel, and one end is grounded, and the other end is connected to the second capacitor; the second adjustable capacitor and the second coupled inductor are connected in parallel, and one end is grounded, and the other end is connected to the third capacitor; the first coupled inductor and the second coupled inductor are coupled through an electromagnetic field, and the coupling coefficient is k.

[0008] Furthermore, in the gain slope reconstruction circuit, the first adjustable capacitor includes m switching capacitors connected in parallel, and the second adjustable capacitor includes n switching capacitors connected in parallel; the size of the first adjustable capacitor and / or the second adjustable capacitor can be changed by opening or closing the switching capacitor, thereby changing the load impedance of the first-stage amplifier circuit and / or the source impedance of the second-stage amplifier circuit, that is, changing the gain of the RF amplifier, thereby reconstructing the gain slope of the RF amplifier.

[0009] Further, the first-stage amplifier circuit includes a first bias voltage source, a first NMOS transistor, a second NMOS transistor, a first source inductor, a first drain inductor, a fifth capacitor, a first resistor and a third resistor, wherein:

[0010] The gate of the first NMOS transistor is connected to a first bias voltage source through a first resistor and is connected to a first capacitor, and the first resistor can prevent the radio frequency signal from entering the first bias voltage source; the source of the first NMOS transistor is grounded through a first source inductor or directly grounded, and the drain is connected to the source of the second NMOS transistor;

[0011] The gate of the second NMOS transistor is connected to the power supply and the filter circuit through a third resistor and receives a DC bias voltage, and the third resistor can prevent the radio frequency signal from entering the power supply and the filter circuit; the fifth capacitor is connected between the gate of the second NMOS transistor and the ground to filter out the radio frequency noise of the gate of the second NMOS transistor; the drain of the second NMOS transistor is connected to the power supply and the filter circuit through the first drain inductor, and is connected to the second capacitor;

[0012] The first NMOS transistor can realize the conversion of the gate input radio frequency voltage signal into a drain current signal. The current signal passes through the second NMOS transistor and flows through the parallel load composed of the first drain inductor and the subsequent circuit.

[0013] Further, the second-stage amplifier circuit includes a second bias voltage source, a third NMOS transistor, a fourth NMOS transistor, a second drain inductor, a sixth capacitor and a fourth resistor, wherein:

[0014] The gate of the third NMOS transistor is connected to the second bias voltage source through a second resistor and is connected to a third capacitor, and the second resistor can prevent the radio frequency signal from entering the second bias voltage source; the source of the third NMOS transistor is grounded, and the drain is connected to the source of the fourth NMOS transistor;

[0015] The gate of the fourth NMOS transistor is connected to the power supply and the filter circuit through a fourth resistor and receives a DC bias voltage, and the fourth resistor can prevent the radio frequency signal from entering the power supply and the filter circuit; the sixth capacitor is connected between the gate of the fourth NMOS transistor and the ground to filter the gate radio frequency noise; the drain of the fourth NMOS transistor is connected to the power supply and the filter circuit through the second drain inductor, and is connected to the fourth capacitor;

[0016] The third NMOS transistor can realize the conversion of the gate input radio frequency voltage signal into a drain current signal. The current signal passes through the fourth NMOS transistor and flows through the parallel load composed of the second drain inductor and the subsequent circuit.

[0017] Furthermore, the power supply and filtering circuit includes a first power supply, a seventh capacitor and an eighth capacitor. After the seventh capacitor and the eighth capacitor are connected in parallel, one end is grounded and the other end is connected to the first power supply to complete power supply filtering.

[0018] Furthermore, one end of the input matching circuit is connected to the RF input, and the other end is connected to the first capacitor, so as to achieve impedance matching between the RF input source impedance and the input end of the first-stage amplifier circuit.

[0019] Furthermore, one end of the output matching circuit is connected to the fourth capacitor, and the other end is connected to the input end of the subsequent circuit, so as to achieve impedance matching between the output end of the second-stage amplifier circuit and the subsequent circuit.

[0020] A radio frequency transceiver comprises the above-mentioned radio frequency amplifier with reconfigurable gain slope.

[0021] A communication device comprises the above-mentioned radio frequency transceiver.

[0022] The beneficial effects of the present invention are:

[0023] (1) Since PVT changes and other reasons may deteriorate the gain flatness of the RF transceiver, the present invention introduces a gain slope reconstruction circuit between the first-stage amplifier circuit and the second-stage amplifier circuit. By configuring the gain slope reconstruction circuit, the gain slope of the RF amplifier can be reconstructed, thereby improving the adverse effects of PVT changes on the gain flatness of the RF transceiver, thereby improving the performance of the communication equipment.

[0024] (2) The present invention can reconstruct the amplifier gain slope after chip manufacturing is completed, optimize the RF transceiver channel gain flatness, shorten the chip development cycle, and reduce chip development and testing costs. The present invention has good engineering practicality, universal and standardized circuit design, simple circuit structure, and easy chip integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 The present invention is a schematic diagram of a gain slope reconfigurable radio frequency amplifier.

[0026] Figure 2 It is a schematic diagram of an embodiment of a gain slope reconfigurable radio frequency amplifier of the present invention.

[0027] Figure 3 The present invention is a schematic diagram of a gain slope reconstruction circuit embodiment of a gain slope reconfigurable radio frequency amplifier.

[0028] Figure 4 It is a schematic diagram of the optimal flatness (or zero slope) of the gain curve of a gain slope reconfigurable radio frequency amplifier of the present invention.

[0029] Figure 5 It is a schematic diagram of a positive slope of a gain curve of a gain slope reconfigurable radio frequency amplifier of the present invention.

[0030] Figure 6 It is a schematic diagram of a negative slope of a gain curve of a gain slope reconfigurable radio frequency amplifier of the present invention.

[0031] Figure 7 The present invention is a schematic diagram of a radio frequency transceiver including a gain slope reconfigurable radio frequency amplifier. DETAILED DESCRIPTION

[0032] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, the specific implementation methods of the present invention are now described. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention, that is, the embodiments described are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0033] Example 1

[0034] See also Figure 1The present embodiment provides a gain slope reconfigurable radio frequency amplifier, comprising an input matching circuit, a first capacitor C1, a first-stage amplifier circuit, a second capacitor C2, a gain slope reconstruction circuit, a third capacitor C3, a second-stage amplifier circuit, a fourth capacitor C4, an output matching circuit, and a power supply and a filter circuit connected in series with the first-stage amplifier circuit and the second-stage amplifier circuit, as described in detail as follows.

[0035] One end of the input matching circuit is connected to the RF input, which may be the output of the previous stage circuit, and the other end is connected to one end of the first capacitor C1 to achieve impedance matching between the RF input source impedance and the input end of the first stage amplifier circuit.

[0036] The first-stage amplifier circuit and the second-stage amplifier circuit provide gain for the gain slope reconfigurable radio frequency amplifier. The gain slope reconstruction circuit can change the output load impedance of the first-stage amplifier circuit and / or the source impedance of the second-stage amplifier circuit, thereby changing the gain of the first-stage amplifier circuit and / or the second-stage amplifier circuit. The gain of the first-stage amplifier circuit and the gain of the second-stage amplifier circuit are superimposed to present a reconfigurable gain slope.

[0037] One end of the output matching circuit is connected to the other end of the fourth capacitor C4, and the other end is connected to the input end of the subsequent circuit to achieve impedance matching between the output end of the second stage amplifier circuit and the subsequent circuit. In addition, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 achieve the function of blocking DC signals and passing AC signals.

[0038] Preferably, see Figure 2 In the first-stage amplifier circuit, the gate of the first NMOS transistor MN1 is connected to the first bias voltage source vb1 through the first resistor R1, and is also connected to the other end of the first capacitor C1. The first resistor R1 prevents the RF signal from entering the first bias voltage source vb1; the source of the first NMOS transistor MN1 is grounded through the first source inductor Ls1 or directly grounded, and its drain is connected to the source of the second NMOS transistor MN2.

[0039] The first power supply VDD of the power supply and filtering circuit provides a DC bias to the gate of the second NMOS transistor MN2 through the third resistor R3. The fifth capacitor C5 is connected between the gate of the second NMOS transistor MN2 and the ground to filter out the gate radio frequency noise. The third resistor R3 prevents the radio frequency signal from entering the first power supply VDD. The drain of the second NMOS transistor MN2 is connected to the first power supply VDD through the first drain inductor Ld1, and is connected to one end of the second capacitor C2.

[0040] In this embodiment, the first NMOS transistor MN1 realizes the conversion of the gate input RF voltage signal into a drain current signal. The current signal passes through the second NMOS transistor MN2 and flows through the parallel load composed of the first drain inductor Ld1 and the subsequent circuit.

[0041] Preferably, see Figure 2 In the second-stage amplifier circuit, the gate of the third NMOS transistor MN3 is connected to the second bias voltage source vb2 through the second resistor R2, and is also connected to the other end of the third capacitor C3. The second resistor R2 prevents the RF signal from entering the second bias voltage source vb2; the source of the third NMOS transistor MN3 is grounded, and its drain is connected to the source of the fourth NMOS transistor MN4.

[0042] The first power supply VDD of the power supply and filtering circuit provides a DC bias to the gate of the fourth NMOS transistor MN4 through the fourth resistor R4. The sixth capacitor C6 is connected between the gate of the fourth NMOS transistor MN4 and the ground to filter out the gate RF noise. The fourth resistor R4 prevents the RF signal from entering the first power supply VDD. The drain of the fourth NMOS transistor MN4 is connected to the first power supply VDD through the second drain inductor Ld2, and is connected to one end of the fourth capacitor C4.

[0043] In this embodiment, the third NMOS transistor MN3 realizes the conversion of the gate input RF voltage signal into a drain current signal. The current signal passes through the fourth NMOS transistor MN4 and flows through the parallel load composed of the second drain inductor Ld2 and the subsequent circuit.

[0044] Preferably, see Figure 2 The gain slope reconstruction circuit includes a first adjustable capacitor CT1 and a first coupling inductor LT1 connected in parallel, and a second adjustable capacitor CT2 and a second coupling inductor LT2 connected in parallel; after the first adjustable capacitor CT1 and the first coupling inductor LT1 are connected in parallel, one end is grounded, and the other end is connected to the other end of the second capacitor C2; after the second adjustable capacitor CT2 and the second coupling inductor LT2 are connected in parallel, one end is grounded, and the other end is connected to one end of the third capacitor C3; the first coupling inductor LT1 and the second coupling inductor LT2 are coupled through an electromagnetic field, and the coupling coefficient is k.

[0045] Preferably, the power supply and filtering circuit includes a first power supply VDD, a seventh capacitor C7, and an eighth capacitor C8; after the seventh capacitor C7 and the eighth capacitor C8 are connected in parallel, one end is grounded and the other end is connected to the first power supply VDD to complete power supply filtering.

[0046] Preferably, see Figure 3 In the gain slope reconstruction circuit, the adjustable capacitor CT1 is composed of m switch capacitors in parallel, and the i-th switch capacitor is composed of capacitor CP With switch KP Series structure, where 1≤i≤m, i is a natural number; switch KP Closed, the adjustable capacitor CT1 increases CP ; Switch KP Disconnected, the adjustable capacitor CT1 reduces CP .

[0047] Accordingly, the adjustable capacitor CT2 is composed of n switch capacitors in parallel, and the jth switch capacitor is composed of capacitor CN <j>With switch KN <j>Series structure, where 1≤j≤n, j is a natural number; switch KN <j>Closed, the adjustable capacitor CT2 increases CN <j>; Switch KN <j>Disconnected, the adjustable capacitor CT2 reduces CN <j>.

[0048] Therefore, the gain slope reconstruction circuit can change the size of the adjustable capacitor CT1 and / or CT2 by opening or closing the switch, thereby changing the load impedance of the first-stage amplifier circuit and / or the source impedance of the second-stage amplifier circuit, changing the amplifier gain, and thus reconstructing the RF amplifier gain slope. Among them, the gain slope can be a negative slope, a positive slope, or a zero slope, and its slope reconstruction accuracy is controlled by the adjustment accuracy of the switch capacitor CT1 and / or CT2.

[0049] See also Figure 4 After superimposing the gain curve a1 of the first-stage amplifier circuit and the gain curve b1 of the second-stage amplifier circuit, within the frequency range of f1 to f2, the gain curve c1 of the gain slope reconfigurable RF amplifier has the optimal flatness (or 0 slope), and the gain curve c1 is the ideal gain curve of the gain slope reconfigurable RF amplifier in the design stage.

[0050] See also Figure 5 , increasing the adjustable capacitor CT1 and / or increasing the adjustable capacitor CT2 can adjust the gain slope. The gain curve of the reconfigurable RF amplifier has a positive slope in the frequency range of f1 to f2:

[0051] See also Figure 5 (a), increasing the adjustable capacitor CT1, due to the decrease in the resonant frequency, the gain curve a1 of the first-stage amplifier circuit moves to a1' toward the low frequency, and has little effect on the gain of the second-stage amplifier circuit. Here, it is assumed that the gain curve of the second-stage amplifier circuit remains unchanged and is still b1. The gain curves a1' and b1 are superimposed to form curve c2, that is, the gain slope of the reconfigurable RF amplifier decreases in the low-frequency gain within the frequency range of f1 to f2, and the gain curve presents a positive slope.

[0052] See also Figure 5 (b), increase the adjustable capacitor CT2. Due to the decrease in the resonant frequency, the gain curve b1 of the second-stage amplifier circuit moves to the low frequency to b1', which has little effect on the gain of the first-stage amplifier circuit. Here, it is assumed that the gain curve of the first-stage amplifier circuit remains unchanged at a1. The gain curves a1 and b1' are superimposed to form a curve c3, that is, the gain slope reconfigurable RF amplifier increases its high-frequency gain in the frequency range of f1 to f2, and the gain curve presents a positive slope.

[0053] See also Figure 6 , reducing the adjustable capacitor CT1 and / or reducing the adjustable capacitor CT2 can adjust the gain slope and the gain curve of the reconfigurable RF amplifier to a negative slope:

[0054] See also Figure 6 (a), reduce the adjustable capacitor CT1, due to the increase of the resonant frequency, the gain curve a1 of the first-stage amplifier circuit moves to the high frequency to a2', which has little effect on the gain of the second-stage amplifier circuit. Here, it is assumed that the gain curve of the second-stage amplifier circuit remains unchanged and is still b1. The gain curves a2' and b1 are superimposed to form a curve c4, that is, the gain slope reconfigurable RF amplifier has increased low-frequency gain in the frequency range of f1 to f2, and the gain curve presents a negative slope.

[0055] See also Figure 6 (b), reduce the adjustable capacitor CT2. Due to the increase of the resonant frequency, the gain curve b1 of the second-stage amplifier circuit moves to the high frequency to b2', which has little effect on the gain of the first-stage amplifier circuit. Here, it is assumed that the gain curve of the first-stage amplifier circuit remains unchanged at a1. The gain curves a1 and b2' are superimposed to form a curve c5, that is, the gain slope of the reconfigurable RF amplifier decreases in the high-frequency gain range of f1 to f2, and the gain curve presents a negative slope.

[0056] Example 2

[0057] This embodiment is based on embodiment 1:

[0058] See also Figure 7 This embodiment provides a radio frequency transceiver, including two single-pole double-throw switches SPDT for switching receiving and transmitting channels, a receiving channel, a transmitting channel and an antenna; wherein the receiving channel includes a low-noise amplifier, a phase control circuit, an amplitude control circuit and a gain slope reconfigurable radio frequency amplifier of embodiment 1, and the transmitting channel includes a phase control circuit, a gain slope reconfigurable radio frequency amplifier of embodiment 1, an amplitude control circuit and a power amplifier.

[0059] It should be noted that there is no restriction on the relative order of the gain slope reconfigurable RF amplifier, phase control circuit, and amplitude control circuit in the receiving channel, and there is no restriction on the relative order of the gain slope reconfigurable RF amplifier, phase control circuit, and amplitude control circuit in the transmitting channel. What is given in the embodiment is only an optional solution.

[0060] After the chip is manufactured, if the gain flatness of the receiving channel or transmitting channel deteriorates due to PVT fluctuations, the gain flatness of the transceiver channel can be optimized by configuring the gain slope reconfigurable RF amplifier and adjusting the gain slope, thereby shortening the chip development cycle and reducing chip development and testing costs.

[0061] It should also be noted that the gain slope reconfigurable RF amplifier can be used alone in a receiving channel or a transmitting channel, or can be used in combination with a power distribution or power synthesis circuit in a multi-receiving and / or multi-transmitting channel circuit to optimize the gain flatness of the receiving and / or transmitting channels.

[0062] Example 3

[0063] This embodiment is based on Embodiment 2:

[0064] This embodiment provides a communication system, including the radio frequency transceiver in Embodiment 2. In the communication system, by using a transceiver chip / circuit including a gain slope reconfigurable radio frequency amplifier, the gain flatness of the radio frequency link can be optimized, thereby shortening the system development cycle and reducing the system development and testing costs.

[0065] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art shall not deviate from the spirit and scope of the present invention, and shall be within the scope of protection of the claims attached to the present invention.< / j> < / j> < / j> < / j> < / j> < / j>

Claims

1. A gain slope reconfigurable radio frequency amplifier, characterized in that: It includes an input matching circuit, a first-stage amplifying circuit, a gain slope reconstruction circuit, a second-stage amplifying circuit, an output matching circuit, and a power supply and a filtering circuit, wherein the power supply and the filtering circuit are respectively connected to the first-stage amplifying circuit and the second-stage amplifying circuit, the input matching circuit, the first-stage amplifying circuit, the gain slope reconstruction circuit, the second-stage amplifying circuit, and the output matching circuit are sequentially connected in series, and a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor are sequentially arranged between the front and rear stages; The gain slope reconstruction circuit can change the output load impedance of the first-stage amplifier circuit and / or the source impedance of the second-stage amplifier circuit, thereby changing the gain of the first-stage amplifier circuit and / or the second-stage amplifier circuit, so that the gains of the first-stage amplifier circuit and the second-stage amplifier circuit are superimposed to present a reconfigurable gain slope.

2. The gain slope reconfigurable radio frequency amplifier according to claim 1, characterized in that: The gain slope reconstruction circuit includes a first adjustable capacitor, a second adjustable capacitor, a first coupled inductor and a second coupled inductor. After the first adjustable capacitor and the first coupled inductor are connected in parallel, one end is grounded and the other end is connected to the second capacitor; after the second adjustable capacitor and the second coupled inductor are connected in parallel, one end is grounded and the other end is connected to the third capacitor; the first coupled inductor and the second coupled inductor are coupled through an electromagnetic field, and the coupling coefficient is k.

3. The gain slope reconfigurable radio frequency amplifier according to claim 2, characterized in that: In the gain slope reconstruction circuit, the first adjustable capacitor includes m switching capacitors connected in parallel, and the second adjustable capacitor includes n switching capacitors connected in parallel; the size of the first adjustable capacitor and / or the second adjustable capacitor can be changed by opening or closing the switching capacitor, thereby changing the load impedance of the first-stage amplifier circuit and / or the source impedance of the second-stage amplifier circuit, that is, changing the gain of the RF amplifier, thereby reconstructing the gain slope of the RF amplifier.

4. The gain slope reconfigurable radio frequency amplifier according to claim 1, characterized in that: The first-stage amplifier circuit includes a first bias voltage source, a first NMOS transistor, a second NMOS transistor, a first source inductor, a first drain inductor, a fifth capacitor, a first resistor and a third resistor, wherein: The gate of the first NMOS transistor is connected to a first bias voltage source through a first resistor and is connected to a first capacitor, and the first resistor can prevent the radio frequency signal from entering the first bias voltage source; the source of the first NMOS transistor is grounded through a first source inductor or directly grounded, and the drain is connected to the source of the second NMOS transistor; The gate of the second NMOS transistor is connected to the power supply and the filter circuit through a third resistor and receives a DC bias voltage, and the third resistor can prevent the radio frequency signal from entering the power supply and the filter circuit; the fifth capacitor is connected between the gate of the second NMOS transistor and the ground to filter out the radio frequency noise of the gate of the second NMOS transistor; the drain of the second NMOS transistor is connected to the power supply and the filter circuit through the first drain inductor, and is connected to the second capacitor; The first NMOS transistor can realize the conversion of the gate input radio frequency voltage signal into a drain current signal. The current signal passes through the second NMOS transistor and flows through the parallel load composed of the first drain inductor and the subsequent circuit.

5. The gain slope reconfigurable radio frequency amplifier according to claim 1, characterized in that: The second-stage amplifier circuit includes a second bias voltage source, a third NMOS transistor, a fourth NMOS transistor, a second drain inductor, a sixth capacitor and a fourth resistor, wherein: The gate of the third NMOS transistor is connected to the second bias voltage source through a second resistor and is connected to a third capacitor, and the second resistor can prevent the radio frequency signal from entering the second bias voltage source; the source of the third NMOS transistor is grounded, and the drain is connected to the source of the fourth NMOS transistor; The gate of the fourth NMOS transistor is connected to the power supply and the filter circuit through a fourth resistor and receives a DC bias voltage, and the fourth resistor can prevent the radio frequency signal from entering the power supply and the filter circuit; the sixth capacitor is connected between the gate of the fourth NMOS transistor and the ground to filter the gate radio frequency noise; the drain of the fourth NMOS transistor is connected to the power supply and the filter circuit through the second drain inductor, and is connected to the fourth capacitor; The third NMOS transistor can realize the conversion of the gate input radio frequency voltage signal into a drain current signal. The current signal passes through the fourth NMOS transistor and flows through the parallel load composed of the second drain inductor and the subsequent circuit.

6. The gain slope reconfigurable radio frequency amplifier according to claim 1, characterized in that: The power supply and filtering circuit includes a first power supply, a seventh capacitor and an eighth capacitor. After the seventh capacitor and the eighth capacitor are connected in parallel, one end is grounded and the other end is connected to the first power supply to complete power supply filtering.

7. The gain slope reconfigurable radio frequency amplifier according to claim 1, characterized in that: One end of the input matching circuit is connected to the radio frequency input, and the other end is connected to the first capacitor, so as to achieve impedance matching between the radio frequency input source impedance and the input end of the first stage amplification circuit.

8. The gain slope reconfigurable radio frequency amplifier according to claim 1, characterized in that: One end of the output matching circuit is connected to the fourth capacitor, and the other end is connected to the input end of the subsequent circuit, so as to achieve impedance matching between the output end of the second stage amplifying circuit and the subsequent circuit.

9. A radio frequency transceiver, characterized in that: A gain slope reconfigurable radio frequency amplifier comprising any one of claims 1-8.

10. A communication device, characterized in that: Includes the radio frequency transceiver as claimed in claim 9.

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