Multi-transmission-zero-point on-chip band-pass filter using cross mutual winding transformer

Abstract

The invention discloses a multi-transmission-zero-point on-chip band-pass filter using a cross mutual winding transformer, and aims to solve the technical problems of high frequency selectivity and out-of-band rejection of an existing on-chip band-pass filter. A cross-wound transformer in the on-chip band-pass filter is located between a first port and a second port, the cross-wound transformer is composed of a pair of cross-wound spiral inductors, one center tap of the cross-wound transformer is connected with a first capacitor and a second capacitor, and the other center tap of the cross-wound transformer is connected with a second capacitor. The other center tap of the cross mutual winding transformer is connected with a third capacitor and a fourth capacitor; the first spiral inductor and the second spiral inductor which are parallel are located on the left side of the cross-winding transformer, and the fourth spiral inductor and the fifth spiral inductor which are parallel are located on the right side of the cross-winding transformer. Coupling capacitance is generated through electric coupling in the cross mutual winding transformer, the transmission zero point of the filter is increased under the condition that no extra circuit element is added, miniaturization is achieved, and the out-of-band rejection performance is enhanced.

Description

Technical Field

[0001] The present invention relates to a multi-transmission zero miniaturized on-chip bandpass filter using a cross-interwound transformer. Background Art

[0002] With the rapid development of modern wireless communication technology, RF front-end modules are constantly moving towards high integration. This trend has led to a rapid increase in demand for integrated on-chip components, especially on-chip bandpass filters. As the core component for signal frequency selection in the transceiver system, the miniaturization and high performance requirements of such filters are becoming more and more significant. In order to achieve a more compact system design and improve overall performance, the miniaturization and high selectivity of on-chip bandpass filters have become key goals in research and development. At present, on-chip bandpass filters have been realized through a variety of manufacturing processes, including complementary metal oxide semiconductors, silicon germanium, gallium arsenide, glass and high-resistance silicon technologies. These processes have their own advantages, but their high manufacturing costs limit the development of on-chip bandpass filters. In addition, due to the limited area and high integration of the on-chip system, the filter needs to achieve better frequency selectivity and signal processing capabilities in a limited space, which further increases the difficulty and challenge of design. To address this problem, many studies have introduced innovative miniaturization solutions. For example, the size of the bandpass filter is reduced by stacking inductors, three-dimensional inductors, slow-wave structures and coplanar waveguides. Stacked inductor and three-dimensional inductor designs utilize multi-layer structures, which can more effectively utilize chip area in vertical space, but require multi-layer processing structures, which not only increases the complexity of the manufacturing process, but also increases production costs. Slow-wave structures and coplanar waveguides perform well in the millimeter wave band and are suitable for high-frequency on-chip applications, but in mid-frequency band applications, the larger chip footprint is still a bottleneck. Therefore, how to design a bandpass filter that meets miniaturization requirements in the limited space on the chip has become a core issue in technology development.

[0003] In addition to the need for miniaturization, on-chip bandpass filters also face challenges in frequency selectivity and out-of-band suppression performance. Frequency selectivity and out-of-band suppression performance mainly depend on the number of transmission zeros of the filter. In order to enhance frequency selectivity and suppress out-of-band interference signals, on-chip bandpass filters usually need to have multiple transmission zeros. However, traditional methods usually achieve multiple transmission zeros by introducing additional transmission paths, increasing coupling paths, adding resonators, or cascading low-pass and band-stop elements. Although these methods have improved the performance of the filter to a certain extent, they have inevitably brought new problems, including the complexity of the circuit structure and the further increase of the chip area. Therefore, how to achieve more transmission zeros without increasing the complexity of the circuit and the chip area has become another major challenge in the current design of on-chip bandpass filters. In summary, the design of on-chip bandpass filters faces multiple requirements of miniaturization, high frequency selectivity and out-of-band suppression, while being constrained by cost, process complexity and chip area limitations. How to balance these competing requirements and develop new on-chip bandpass filter designs has become a research focus in this field. Summary of the invention

[0004] The purpose of the present invention is to solve the technical problems of miniaturization, high frequency selectivity and out-of-band suppression of existing on-chip bandpass filters, and to provide a multi-transmission zero on-chip bandpass filter using cross-interwinding transformers.

[0005] The multi-transmission zero-point on-chip bandpass filter using a cross-interwinding transformer of the present invention comprises a port one, a port two, a first spiral inductor L1, a second spiral inductor L2, a fourth spiral inductor L4, a fifth spiral inductor L5, a cross-interwinding transformer L3, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4, wherein the port one is composed of a first port feeder G1-1, a second port feeder S1 and a third port feeder G1-2 arranged in parallel and spaced apart, the second port feeder S1 is located between the first port feeder G1-1 and the third port feeder G1-2, the port two is composed of a first port feeder G2-1, a second port feeder S2 and a third port feeder G2-2 arranged in parallel and spaced apart, the second port feeder S2 is located between the first port feeder G2-1 and the third port feeder G2-2;

[0006] The cross-interwinding transformer L3 is located between the first port and the second port. The cross-interwinding transformer L3 is composed of a pair of cross-interwinding spiral inductors. A center tap of the cross-interwinding transformer L3 is connected to the first capacitor C1 and the second capacitor C2, and another center tap of the cross-interwinding transformer L3 is connected to the third capacitor C3 and the fourth capacitor C4. The parallel first spiral inductor L1 and the second spiral inductor L2 are located on the left side of the cross-interwinding transformer L3, and the parallel fourth spiral inductor L4 and the fifth spiral inductor L5 are located on the right side of the cross-interwinding transformer L3.

[0007] One end of the first microstrip line M1 is connected to the second port feeder S1, the other end of the first microstrip line M1 is respectively connected to the center taps of the first spiral inductor L1 and the second spiral inductor L2, the first spiral inductor L1 is connected to the outer microstrip line of a cross-wound spiral inductor in the cross-wound transformer L3, the second spiral inductor L2 is connected to the first capacitor C1 via the second microstrip line M2, one end of the fourth microstrip line M4 is connected to the third port feeder G1-2, and the other end of the fourth microstrip line M4 is connected to the third capacitor C3;

[0008] One end of the sixth microstrip line M6 is connected to the No. 2 port feeder S2, the other end of the sixth microstrip line M6 is respectively connected to the center taps of the fourth spiral inductor L4 and the fifth spiral inductor L5, the fifth spiral inductor L5 is connected to the outer microstrip line of another spiral inductor cross-wound in the cross-wound transformer L3, the fourth spiral inductor L4 is connected to the fourth capacitor C4 via the fifth microstrip line M5, one end of the third microstrip line M3 is connected to the No. 1 port feeder G2-1, and the other end of the third microstrip line M3 is connected to the second capacitor C2;

[0009] The first capacitor C1 and the second capacitor C2 are connected via the lower plate metal layer, and the third capacitor C3 and the fourth capacitor C4 are connected via the lower plate metal layer.

[0010] The present invention is based on the proposed miniaturized bandpass filter circuit using multiple transmission zeros on a cross-interwinding transformer chip, which utilizes the coupling capacitance generated by electrical coupling in the cross-interwinding transformer to increase the transmission zeros of the filter without adding additional circuit elements (capacitors, inductors), thereby miniaturizing the filter and enhancing the out-of-band suppression performance. According to the given filter design requirements (bandwidth, in-band ripple height RL, out-of-band ripple height SR), the circuit parameters that meet the design requirements are calculated, and a miniaturized bandpass filter with multiple transmission zeros can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A circuit schematic diagram of a multi-transmission zero on-chip bandpass filter using a cross-interwound transformer in an embodiment;

[0012] Figure 2 Schematic diagram of an odd-even mode equivalent circuit of a multi-transmission zero on-chip bandpass filter using a cross-interwinding transformer in an embodiment;

[0013] Figure 3 Schematic diagram of circuit S parameters of a multi-transmission zero on-chip bandpass filter using a cross-interwinding transformer in an embodiment;

[0014] Figure 4The circuit simulation results of the multi-transmission zero on-chip bandpass filter using the cross-interwinding transformer in the embodiment meet different design requirements when L1=0.35nH is selected: (a) RL=SR=20dB, FBW=20%; (b) RL=15dB, SR=20dB, FBW=20%; (c) RL=20dB, SR=25dB, FBW=20%; (d) RL=20dB, SR=20dB, FBW=30%;

[0015] Figure 5 The curve diagram (a) of the circuit parameters C1, C2, L2, L3 and M when the value of L1 is changed when RL=SR=20dB and FBW=20% in the embodiment, and the circuit parameters k and C c The curve graph of the corresponding changes (b);

[0016] Figure 6 In the embodiment, when RL=SR=20dB, FBW=20%, when L1=0.3nH, the circuit S parameter result is shown in Figure (a), and when L1=0.4nH, the circuit S parameter result is shown in Figure (b);

[0017] Figure 7 A microwave planar circuit diagram of a multi-transmission zero on-chip bandpass filter using a cross-interwinding transformer in an embodiment;

[0018] Figure 8 3D layout of a multi-transmission zero on-chip bandpass filter using a cross-interwound transformer in an embodiment;

[0019] Fig. 9 A physical diagram of a multi-transmission zero on-chip bandpass filter using a cross-interwound transformer in an embodiment;

[0020] Fig.10 Graph showing simulation and measured results of a multi-transmission zero on-chip bandpass filter using a cross-interwinding transformer in an embodiment. DETAILED DESCRIPTION

[0021] Specific implementation method one: In this implementation method, a multi-transmission zero on-chip bandpass filter using a cross-interwinding transformer includes port one, port two, a first spiral inductor L1, a second spiral inductor L2, a fourth spiral inductor L4, a fifth spiral inductor L5, a cross-interwinding transformer L3, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4. Port one is composed of a first port feeder G1-1, a second port feeder S1 and a third port feeder G1-2 arranged in parallel and spaced apart, and the second port feeder S1 is located between the first port feeder G1-1 and the third port feeder G1-2. Port two is composed of a first port feeder G2-1, a second port feeder S2 and a third port feeder G2-2 arranged in parallel and spaced apart, and the second port feeder S2 is located between the first port feeder G2-1 and the third port feeder G2-2.

[0022] The cross-interwinding transformer L3 is located between the first port and the second port. The cross-interwinding transformer L3 is composed of a pair of cross-interwinding spiral inductors. A center tap of the cross-interwinding transformer L3 is connected to the first capacitor C1 and the second capacitor C2, and another center tap of the cross-interwinding transformer L3 is connected to the third capacitor C3 and the fourth capacitor C4. The parallel first spiral inductor L1 and the second spiral inductor L2 are located on the left side of the cross-interwinding transformer L3, and the parallel fourth spiral inductor L4 and the fifth spiral inductor L5 are located on the right side of the cross-interwinding transformer L3.

[0023] One end of the first microstrip line M1 is connected to the second port feeder S1, the other end of the first microstrip line M1 is respectively connected to the center taps of the first spiral inductor L1 and the second spiral inductor L2, the first spiral inductor L1 is connected to the outer microstrip line of a cross-wound spiral inductor in the cross-wound transformer L3, the second spiral inductor L2 is connected to the first capacitor C1 via the second microstrip line M2, one end of the fourth microstrip line M4 is connected to the third port feeder G1-2, and the other end of the fourth microstrip line M4 is connected to the third capacitor C3;

[0024] One end of the sixth microstrip line M6 is connected to the No. 2 port feeder S2, the other end of the sixth microstrip line M6 is respectively connected to the center taps of the fourth spiral inductor L4 and the fifth spiral inductor L5, the fifth spiral inductor L5 is connected to the outer microstrip line of another spiral inductor cross-wound in the cross-wound transformer L3, the fourth spiral inductor L4 is connected to the fourth capacitor C4 via the fifth microstrip line M5, one end of the third microstrip line M3 is connected to the No. 1 port feeder G2-1, and the other end of the third microstrip line M3 is connected to the second capacitor C2;

[0025] The first capacitor C1 and the second capacitor C2 are connected via the lower plate metal layer, and the third capacitor C3 and the fourth capacitor C4 are connected via the lower plate metal layer.

[0026] This embodiment proposes a new type of miniaturized on-chip bandpass filter using a cross-interwinding transformer. The on-chip bandpass filter uses the coupling capacitance generated by the electrical coupling in the cross-interwinding transformer to generate multiple transmission zeros without adding additional circuit elements such as capacitors and inductors, thereby achieving miniaturization while significantly improving frequency selectivity and out-of-band suppression performance. In addition, the design does not require the use of three-dimensional inductors, so that the filter can adapt to a variety of manufacturing process requirements, and by controlling additional circuit degrees of freedom, the out-of-band suppression range can be flexibly adjusted according to the design requirements of specific applications.

[0027] Specific implementation method 2: The difference between this implementation method and specific implementation method 1 is that the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are all MIM capacitors.

[0028] Specific implementation method three: This implementation method is different from specific implementation methods one or two in that the spacing between the second port feeder S1 and the first port feeder G1 - 1 and the third port feeder G1 - 2 is 50-60 μm respectively.

[0029] Specific implementation mode 4: This implementation mode is different from any one of specific implementation modes 1 to 3 in that a grounding through hole Via is respectively provided on the first port feeder line G1 - 1 and the third port feeder line G1 - 2 .

[0030] Specific implementation mode 5: This implementation mode is different from specific implementation modes 1 to 4 in that a grounding through hole Via is respectively provided on the first port feeder G2 - 1 and the third port feeder G2 - 2 .

[0031] Specific embodiment 6: This embodiment is different from any one of specific embodiments 1 to 5 in that the other end of the first microstrip line M1 is connected to the center taps of the first spiral inductor L1 and the second spiral inductor L2 respectively through the bottom plate metal layer.

[0032] Specific embodiment 7: This embodiment is different from any one of specific embodiments 1 to 6 in that the spacing between the cross-winding spiral inductors in the cross-winding transformer L3 is 10 μm.

[0033] Specific embodiment eight: This embodiment is different from any one of specific embodiments one to seven in that the pitch of the spiral microstrip lines of the first spiral inductor L1 , the second spiral inductor L2 , the fourth spiral inductor L4 and the fifth spiral inductor L5 are all 10 μm.

[0034] Specific embodiment nine: This embodiment differs from any one of specific embodiments one to eight in that a center tap of the cross-interwinding transformer L3 is connected to the first capacitor C1 and the second capacitor C2 through the lower plate metal layer, and another center tap of the cross-interwinding transformer L3 is connected to the third capacitor C3 and the fourth capacitor C4 through the lower plate metal layer.

[0035] Specific implementation example ten: This implementation example is different from any one of specific implementation examples one to nine in that the microwave circuit of the multi-transmission zero on-chip bandpass filter using the cross-interwinding transformer has a centrally symmetrical structure.

[0036] Embodiment: In this embodiment, a multi-transmission zero on-chip bandpass filter using a cross-interwinding transformer includes port one, port two, a first spiral inductor L1, a second spiral inductor L2, a fourth spiral inductor L4, a fifth spiral inductor L5, a cross-interwinding transformer L3, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4. Port one is composed of a first port feeder G1-1, a second port feeder S1 and a third port feeder G1-2 arranged in parallel and spaced apart, the second port feeder S1 is located between the first port feeder G1-1 and the third port feeder G1-2, and the spacing between the second port feeder S1 and the first port feeder G1-1 and the third port feeder G1-2 is 54 μm. Port two is composed of a first port feeder G2-1, a second port feeder S2 and a third port feeder G2-2 arranged in parallel and spaced apart, and the second port feeder S2 is located between the first port feeder G2-1 and the third port feeder G2-2;

[0037] The cross-interwinding transformer L3 is located between the first port and the second port. The cross-interwinding transformer L3 is composed of a pair of cross-interwinding spiral inductors. The spacing between the cross-interwinding spiral microstrip lines is 10 μm. The inner circle radius of the cross-interwinding transformer L3 is 45 μm, and the outer circle radius is 135 μm. A center tap of the cross-interwinding transformer L3 is connected to the first capacitor C1 and the second capacitor C2, and another center tap of the cross-interwinding transformer L3 is connected to the third capacitor C3 and the fourth capacitor C4; the parallel first spiral inductor L1 and the second spiral inductor L2 are located on the left side of the cross-interwinding transformer L3, and the parallel fourth spiral inductor L4 and the fifth spiral inductor L5 are located on the right side of the cross-interwinding transformer L3. The inner circle radii of the first spiral inductor L1, the second spiral inductor L2, the fourth spiral inductor L4, and the fifth spiral inductor L5 are all 37.5 μm, and the spacing between the spiral microstrip lines is all 10 μm.

[0038] One end of the first microstrip line M1 is connected to the second port feeder S1, the other end of the first microstrip line M1 is respectively connected to the center taps of the first spiral inductor L1 and the second spiral inductor L2, the first spiral inductor L1 is connected to the outer microstrip line of a cross-wound spiral inductor in the cross-wound transformer L3, the second spiral inductor L2 is connected to the first capacitor C1 via the second microstrip line M2, one end of the fourth microstrip line M4 is connected to the third port feeder G1-2, and the other end of the fourth microstrip line M4 is connected to the third capacitor C3;

[0039] One end of the sixth microstrip line M6 is connected to the No. 2 port feeder S2, the other end of the sixth microstrip line M6 is respectively connected to the center taps of the fourth spiral inductor L4 and the fifth spiral inductor L5, the fifth spiral inductor L5 is connected to the outer microstrip line of another spiral inductor cross-wound in the cross-wound transformer L3, the fourth spiral inductor L4 is connected to the fourth capacitor C4 via the fifth microstrip line M5, one end of the third microstrip line M3 is connected to the No. 1 port feeder G2-1, and the other end of the third microstrip line M3 is connected to the second capacitor C2;

[0040] The first capacitor C1 and the second capacitor C2 are connected via the lower plate metal layer, and the third capacitor C3 and the fourth capacitor C4 are connected via the lower plate metal layer.

[0041] The circuit topology diagram of the multi-transmission zero on-chip bandpass filter using the cross-interwinding transformer in this embodiment is as follows: Figure 1 As shown. It includes port 1, port 2, inductors (L1, L2, L3), capacitors (C1, C2, C3, C c ). Port 1 is connected to one end of inductors L1 and L2, the other end of L2 is connected to C1, the other end of C1 is connected to C2 and L3, the other end of C2 is grounded, and the other end of L3 is connected to the end of L1 that is not connected to the port. L1, L3, C1, and L2 form a ring loop, and the circuit is mirror-symmetrical on the left and right. There is mutual inductance between the two inductors L3, and the mutual inductance coefficient is M. The left and right ring loops are connected through the coupling capacitor C at both ends of L3. c to connect.

[0042] Since the circuit is a symmetrical structure, the S parameters of the circuit can be solved by performing odd-even mode analysis on the circuit. The equivalent circuit diagram of the odd-even mode of the circuit is as follows: Figure 2 As shown. By analyzing the voltage and current of the even-mode circuit, the input impedance Z of the even-mode circuit is calculated. ine And the input impedance Z of the odd-mode circuit ino for:

[0043] Z ine =Z e1 Z e2 / (Z e1 +Z e2 )+Z e3

[0044]

[0045] in

[0046] s=jω,Z e1 =sL2+1 / (sC1),Z e2 =s(L1+L3+M),Z e3 =1 / (sC2),Zo1 =Z e1 ,Z o2 =1 / (s(C2+2C c ),

[0047] Z o3 =sL1,Z o4 =1 / (2sC c ),Z o5 =s(L3-M),

[0048] A1=Z o1 +Z o2 ,A2=Z o3 +Z o4 ,A3=Z o1 +Z o3 ,A4=Z o2 +Z o4 .

[0049] Then, the expression of the S parameter of the circuit can be derived as follows:

[0050]

[0051] S 21 =(Z0(Z ine -Z ino )) / ((Z ine +Z0)(Z ino +Z0))

[0052] The S parameter diagram of the circuit is shown in Figure 3 As shown, where f TZm and f RZn are the frequencies of the mth transmission zero and the nth reflection zero (m=1,2,3,4; n=1,2), f TDi and f RD S 11 and S 21 The derivative of is zero (i=1,2,3), RL is the return loss, and SR is the out-of-band suppression. It can be seen that the proposed circuit has two in-band reflection zeros and four out-of-band reflection zeros, where TZ1, TZ3, and TZ4 are coupling capacitors C c produce.

[0053] In order to achieve equal ripple height out of band and control SR, the following constraint equation needs to be satisfied:

[0054]

[0055] where ω TZm and ω TDi They are f TZm and f TDiangular frequency.

[0056] In order to control the bandwidth and in-band height RL, the following constraint equations need to be satisfied:

[0057]

[0058] where ω RZn ,ω RD , and ω cj They are f RZn 、f RD , and f cj angular frequency.

[0059] When the design requirements of the filter (bandwidth, in-band ripple height RL, out-band ripple height SR) are determined, 6 design equations need to be satisfied. The circuit has a total of 7 design parameters (L1, L2, L3, C1, C2, C c ,M). Since the circuit design variables are greater than the design equation, that is, the circuit has an extra degree of freedom, there are countless circuit solutions that meet the design requirements. When a circuit design parameter is given, there is only one set of circuit solutions that meet the determined design requirements.

[0060] For example, when L1=0.35nH is selected, by determining the design requirements of the filter (RL=SR=20dB, FBW=20%; RL=15dB, SR=20dB, FBW=20%; RL=20dB, SR=25dB, FBW=20%; RL=20dB, SR=20dB, FBW=30%), a unique set of solutions that meet the requirements can be found.

[0061] Filter design parameters that meet RL=20dB, SR=20dB, FBW=20%:

[0062] L1=0.35nH, L2=0.39nH, L3=0.48nH, C1=0.72pF, C2=0.79pF, M=0.30nH, C c =68fF.

[0063] Filter design parameters that meet RL=15dB, SR=20dB, FBW=20%:

[0064] L1=0.35nH, L2=0.33nH, L3=0.31nH, C1=0.92pF, C2=0.74pF, M=0.21nH, C c =59fF.

[0065] Filter design parameters that meet RL=20dB, SR=20dB, FBW=30%:

[0066] L1=0.35nH, L2=0.42nH, L3=0.74nH, C1=0.56pF, C2=0.84pF, M=0.51nH, C c =82fF.

[0067] According to the solved circuit parameters, the circuit simulation results are as follows Figure 4 shown.

[0068] When the filter design requirements are kept unchanged at RL = SR = 20dB, FBW = 20%, by changing the value of L1, the curves of other circuit parameters changing accordingly are as follows: Figure 5 As shown in Figure 2, k is the coupling coefficient between L3, k = M / L3.

[0069] When the design requirements of the filter are kept unchanged as RL=SR=20dB,FBW=20%, by changing the value of L1, the circuit S parameter curve is as follows Figure 6 It can be found that when the design requirements of the filter remain unchanged, by determining the value of L3 from 0.3nH to 0.4nH, the high-frequency 20dB out-of-band suppression range can be extended from 31GHz to 43GHz.

[0070] like Figure 7 and Figure 8 As shown, the present invention provides a 3D layout of an on-chip multi-transmission zero-point bandpass filter using a cross-interwinding transformer, and the 3D layout includes: port one, port two, spiral inductors L1 and L2, cross-interwinding transformer L3, and MIM capacitors C1 and C2.

[0071] like Figure 7 and Figure 8 As shown, the design process of an on-chip multi-transmission zero bandpass filter using a cross-interwound transformer includes the following steps:

[0072] 1. Determine the filter design indicators (bandwidth FBW, in-band ripple height RL, out-band ripple height SR), for example, RL = 20dB, SR = 20dB, FBW = 20%, and the center frequency is 5GHz.

[0073] 2. Determine a circuit's redundant degrees of freedom, for example, determine L1 to be 0.37nH, and calculate other circuit parameters according to the following constraint equations:

[0074]

[0075] The other parameters of the circuit are: L2 = 0.37nH, L3 = 0.46nH, C1 = 0.73pF, C2 = 0.77pF, M = 0.30nH, C c =67fF.

[0076] 4. According to the calculated theoretical parameter values, the capacitors and inductors are simulated respectively. Inductors L1 and L2 are implemented by spiral inductors, C1 and C2 are implemented by MIM capacitors, and the cross-interwinding transformer structure is implemented by a pair of cross-interwinding spiral inductors L3. The circuit components are arranged according to Figure 7 The connections shown are drawn into a layout. Among them, G1, S1, and G1 constitute port one, G2, S2, and G2 constitute port two, Via is a grounding via, and the signal of port one is fed into the circuit via microstrip line M1, M1 is connected to the center taps of inductors L1 and L2; inductor L1 is connected to L3, and the center tap of L3 is connected to capacitors C1 and C2; inductor L2 is connected to capacitor C1 via microstrip line M2, capacitor C1 is connected to capacitor C2, and capacitor C2 is connected to G2 via microstrip line M3 to achieve grounding. The overall circuit has a central symmetrical structure.

[0077] 5. Perform electromagnetic simulation on the entire circuit and fine-tune the size of capacitors and inductors to ensure that the simulation results meet the design requirements.

[0078] 6. Carry out tape-out production of the designed circuit, as shown in the actual picture Fig. 9 The simulation and test results are shown in Fig.10 shown.

Claims

1. A multi-transmission zero on-chip bandpass filter using a cross-interwound transformer, characterized in that The multi-transmission zero on-chip bandpass filter comprises port one, port two, a first spiral inductor L1, a second spiral inductor L2, a fourth spiral inductor L4, a fifth spiral inductor L5, a cross-interwinding transformer L3, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4, port one is composed of a first port feeder G1-1, a second port feeder S1 and a third port feeder G1-2 arranged in parallel and spaced apart, the second port feeder S1 is located between the first port feeder G1-1 and the third port feeder G1-2, port two is composed of a first port feeder G2-1, a second port feeder S2 and a third port feeder G2-2 arranged in parallel and spaced apart, the second port feeder S2 is located between the first port feeder G2-1 and the third port feeder G2-2; The cross-interwinding transformer L3 is located between the first port and the second port. The cross-interwinding transformer L3 is composed of a pair of cross-interwinding spiral inductors. A center tap of the cross-interwinding transformer L3 is connected to the first capacitor C1 and the second capacitor C2, and another center tap of the cross-interwinding transformer L3 is connected to the third capacitor C3 and the fourth capacitor C4. The parallel first spiral inductor L1 and the second spiral inductor L2 are located on the left side of the cross-interwinding transformer L3, and the parallel fourth spiral inductor L4 and the fifth spiral inductor L5 are located on the right side of the cross-interwinding transformer L3. One end of the first microstrip line M1 is connected to the second port feeder S1, the other end of the first microstrip line M1 is respectively connected to the center taps of the first spiral inductor L1 and the second spiral inductor L2, the first spiral inductor L1 is connected to the outer microstrip line of a cross-wound spiral inductor in the cross-wound transformer L3, the second spiral inductor L2 is connected to the first capacitor C1 via the second microstrip line M2, one end of the fourth microstrip line M4 is connected to the third port feeder G1-2, and the other end of the fourth microstrip line M4 is connected to the third capacitor C3; One end of the sixth microstrip line M6 is connected to the No. 2 port feeder S2, the other end of the sixth microstrip line M6 is respectively connected to the center taps of the fourth spiral inductor L4 and the fifth spiral inductor L5, the fifth spiral inductor L5 is connected to the outer microstrip line of another spiral inductor cross-wound in the cross-wound transformer L3, the fourth spiral inductor L4 is connected to the fourth capacitor C4 via the fifth microstrip line M5, one end of the third microstrip line M3 is connected to the No. 1 port feeder G2-1, and the other end of the third microstrip line M3 is connected to the second capacitor C2; The first capacitor C1 and the second capacitor C2 are connected via the lower plate metal layer, and the third capacitor C3 and the fourth capacitor C4 are connected via the lower plate metal layer.

2. The multi-transmission zero on-chip bandpass filter using a cross-interwound transformer according to claim 1, characterized in that The first capacitor C1 , the second capacitor C2 , the third capacitor C3 and the fourth capacitor C4 are all MIM capacitors.

3. The multi-transmission zero on-chip bandpass filter using a cross-interwound transformer according to claim 1, characterized in that The spacing between the second port feed line S1 and the first port feed line G1 - 1 and the third port feed line G1 - 2 is 50-60 μm respectively.

4. The multi-transmission zero on-chip bandpass filter using a cross-interwound transformer according to claim 1, characterized in that A grounding via Via is respectively formed on the first port feeder G1 - 1 and the third port feeder G1 - 2 .

5. The multi-transmission zero on-chip bandpass filter using a cross-interwound transformer according to claim 1, characterized in that The first port feeder G2 - 1 and the third port feeder G2 - 2 are respectively provided with grounding vias Via.

6. The multi-transmission zero on-chip bandpass filter using a cross-interwound transformer according to claim 1, characterized in that The other end of the first microstrip line M1 is connected to the center taps of the first spiral inductor L1 and the second spiral inductor L2 respectively through the bottom plate metal layer.

7. The multi-transmission zero on-chip bandpass filter using a cross-interwound transformer according to claim 1, characterized in that The pitch of the cross-interwinding spiral inductor in the cross-interwinding transformer L3 is 10 μm.

8. The multi-transmission zero on-chip bandpass filter using a cross-interwound transformer according to claim 1, characterized in that The pitches of the spiral microstrip lines of the first spiral inductor L1 , the second spiral inductor L2 , the fourth spiral inductor L4 and the fifth spiral inductor L5 are all 10 μm.

9. The multi-transmission zero on-chip bandpass filter using cross-interwound transformers according to claim 1, characterized in that A center tap of the cross-interwinding transformer L3 is connected to the first capacitor C1 and the second capacitor C2 through the lower plate metal layer, and another center tap of the cross-interwinding transformer L3 is connected to the third capacitor C3 and the fourth capacitor C4 through the lower plate metal layer.

10. The multi-transmission zero on-chip bandpass filter using cross-interwound transformers according to claim 1, characterized in that The microwave circuit of the multi-transmission zero-point on-chip bandpass filter using the cross-interwinding transformer has a central symmetrical structure.

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