A digital filter structure for sigma-delta ADC down-sampling

Abstract

The application discloses a kind of digital filter structures for Σ-ΔADC downsampling, adopt full digital method to construct three-order single loop feedforward system, series integrated integral-comb cascaded filter, compensation filter and half-band filter.Integral-comb cascaded filter is composed of multistage integrator series recursion structure, support downsampling multiple programmable, improve parallelism and hardware utilization by moving delay unit position in advance.Compensation filter adopts odd-order integrator multi-branch parallel, reduce resource occupation, significantly improve processing speed;Half-band filter uses retiming technology to adjust coefficient position, reduce critical path delay, improve the highest frequency of system, while reducing the amount of calculation through symmetric structure and multiplexing extraction path, front extraction reduces the demand of operation rate and data loss.The application realizes low power consumption, low hardware consumption and high design flexibility of downsampling filter in Σ-ΔADC digital module.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, and specifically discloses a digital filter structure for downsampling of Σ-ΔADC. Background Technology

[0002] With the rapid development of semiconductor manufacturing processes, digital circuits have become a powerful engine for data processing. As a crucial pathway for the interaction between analog and digital information, the analog-to-digital converter (ADC) has become a vital component. Among the many types of ADCs, the Σ-Δ ADC, with its extremely high acquisition rate, shaping technology, and insensitivity to process matching, has become the best choice for achieving high resolution. Σ-Δ ADCs have a natural advantage in low-frequency, high-resolution fields such as medical electronics and audio. In pursuit of high resolution, analog design engineers have focused heavily on optimizing and innovating the structure of the analog modulator, neglecting the subsequent digital circuitry. The digital portion of a Σ-Δ ADC largely determines the chip's power consumption and hardware overhead; therefore, designing digital modules with low power consumption, small area, and high flexibility is essential.

[0003] The development of downsampling filters was initially not synchronized with modulators. It wasn't until the introduction of Σ-ΔADC technology that downsampling filters emerged to complement Σ-ΔADCs. The earliest example was proposed by Croisier in 1973, based on distributed multiply-accumulate coding. This method, complementing the FPGA technology introduced at the same time, became a popular approach in filter design. Later, Hogenauer proposed a high-speed downsampling structure using an integrator-comb (CIC) filter, which remains influential today. BrandtBP, building upon this distributed approach, optimized the structure and area through hardware multiplexing within the FPGA.

[0004] The downsampling filter implementation scheme described above is not suitable for low-power, low-area, and highly flexible Σ-Δ ADCs. There are two possible implementation approaches: one is to use a single FIR filter, and the other is to cascade multiple filters. However, designing a low-order low-pass FIR filter with a high density factor, flat passband, and high stopband attenuation using the equiripple method in FilterDesigner requires tens of thousands of orders, which necessitates a large number of multiply-accumulate operations, resulting in a significant overhead in terms of performance, area, and power consumption. Therefore, the cascaded multi-stage FIR filter approach is more suitable for the downsampling filter module in high-performance Σ-Δ ADCs.

[0005] In signal rate conversion systems, integrator-comb cascaded filters are the most widely used. They possess low-pass and high-impedance properties, and all their coefficients are integers, eliminating the need for quantization processing and ROM usage during hardware implementation. Furthermore, the special nature of the coefficients reduces the number of shift and multiplication operations, with the final overhead determined solely by the number of additions. The regular structure of the integrator-comb cascaded filter allows for adjustments to the decimation factor to suit different system requirements, providing inherent programmability. However, when used as a low-pass filter, the passband is not flat, and the high-impedance characteristics are affected by the number of cascades, necessitating the addition of a compensation filter. This compensation filter can also perform a decimation operation simultaneously. Finally, to achieve a flatter passband and stopband, another filter stage is required for control. Half-band filters have a unique spectrum, resulting in half the coefficients of typical structures. They require less overhead for the same specifications, and their passband and stopband are flat, with easily controllable transition bands. Therefore, half-band filters are often used as the final stage, performing a 2x downsampling, which also reduces the pressure on the compensation filter's stopband attenuation. Therefore, multi-stage cascaded forms of integrator-comb filters, compensation filters, and half-band filters will have excellent overall performance and are more suitable for use in low-power, low-area, and highly flexible digital modules for Σ-Δ ADCs. Summary of the Invention

[0006] The purpose of this invention is to provide a digital filter structure for Σ-Δ ADC downsampling, thereby overcoming the shortcomings of existing downsampling filter structures, such as high power consumption, large area, complex structure, low flexibility, and the need for additional compensation circuitry. To achieve the above objective, this invention adopts the following technical solution:

[0007] The digital filter structure for Σ-Δ ADC downsampling includes:

[0008] Integral-comb cascaded filters, compensated filters, and half-band filters; among them,

[0009] The input terminal of the integral-comb cascade filter is connected to the signal input terminal, which is used to input the output signal of the Σ-ΔADC modulator.

[0010] The output of the integral-comb cascade filter is connected to the input of the compensation filter;

[0011] The output of the compensation filter is connected to the input of the half-band filter.

[0012] The output terminal of the half-band filter outputs the filtered signal.

[0013] The integrator-comb cascaded filter includes:

[0014] First integrator, second integrator, third integrator, ..., (N-1)th integrator, Nth integrator, first filter, second filter, third filter, ..., (N-1)th filter, Nth filter, first fixed-point conversion module, second fixed-point conversion module, third fixed-point conversion module, programmable downsampling module; wherein,

[0015] The first integrator is connected to the second integrator and the first fixed-point conversion module; the second integrator is connected to the third integrator; and so on, the (N-1)th integrator is connected to the Nth integrator; the Nth integrator is connected to the programmable downsampling module; the programmable downsampling module is connected to the second fixed-point conversion module; the second fixed-point conversion module is connected to the first filter; the second filter is connected to the third filter; and so on, the (N-1)th filter is connected to the Nth filter; the Nth filter is connected to the compensation filter.

[0016] The compensation filter includes:

[0017] The first branch first filter, the first branch second filter, the first branch third filter, ..., the first branch (N-1)th filter, the first branch Nth filter, the second branch first filter, the second branch second filter, the second branch third filter, ..., the second branch (N-1)th filter, the second branch Nth filter, the first downsampling module, the second downsampling module, and the delay unit z-1; where,

[0018] The delay unit z-1 is connected to the integral-comb cascaded filter, the first downsampling module, and the second downsampling module; the first downsampling module is connected to the first filter of the first branch; the first filter of the first branch is connected to the second filter of the first branch and the Nth filter of the second branch; the second filter of the first branch is connected to the third filter of the first branch; and so on. The (N-1)th filter of the first branch is connected to the Nth filter of the first branch; the Nth filter of the first branch is connected to the half-band filter; the second downsampling module is connected to the first filter of the second branch; the first filter of the second branch is connected to the second filter of the second branch; the second filter of the second branch is connected to the third filter of the second branch; and so on. The (N-1)th filter of the second branch is connected to the Nth filter of the second branch; and so on.

[0019] The half-band filter includes:

[0020] First multiplier, second multiplier, third multiplier, ..., (N-1)th multiplier, Nth multiplier, first filter, second filter, third filter, ..., (2N-1)th filter, first downsampling module, second downsampling module, delay unit z-1; where,

[0021] The first downsampling module is connected to the delay unit z-1, the compensation filter, the first multiplier, the second multiplier, the third multiplier, ..., the (N-1)th multiplier; the delay unit z-1 is connected to the second downsampling module; the first multiplier is connected to the first filter and the (2N-1)th filter; the second multiplier is connected to the first filter and the (2N-2)th filter; and so on, the (N-1)th multiplier is connected to the (N-2)th filter and the (N-1)th filter; the second downsampling module is connected to the Nth multiplier; and the Nth multiplier is connected to the Nth filter.

[0022] The Nth integrator includes:

[0023] Adder, delay unit z-1; where,

[0024] The adder is connected to the delay unit z-1 and the programmable downsampling module; the delay unit z-1 is connected to the programmable downsampling module.

[0025] The Nth filter includes:

[0026] Adder, delay unit z-1; where,

[0027] The adder is connected to the (N-1)th filter, the delay unit z-1, and the third fixed-point conversion module; the delay unit z-1 is connected to the (N-1)th filter.

[0028] The first branch Nth filter includes:

[0029] The system comprises a first delay unit z-1, a second delay unit z-1, a first adder, a second adder, and a multiplier; wherein...

[0030] The first delay unit z-1 is connected to the first adder, the (N-1)th filter of the first branch, and the second delay unit z-1; the second delay unit z-1 is connected to the first adder and the (N-1)th filter of the first branch; the first adder is connected to the multiplier; the multiplier is connected to the second adder; and the second adder is connected to the (N-1)th filter of the first branch and the half-band filter.

[0031] The second branch Nth filter includes:

[0032] The system comprises a first delay unit z-1, a second delay unit z-1, a first adder, a second adder, and a multiplier; wherein...

[0033] The first delay unit z-1 is connected to the first adder, the (N-1)th filter of the second branch, and the second delay unit z-1; the second delay unit z-1 is connected to the first adder and the (N-1)th filter of the second branch; the first adder is connected to the multiplier; the multiplier is connected to the second adder; and the second adder is connected to the (N-1)th filter of the second branch and the first filter of the first branch.

[0034] The 2N-1th filter includes:

[0035] Delay unit z-1, adder; where,

[0036] The delay unit z-1 is connected to the 2N-2th filter and the adder; the adder is connected to the first multiplier and the first filter.

[0037] The digital filter structure for downsampling in a Σ-ΔADC can be configured to operate in either fully parallel or serial mode via parameters configured in the register module of the Σ-ΔADC system.

[0038] Compared with the prior art, the present invention has the following technical effects:

[0039] 1. The digital filter structure for downsampling of Σ-Δ ADC of the present invention has the advantages of low power consumption, low area and high flexibility, and is suitable for Σ-Δ ADC design with specific performance requirements.

[0040] 2. In this digital filter structure for Σ-ΔADC downsampling, the downsampling module is moved forward using a recursive integral-comb cascade filter, which reduces hardware resource consumption.

[0041] 3. In this digital filter structure for Σ-Δ ADC downsampling, the compensation filter utilizes linear symmetry of coefficients to reduce the number of multiplication operations, thereby reducing circuit resources and increasing speed. Simultaneously, it reduces the computational speed requirement and significantly improves system parallelism by replicating multiple paths.

[0042] 4. In this digital filter structure for Σ-ΔADC downsampling of the present invention, the half-band filter uses retiming technology to modify the coefficient positions, thereby reducing the critical path delay and increasing the system's highest frequency. Attached Figure Description

[0043] Figure 1This is a schematic diagram of a series third-order feedforward structure of a digital filter structure for downsampling in a Σ-Δ ADC provided by an embodiment of the present invention;

[0044] Figure 2 This is a schematic diagram of an integral-comb cascaded filter architecture for a digital filter structure used for Σ-ΔADC downsampling, provided as an embodiment of the present invention.

[0045] Figure 3 This is a schematic diagram of a compensation filter architecture design for a digital filter structure used for Σ-ΔADC downsampling, provided in an embodiment of the present invention.

[0046] Figure 4 This is a schematic diagram of a half-band filter architecture design for a digital filter structure used for Σ-ΔADC downsampling, provided as an embodiment of the present invention. Detailed Implementation

[0047] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0048] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0049] The present invention will now be described in further detail with reference to specific embodiments.

[0050] Please see Figure 1 , Figure 1 This is a schematic diagram of a three-stage filter series connection for a digital filter structure used for Σ-ΔADC downsampling, provided in an embodiment of the present invention.

[0051] In one aspect of the present invention, the downsampling digital filter is composed of an integral-comb cascaded filter, a compensation filter, and a half-band filter in a multi-stage series configuration to form a third-order single-loop feedforward structure.

[0052] In this case, since the passband of the integrator-comb cascaded filter is not flat when used in low-pass mode, its high-impedance characteristics are also easily affected by the number of cascades. A compensation filter is added to compensate for its spectral characteristics. This compensation filter can also perform a decimation operation at the same time. After compensation, the output data has a flat low-frequency passband and better high-impedance characteristics. The final half-band filter outputs data with a flatter passband and a steeper stopband after final downsampling. The half-band filter can also perform downsampling by 2 times, which reduces the pressure of stopband attenuation on the compensation filter and reduces the area and hardware resource consumption.

[0053] It should be noted that the integrator-comb cascaded filter has three programmable downsampling factors, while the compensation filter and half-band filter have fixed downsampling factors. The required frequency division clock can be generated by modifying parameters through a specified register address of the Σ-ΔADC system, thereby programming and configuring the downsampling factor of the Σ-ΔADC modulator to suit digital filter applications.

[0054] It should be noted that the downsampling filter can be configured to use either fully parallel or serial mode via the register module of the Σ-ΔADC system.

[0055] In the serial mode structure, an adder is repeatedly reused to complete the operation by moving the data window. For the fully parallel mode, the compensation filter is implemented using a highly pipelining, structurally regular pulsating method; the half-band filter is implemented using a transpose method.

[0056] It should be noted that the frequency divider circuit of the Σ-ΔADC system generates the driving clock required inside the downsampling digital filter.

[0057] Furthermore, since the input excitation signal of the digital downsampling filter comes from the output floating-point data of the Σ-Δ modulator, it is also necessary to perform fixed-point conversion on the floating-point numbers and intermediate data, which requires a fixed-point conversion unit.

[0058] It should be noted that, in order to simplify the accompanying drawings, Figure 1 The diagram only shows three fixed-point conversion modules, i.e., the convert modules, in the integral-comb cascaded filter. However, the compensation filter and the half-band filter also require fixed-point conversion units, located at the input of each of the three filters, the output of the internal downsampling module, and the final output.

[0059] Additionally, it should be noted that the orders of the integral-comb cascade filter, the compensation filter, and the half-band filter are calculated based on specific performance requirements and the model.

[0060] Further, please see Figure 2 , Figure 2 This is a schematic diagram of an integral-comb cascaded filter architecture for a digital filter structure used for downsampling in a Σ-Δ ADC.

[0061] In another aspect of the invention, the integrator-comb filter is obtained by cascading an integrator and a comb filter, and cascading multiple integrator-comb filters provides better low-pass properties. Furthermore, the downsampling module is moved forward in the recursive structure. The selected downsampling factor is configured by the frequency division clock generated from the register parameters of the Σ-ΔADC system.

[0062] It should be noted that the amplitude of the cascaded integral-comb filter is calculated using the following formula:

[0063]

[0064] Where R is the deceleration factor, M is a fixed value, and N is the number of series stages.

[0065] Furthermore, it should be noted that the -3dB bandwidth must be specifically considered during calculation. It must be ensured that the dropout rate of the integrator-comb filter within its effective range is greater than the rise rate of the NTF.

[0066] It should be noted that since the excitation of the digital downsampling filter comes from the output of the Σ-Δ modulator, the floating-point number also needs to be converted to a fixed-point value. The fixed-point conversion unit is... Figure 1 The convert module in [the context of the project].

[0067] Specifically, in this embodiment, the integrator-comb filter employs a four-stage structure. In the integrator design, the delay unit is moved to the data path, improving system parallelism and reducing hardware consumption without changing functionality. It also includes a fixed-point conversion module for floating-point to fixed-point conversion and intermediate data processing. Furthermore, the data path is interrupted via pipelined processing, increasing the maximum clock frequency.

[0068] Furthermore, it should be noted that fixed-point design is crucial due to the bit growth inherent in integrator-comb filters. The fixed-point design must be carefully considered in conjunction with the specific hardware implementation to prevent data overflow leading to functional errors while minimizing hardware resource consumption. The maximum bit width of the required fixed-point number for an integrator-comb filter is calculated using the following formula:

[0069]

[0070] Wherein, Bin is the bit width of the input signed data.

[0071] Further, please see Figure 3 , Figure 3This is a schematic diagram of a compensation filter architecture design for a digital filter structure used for downsampling in a Σ-Δ ADC.

[0072] The compensation filter adopts a non-configurable mode, which only compensates for the passband attenuation under the maximum bandwidth of the integral-comb filter, i.e. the minimum downsampling factor, thereby reducing the required area and hardware overhead.

[0073] It should be noted that FIR filters, compared to IIR filters, inherently possess linear phase characteristics, allowing for structural optimization. In the example, the compensation filter has an odd length, satisfying the even symmetry condition, meaning the unit impulse response exhibits periodic symmetry. This symmetrical structure saves nearly half the computational overhead, and the pre-processing and decomposition of the extraction path reduces computational speed requirements and data waste.

[0074] Specifically, in this embodiment, the number of filter data paths is related to the downsampling factor, and replicating multiple paths greatly improves the parallelism of the system. Furthermore, each path of the compensation filter does not operate simultaneously, eliminating the waste of intermediate computation time. In the integrator design, the delay unit is adjusted to the data path, improving system parallelism while reducing hardware consumption without changing functionality.

[0075] Furthermore, it should be noted that the input to the compensation filter is the output of the preceding integrator-comb filter, therefore it also requires a fixed-point unit. The higher the required accuracy, the larger the required order. The minimum bit width of the fixed-point unit for the compensation filter is calculated using the following formula:

[0076]

[0077] Where Ap is the stopband attenuation and L is the filter order.

[0078] It should be noted that, in order to simplify the accompanying drawings, Figure 3 The fixed-point conversion module, i.e., the convert module, is not shown in the diagram. The fixed-point conversion module of the compensation filter is located at the input end of the compensation filter, the output end of each internal downsampling module, and the final output end.

[0079] Further, please see Figure 4 , Figure 4 This is a schematic diagram of a half-band filter architecture design for a digital filter structure used for downsampling in a Σ-Δ ADC.

[0080] Specifically, half-band filters utilize spectral mirroring; if their order is odd, half of their coefficients are zero. The actual number of multiplications required, i.e., the required input fan-out capability, is much smaller than that of compensated filters. A parallel structure is achieved by replicating multiple paths, and retiming techniques are used to modify the coefficient positions, reducing critical path delay and increasing the system's highest frequency.

[0081] It should be noted that the input to the half-band filter is the output of the preceding compensation filter. For the sake of simplicity, the accompanying diagram is provided below. Figure 4 The fixed-point conversion module, i.e., the convert module, is not shown in the figure, but the half-band filter also needs a fixed-point unit to process the floating-point data generated in the middle. Its fixed-point conversion module is located at the input end of the half-band filter, the output end of each internal downsampling module, and the final output end.

[0082] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A digital filter for Sigma-Delta ADC down-sampling, characterized by, The application relates to an integral-comb cascade filter, a compensation filter and a half-band filter. The input end of the integral-comb cascade filter is connected with a signal input end used for inputting an output signal of a sigma-delta ADC modulator. The output end of the integral-comb cascade filter is connected with the input end of the compensation filter. The output end of the compensation filter is connected with the input end of the half-band filter. The output end of the half-band filter outputs a filtered signal. The integral-comb cascade filter comprises a first integrator, a second integrator, a third integrator, an N-1 integrator, an N integrator, a first filter, a second filter, a third filter, an N-1 filter, an N filter, a first fixed-point conversion module, a second fixed-point conversion module, a third fixed-point conversion module and a programmable down-sampling module. The first integrator is connected with the second integrator and the first fixed-point conversion module; the second integrator is connected with the third integrator; the N-1 integrator is connected with the N integrator; the N integrator is connected with the programmable down-sampling module; the programmable down-sampling module is connected with the second fixed-point conversion module; the second fixed-point conversion module is connected with the first filter; the second filter is connected with the third filter; the N-1 filter is connected with the N filter; and the N filter is connected with the compensation filter. The compensation filter comprises: The half-band filter comprises: The digital filter for the sigma-delta ADC down-sampling selects two modes of full parallel and series through register module configuration parameters of the sigma-delta ADC system. a first branch first filter, a first branch second filter, a first branch third filter, a first branch N-1th filter, a first branch Nth filter, a second branch first filter, a second branch second filter, a second branch third filter, a second branch N-1th filter, a second branch Nth filter, a first down-sampling module, a second down-sampling module, a delay unit z -1 ; wherein, The delay unit z -1 The integral-comb cascade filter is connected with a first down-sampling module, a second down-sampling module; the first down-sampling module is connected with the first branch first filter; the first branch first filter is connected with the first branch second filter and the second branch Nth filter; the first branch second filter is connected with the first branch third filter; by analogy, the first branch N-1th filter is connected with the first branch Nth filter; the first branch Nth filter is connected with a half-band filter; the second down-sampling module is connected with the second branch first filter; the second branch first filter is connected with the second branch second filter; the second branch second filter is connected with the second branch third filter; by analogy, the second branch N-1th filter is connected with the second branch Nth filter; the second branch N-1th filter is connected with the second branch Nth filter; The N integrator comprises: a first multiplier, a second multiplier, a third multiplier, a (N-1)th multiplier, an Nth multiplier, a first filter, a second filter, a third filter, a 2N-1th filter, a first down-sampling module, a second down-sampling module, a delay unit z -1 ; wherein, The first down-sampling module is connected with the delay unit z -1 , a compensation filter, a first multiplier, a second multiplier, a third multiplier, …, an N-1 multiplier; the delay unit z -1 is connected with the second down-sampling module; the first multiplier is connected with the first filter, a 2N-1 filter; the second multiplier is connected with the first filter, a 2N-2 filter; by analogy, the N-1 multiplier is connected with an N-2 filter, an N-1 filter; the second down-sampling module is connected with the Nth multiplier; the Nth multiplier is connected with the Nth filter; The N filter comprises:

2. The digital filter for Sigma-Delta ADC down-sampling according to claim 1, characterized in that, The first branch N filter comprises: adder, delay unit z -1 ; wherein, The adder is connected with the delay unit z -1 , programmable down-sampling module; the delay unit z -1 is connected with the programmable down-sampling module.

3. The digital filter for Sigma-Delta ADC down-sampling of claim 1, wherein, The second branch N filter comprises: adder, delay unit z -1 ; wherein, The adder is connected with the N-1 filter and the delay unit z -1 The third fixed-point conversion module is connected with the delay unit z -1 The delay unit z is connected with the N-1 filter.

4. The digital filter for Sigma-Delta ADC down-sampling of claim 1, wherein, The 2N-1 filter comprises: a first delay unit z -1 a second delay unit z -1 a first adder, a second adder, a multiplier; wherein, The first delay unit z -1 With the first adder, the (N-1)th filter of the first branch, and the second delay unit z -1 Connected; the second delay unit z -1 It is connected to the first adder and the (N-1)th filter of the first branch; the first adder is connected to the multiplier; the multiplier is connected to the second adder; the second adder is connected to the (N-1)th filter of the first branch and the half-band filter.

5. The digital filter for down-sampling of a sigma-delta ADC according to claim 1, characterized in that, ​ a first delay unit z -1 a second delay unit z -1 a first adder, a second adder, a multiplier; wherein, The first delay unit z -1 With the first adder, the (N-1)th filter of the second branch, and the second delay unit z -1 Connected; the second delay unit z -1 It is connected to the first adder and the (N-1)th filter of the second branch; the first adder is connected to the multiplier; the multiplier is connected to the second adder; the second adder is connected to the (N-1)th filter of the second branch and the first filter of the first branch.

6. The digital filter for down-sampling of a sigma-delta ADC according to claim 1, characterized in that, ​ Delay unit z -1 , an adder; wherein, The delay unit z -1 The second filter is connected with the second N-2 filter and the adder.

Images