Duty cycle calibration circuit and method

Abstract

The present invention discloses a duty cycle calibration circuit and method, relating to the technical field of integrated circuit design. The duty cycle calibration circuit includes a reference current mirror circuit, a duty cycle detection circuit, a duty cycle adjustment circuit, a divide-by-two frequency circuit, and a digital state machine. The reference current mirror circuit includes a first MOS transistor for receiving an input reference current, a second MOS transistor for shutting down the circuit, a third MOS transistor for current mirroring, and an OR gate. The output of the third MOS transistor is connected to the drain of a current mirror PMOS transistor in the duty cycle detection circuit. During operation, the duty cycle calibration circuit of the present invention does not require a large RC circuit or 0.5 times the power supply voltage. The circuit structure is simple, reducing system complexity and chip area.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and more particularly to a duty cycle calibration circuit and method for a clock signal. Background Art

[0002] The duty cycle of a clock signal refers to the proportion of time a high level remains active within a single clock cycle. During circuit design and manufacturing, device parameter mismatches and inconsistencies in the drive capabilities of PMOS and NMOS transistors in the clock driver circuit can cause the clock signal's duty cycle to deviate from the ideal 50%. This deviation can make it more difficult to meet circuit timing requirements and introduce deterministic duty cycle distortion and jitter into the output signal's eye diagram, reducing the eye opening.

[0003] The traditional duty cycle calibration circuit uses a low-pass filter (including but not limited to operational amplifiers, resistors and capacitors) to filter out the high-frequency components in the clock signal, retain the DC component voltage, and then compare the DC component voltage with 0.5 times the power supply voltage to determine the relationship between the current clock signal duty cycle and 50%; however, this method requires larger resistor and capacitor values to effectively filter out the high-frequency components in the clock signal, and larger resistors and resistance values occupy a large chip area; jitter on the power supply voltage affects the output of the low-pass filter and the 0.5 times the power supply voltage generation circuit through different paths, thereby causing errors in the calibration circuit results; as the power supply voltage continues to decrease under advanced processes, the error in the process of generating 0.5 times the power supply voltage has an increasingly greater impact on duty cycle calibration; and the low bandwidth of the low-pass filter means that after each round of duty cycle adjustment, it takes a long time to wait before the accurate DC component voltage of the current clock signal is obtained. Summary of the Invention

[0004] The purpose of the present invention is to provide a duty cycle calibration circuit and method thereof, so that the duty cycle calibration circuit does not require a large-area RC circuit during operation, and does not require 0.5 times the power supply voltage, so as to solve the problems raised in the above background technology.

[0005] To achieve the above object, according to one aspect of the present invention, the present invention provides a duty cycle calibration circuit, which includes a reference current mirror circuit, a duty cycle detection circuit, a duty cycle adjustment circuit, a two-frequency divider circuit, and a digital state machine;

[0006] The reference current mirror circuit includes a first MOS transistor for receiving an input reference current, a second MOS transistor for shutting down the circuit, a third MOS transistor for current mirroring, and an OR gate. The output of the third MOS transistor is connected to the drain of the current mirror PMOS transistor in the duty cycle detection circuit.

[0007] A first input port of the OR gate is connected to an output Reset signal of the digital state machine, and a second input port of the OR gate is connected to a shutdown control signal of the duty cycle calibration circuit;

[0008] The duty cycle detection circuit includes a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor for current mirroring, a seventh MOS transistor and an eighth MOS transistor for switch control, a capacitor C1, a capacitor C2, a first reset switch, a second reset switch, a first comparator, and a second comparator;

[0009] The first reset switch and the second reset switch are each composed of an NMOS transistor; the negative end of the first reset switch is grounded, and the positive end is connected to the positive end of capacitor C1; the negative end of the second reset switch is grounded, and the positive end is connected to the positive end of capacitor C2; the value of capacitor C1 is equal to the value of capacitor C2; the negative end of capacitor C1 is grounded, and the positive end is connected to the positive input end of the first comparator; the negative end of capacitor C2 is grounded, and the positive end is connected to the positive input end of the second comparator; the negative input ends of the first comparator and the second comparator are connected to a fixed voltage VREF; the outputs of the first comparator and the second comparator are connected to a digital state machine; the gate of the switch-controlled seventh MOS transistor is connected to the first output end of the duty cycle adjustment circuit; and the gate of the switch-controlled eighth MOS transistor is connected to the first output end of the divide-by-two circuit.

[0010] Preferably, the divide-by-two frequency circuit is composed of a flip-flop DFF, and the duty cycle of the output clock signal of the divide-by-two frequency circuit is 50%.

[0011] Preferably, the first input terminal of the duty cycle adjustment circuit is connected to the input clock with a non-ideal duty cycle; the second input terminal of the duty cycle adjustment circuit is connected to the output terminal of the digital state machine; and the second output terminal of the duty cycle adjustment circuit is connected to the first input terminal of the binary frequency divider circuit.

[0012] Preferably, the clock signal passing through the duty cycle adjustment circuit is connected to the gate of the seventh MOS transistor controlled by the switch to control the charging time of the capacitor C1;

[0013] When the duty cycle is less than 50%, the capacitor C1 is charged for more than half of the fixed time t. When the duty cycle is greater than 50%, the capacitor C1 is charged for less than half of the fixed time t. The output voltage of the charged capacitor C1 is V1.

[0014] The clock signal at the first output terminal of the divide-by-two circuit is connected to the gate of the eighth MOS transistor controlled by the switch to control the charging time of the capacitor C2. Since the duty cycle of the clock signal output by the divide-by-two circuit is 50%, half of the fixed time t is spent charging the capacitor C2. The output voltage of the charged capacitor C2 is V2.

[0015] The relationship between the charging current and voltage of a capacitor is:

[0016] dU=I*dt / C

[0017] Where dU is the change in voltage, I is the charging current, dt is the charging time, and C is the capacitance value.

[0018] Preferably, when the duty cycle is greater than 50%, the rising speed of V1 is less than the rising speed of V2, and the flip time of the output voltage of the first comparator from a low level to a high level is later than the flip time of the output voltage of the second comparator from a low level to a high level; conversely, when the duty cycle is less than 50%, the rising speed of V1 is greater than the rising speed of V2, and the flip time of the output voltage of the first comparator from a low level to a high level is earlier than the flip time of the output voltage of the second comparator from a low level to a high level;

[0019] Meanwhile, when the capacitors C1 and C2 are being charged, both the first reset switch and the second reset switch are turned off.

[0020] According to a second aspect of the present invention, the present invention provides a calibration method for a duty cycle calibration circuit, the method comprising the following steps:

[0021] The digital state machine receives the output voltages of the first comparator and the second comparator, and determines whether the duty cycle of the current clock signal is greater than 50% by comparing the time when the voltages of the first comparator and the second comparator flip;

[0022] When the digital state machine determines that the duty cycle of the current clock signal is greater than 50%, the control word signal at the second input terminal of the duty cycle adjustment circuit is modified to reduce the duty cycle of the output clock signal of the duty cycle adjustment circuit;

[0023] When the digital state machine determines that the duty cycle of the current clock signal is less than 50%, the control word signal at the second input terminal of the duty cycle adjustment circuit is modified to increase the duty cycle of the output clock signal of the duty cycle adjustment circuit;

[0024] After completing one round of duty cycle adjustment, the first reset switch and the second reset switch are turned on to release the charge at the positive terminals of capacitors C1 and C2. Voltages V1 and V2 are then connected to ground until the next round of duty cycle detection begins. The first reset switch and the second reset switch are then turned off to ensure that the charging starting voltages of capacitors C1 and C2 are both 0.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] A duty cycle calibration circuit disclosed herein controls the on / off switching of a switching tube via a clock signal, thereby controlling the charging time of a charging capacitor. The positive terminals of two charging capacitors are compared with a reference voltage VREF via two comparators. A digital state machine analyzes the order in which the output voltages of the two comparators flip from 0 to 1, thereby determining the relationship between the duty cycle of the current clock signal and 50%. Furthermore, the circuit has a simple structure and does not require large resistors and capacitors, thereby reducing system complexity and chip area.

[0027] The duty cycle calibration circuit described in the present invention connects the output voltages of two charging capacitors to the positive input terminals of two comparators respectively, and connects the negative input terminals of the two comparators to a reference voltage VREF. Unlike the 0.5 times power supply voltage that needs to be calibrated in the traditional duty cycle calibration circuit, the reference voltage VREF in this embodiment only needs to be greater than 0 in theory. In practical applications, it can be set between 0.4 times and 0.9 times the power supply voltage, thereby reducing the complexity of the reference voltage generation circuit.

[0028] The calibration method of the duty cycle calibration circuit described in the present invention can determine the difference between the current duty cycle and the ideal value of 50% in a short time after each round of duty cycle adjustment. Unlike traditional low-pass filters, there is no need to wait for a long time to obtain the accurate DC component voltage of the current clock signal. The present invention has the advantage of fast calibration speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a circuit module diagram of a duty cycle calibration circuit of the present invention.

[0030] Figure 2 It is a circuit structure diagram of a duty cycle calibration circuit of the present invention.

[0031] Figure 3 This is a structural diagram of a reset switch circuit of a duty cycle calibration circuit of the present invention.

[0032] Figure 4 The diagram is a structure diagram of a two-frequency division circuit of a duty cycle calibration circuit of the present invention.

[0033] Figure 5 It is a waveform diagram of a duty cycle adjustment circuit output clock signal, a two-frequency division circuit output clock signal, a capacitor C1 positive terminal voltage, and a capacitor C2 positive terminal voltage in a duty cycle calibration circuit of the present invention. DETAILED DESCRIPTION

[0034] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0035] The traditional duty cycle calibration circuit uses a low-pass filter (including but not limited to operational amplifiers, resistors and capacitors) to filter out the high-frequency components in the clock signal, retain the DC component voltage, and then compare the DC component voltage with 0.5 times the power supply voltage to determine the relationship between the current clock signal duty cycle and 50%; however, this method requires larger resistor and capacitor values to effectively filter out the high-frequency components in the clock signal, and larger resistors and resistance values occupy a large chip area; as the power supply voltage continues to decrease under advanced processes, the error in the process of generating 0.5 times the power supply voltage has an increasingly greater impact on duty cycle calibration; the jitter on the power supply voltage affects the output of the low-pass filter and the 0.5 times the power supply voltage generation circuit through different paths, thereby causing errors in the calibration circuit results; and the low bandwidth of the low-pass filter requires a long wait time after each round of duty cycle adjustment to obtain the accurate DC component voltage of the current clock signal.

[0036] like Figure 1 As shown, a duty cycle calibration circuit according to an embodiment of the present invention includes: a reference current mirror circuit, a duty cycle detection circuit, a duty cycle adjustment circuit, a two-frequency division circuit and a digital state machine.

[0037] like Figure 2 As shown, a structural diagram of a duty cycle calibration circuit according to an embodiment of the present invention, NMOS transistor NM0, NMOS transistor NM1, NMOS transistor NM2 and an OR gate constitute a reference current mirror circuit;

[0038] The drain of the NMOS transistor NM1 is connected to the reference input current I_ref, the drain of the NMOS transistor NM1 is connected to the gate of the NMOS transistor NM1, and the drain of the NMOS transistor NM1 is connected to the drain of the NMOS transistor NM0;

[0039] The source of the NMOS transistor NM1 is grounded;

[0040] The source of the NMOS transistor NM0 is grounded, and the gate of the NMOS transistor NM0 is connected to the OR gate to output the Ctrl signal;

[0041] A first input port of the OR gate is connected to the output Reset signal of the digital state machine, and a second input port of the OR gate is connected to the shutdown control signal PD of the duty cycle calibration circuit.

[0042] The source of the NMOS transistor NM2 is grounded, and the drain of the NMOS transistor NM2 is connected to the drain of the PMOS transistor PM1;

[0043] The duty cycle detection circuit includes a PMOS transistor PM1, a PMOS transistor PM2, a PMOS transistor PM4, a PMOS transistor PM3, a PMOS transistor PM5, a capacitor C1, a capacitor C2, a reset switch SW1, a reset switch SW2, a comparator COMP1 and a comparator COMP2;

[0044] The drain of the PMOS transistor PM1 is connected to the gate of the PMOS transistor PM2, the drain of the PMOS transistor PM1 is connected to the gate of the PMOS transistor PM2, and the drain of the PMOS transistor PM1 is connected to the gate of the PMOS transistor PM4;

[0045] The source of the PMOS transistor PM1 is connected to the power supply VDD, the source of the PMOS transistor PM2 is connected to the power supply VDD, and the source of the PMOS transistor PM4 is connected to the power supply VDD;

[0046] The ratio of the width to the length of the PMOS transistor PM2 is equal to k times the ratio of the width to the length of the PMOS transistor PM1 , where k is set according to the required duty cycle detection speed.

[0047] The width and length of the PMOS transistor PM2 and the PMOS transistor PM4 are the same, and the currents output by the two are also equal;

[0048] The drain of the PMOS transistor PM2 is connected to the source of the PMOS transistor PM3 , the gate of the PMOS transistor PM3 is connected to the clock signal CLK_Adjust output by the duty cycle adjustment circuit, the drain of the PMOS transistor PM3 is connected to the first port of the capacitor C1 , and the drain of the PMOS transistor PM3 is connected to the first port of the reset switch SW1 ;

[0049] The second terminal of the capacitor C1 is grounded, and the second terminal of the reset switch SW1 is grounded;

[0050] The drain of the PMOS transistor PM4 is connected to the source of the PMOS transistor PM5, the gate of the PMOS transistor PM5 is connected to the clock signal CLK_DIV2 output by the divide-by-two circuit, the drain of the PMOS transistor PM5 is connected to the first port of the capacitor C2, and the drain of the PMOS transistor PM5 is connected to the first port of the reset switch SW2;

[0051] The input port of the two-frequency divider circuit is connected to the clock signal CLK_Adjust output by the duty cycle adjustment circuit;

[0052] A second port of the capacitor C2 is grounded, and a second port of the reset switch SW2 is grounded;

[0053] The control signal of the reset switch SW1 is the output Reset signal of the digital state machine, and the control signal of the reset switch SW2 is the output Reset signal of the digital state machine;

[0054] The first terminal of the capacitor C1 is connected to the positive input terminal of the comparator COMP1, and the first terminal of the capacitor C2 is connected to the positive input terminal of the comparator COMP2;

[0055] The value of capacitor C1 is equal to the value of capacitor C2;

[0056] The negative input terminal of the comparator COMP1 is connected to the fixed reference voltage VREF, and the negative input terminal of the comparator COMP2 is connected to the fixed reference voltage VREF;

[0057] When the voltage at the positive input port of the comparator is greater than the voltage at the negative input port, the comparator outputs a high level, otherwise it outputs a low level;

[0058] Theoretically, the value of the fixed reference voltage VREF can be greater than 0. In practical applications, it is recommended to set it between 0.4 times and 0.9 times the power supply voltage.

[0059] The output out_div2 of the comparator COMP1 is connected to the first input port of the digital state machine, and the output out_clk of the comparator COMP2 is connected to the second input port of the digital state machine;

[0060] The clock signal CLK_IN with duty cycle distortion is connected to the first input port of the duty cycle adjustment circuit, and the output signal CTRL_Code of the digital state machine is connected to the second input port of the duty cycle adjustment circuit;

[0061] like Figure 3 As shown, the reset switches SW1 and SW2 are both composed of NMOS transistors. The gates of the NMOS transistors of the reset switches SW1 and SW2 are connected to the OR gate output signal Ctrl. When the Ctrl signal is high, the reset switch is turned on, otherwise the reset switch is turned off.

[0062] like Figure 4 As shown, the divide-by-two circuit is composed of a DFF, the clock input port of the DFF circuit is connected to the clock signal CLK_Adjust output by the duty cycle adjustment circuit, the output QB of the DFF circuit is connected to the data input port D of the DFF, and the output Q of the DFF circuit is the clock signal CLK_DIV2 output by the divide-by-two circuit.

[0063] Working Principle: The reference current mirror circuit includes an OR gate. The first input of the OR gate is connected to the Reset signal output from the digital state machine, and the second input is connected to the shutdown control signal PD of the duty cycle calibration circuit. When PD is high, the output signal Ctrl of the OR gate is high, the gate of the NMOS transistor NM0 is high, and the drain of the NMOS transistor NM0 is low. The output current of the reference current mirror circuit is approximately zero, the current of the duty cycle calibration circuit is also approximately zero, and the entire duty cycle calibration circuit is shut down.

[0064] When PD is high, the output signal Ctrl of the OR gate is high, the reset switches SW1 and SW2 are both turned on, the positive input ports of comparators COMP1 and COMP2 are connected to the ground, and the outputs of comparators COMP1 and COMP2 are both low.

[0065] When PD jumps from high level to low level, the output signal Ctrl of the OR gate is determined by the output Reset of the digital state machine. When the calibration starts, Reset jumps from high level to low level, the output signal Ctrl of the OR gate is low level, the gate of the NMOS transistor NM0 is low level, the NMOS transistor NM0 is turned off, and the duty cycle calibration circuit is turned on.

[0066] When the output signal Ctrl of the OR gate is at a low level, both reset switches SW1 and SW2 are turned off.

[0067] The gate of the PMOS transistor PM3 is connected to the clock signal CLK_Adjust output by the duty cycle adjustment circuit. When CLK_Adjust is at a low level, the output current of the PMOS transistor PM2 starts to charge the capacitor C1. When CLK_Adjust is at a high level, the PMOS transistor PM3 is turned off and the voltage on the capacitor C1 remains unchanged.

[0068] The gate of the PMOS transistor PM5 is connected to the clock signal CLK_DIV2 output by the divide-by-two circuit. When CLK_DIV2 is low, the output current of the PMOS transistor PM4 starts to charge the capacitor C2. When CLK_DIV2 is high, the PMOS transistor PM5 is turned off and the voltage on the capacitor C2 remains unchanged.

[0069] like Figure 5 As shown, when the input clock signal CLK_IN has duty cycle distortion, the clock signal CLK_Adjust output by the duty cycle adjustment circuit also has duty cycle distortion at the beginning of calibration, and the duty cycle of the clock signal CLK_DIV2 output by the divide-by-two circuit can still be equal to 50%.

[0070] When the duty cycle is less than 50%, the capacitor C1 is charged for more than half of the fixed time t. When the duty cycle is greater than 50%, the capacitor C1 is charged for less than half of the fixed time t. The output voltage of the charged capacitor C1 is V1.

[0071] Since the duty cycle of the clock signal output by the divide-by-two circuit is 50%, half of the fixed time t is spent charging the second capacitor. The output voltage of the charged capacitor C2 is V2.

[0072] The relationship between the charging current and voltage of a capacitor is dU = I*dt / C, where dU is the change in voltage, I is the charging current, dt is the charging time, and C is the capacitance value.

[0073] When the duty cycle of the clock signal CLK_Adjust is greater than 50%, within the fixed time t, less than half of the time is spent charging the capacitor C1. Therefore, the rising speed of V1 is slower than the rising speed of V2. The output voltage of comparator COMP1 switches from a low level to a high level later than the output voltage of comparator COMP2 switches from a low level to a high level.

[0074] On the contrary, when the duty cycle is less than 50%, within the fixed time t, more than half of the time is spent charging the capacitor C1, so the rising speed of V1 is greater than the rising speed of V2, and the output voltage of comparator COMP1 flips from a low level to a high level earlier than the output voltage of comparator COMP2 flips from a low level to a high level.

[0075] The digital state machine receives the output signal out_div2 of the comparator COMP1 and the output signal out_clk of the comparator COMP2, and determines the relationship between the current duty cycle of the clock signal CLK_Adjust and 50% by comparing the time when the voltages of out_div2 and out_clk flip.

[0076] When the digital state machine determines that the current duty cycle of the clock signal CLK_Adjust is greater than 50%, the output signal CTRL_Code is adjusted to reduce the duty cycle of the output clock signal CLK_Adjust of the duty cycle adjustment circuit. Similarly, when the digital state machine determines that the current duty cycle of the clock signal CLK_Adjust is less than 50%, the output signal CTRL_Code is adjusted to increase the duty cycle of the output clock signal CLK_Adjust of the duty cycle adjustment circuit.

[0077] When the output voltage of comparator COMP1 or COMP2 flips from low level to high level, a round of duty cycle calibration is completed, the output Reset signal of the digital state machine changes from low level to high level, the OR gate output signal Ctrl changes to high level, the reset switches SW1 and SW2 are turned on, and the positive terminals of capacitors C1 and C2 are connected to ground, that is, the voltages V1 and V2 are approximately equal to 0; until the next round of duty cycle detection begins, the Reset signal changes from high level to low level, the OR gate output signal Ctrl changes to low level, and the reset switches SW1 and SW2 are turned off, ensuring that the charging starting voltages of capacitors C1 and C2 are equal and both are 0.

[0078] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0079] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A duty cycle calibration circuit, characterized in that: The duty cycle calibration circuit includes a reference current mirror circuit, a duty cycle detection circuit, a duty cycle adjustment circuit, a two-frequency division circuit and a digital state machine; The reference current mirror circuit includes a first MOS transistor for receiving an input reference current, a second MOS transistor for shutting down the circuit, a third MOS transistor for current mirroring, and an OR gate. The output of the third MOS transistor is connected to the drain of the current mirror PMOS transistor in the duty cycle detection circuit. A first input port of the OR gate is connected to an output Reset signal of the digital state machine, and a second input port of the OR gate is connected to a shutdown control signal of the duty cycle calibration circuit; The duty cycle detection circuit includes a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor for current mirroring, a seventh MOS transistor and an eighth MOS transistor for switch control, a capacitor C1, a capacitor C2, a first reset switch, a second reset switch, a first comparator, and a second comparator; The first reset switch and the second reset switch are each composed of an NMOS transistor; the negative terminal of the first reset switch is grounded, and the positive terminal is connected to the positive terminal of capacitor C1; the negative terminal of the second reset switch is grounded, and the positive terminal is connected to the positive terminal of capacitor C2; the value of capacitor C1 is equal to the value of capacitor C2; the negative terminal of capacitor C1 is grounded, and the positive terminal is connected to the positive input terminal of the first comparator; the negative terminal of capacitor C2 is grounded, and the positive terminal is connected to the positive input terminal of the second comparator; the negative input terminals of the first comparator and the second comparator are connected to a fixed voltage VREF; the outputs of the first comparator and the second comparator are connected to the digital state machine; the gate of the switch-controlled seventh MOS transistor is connected to the first output terminal of the duty cycle adjustment circuit; the gate of the switch-controlled eighth MOS transistor is connected to the first output terminal of the divide-by-two circuit; The divide-by-two frequency circuit is composed of a flip-flop DFF, and the duty cycle of the output clock signal of the divide-by-two frequency circuit is 50%; The first input terminal of the duty cycle adjustment circuit is connected to the input clock of the non-ideal duty cycle; the second input terminal of the duty cycle adjustment circuit is connected to the output terminal of the digital state machine; the second output terminal of the duty cycle adjustment circuit is connected to the first input terminal of the two-frequency divider circuit; The clock signal of the duty cycle adjustment circuit is connected to the gate of the seventh MOS tube controlled by the switch to control the charging time of the capacitor C1; When the duty cycle is less than 50%, the capacitor C1 is charged for more than half of the fixed time t. When the duty cycle is greater than 50%, the capacitor C1 is charged for less than half of the fixed time t. The output voltage of the charged capacitor C1 is V1. The clock signal at the first output of the divide-by-two circuit is connected to the gate of the eighth MOS transistor controlled by the switch to control the charging time of the capacitor C2. Since the duty cycle of the clock signal output by the divide-by-two circuit is 50%, half of the fixed time t is spent charging the capacitor C2. The output voltage of the charged capacitor C2 is V2. The relationship between the charging current and voltage of a capacitor is: dU=I*dt / C Where dU is the change in voltage, I is the charging current, dt is the charging time, and C is the capacitance value. When the duty cycle is greater than 50%, the rising speed of V1 is less than the rising speed of V2, and the switching time of the output voltage of the first comparator from low level to high level is later than the switching time of the output voltage of the second comparator from low level to high level; conversely, when the duty cycle is less than 50%, the rising speed of V1 is greater than the rising speed of V2, and the switching time of the output voltage of the first comparator from low level to high level is earlier than the switching time of the output voltage of the second comparator from low level to high level; Meanwhile, when the capacitors C1 and C2 are being charged, both the first reset switch and the second reset switch are turned off.

2. A calibration method for a duty cycle calibration circuit, applied to the duty cycle calibration circuit according to claim 1, characterized in that: The method comprises the following steps: The digital state machine receives the output voltages of the first comparator and the second comparator, and determines the size of the duty cycle of the current clock signal relative to 50% by comparing the time when the voltages of the first comparator and the second comparator flip; When the digital state machine determines that the duty cycle of the current clock signal is greater than 50%, the control word signal at the second input terminal of the duty cycle adjustment circuit is modified to reduce the duty cycle of the output clock signal of the duty cycle adjustment circuit; When the digital state machine determines that the duty cycle of the current clock signal is less than 50%, the control word signal at the second input terminal of the duty cycle adjustment circuit is modified to increase the duty cycle of the output clock signal of the duty cycle adjustment circuit; After completing one round of duty cycle adjustment, the first reset switch and the second reset switch are turned on to release the charge at the positive terminals of capacitors C1 and C2. Voltages V1 and V2 are then connected to ground until the next round of duty cycle detection begins. The first reset switch and the second reset switch are then turned off to ensure that the charging starting voltages of capacitors C1 and C2 are both 0.

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