Circuit for supplying clock signal

Abstract

The present disclosure provides a circuit for supplying a clock signal. An example circuit for supplying clock signals includes: a selector to select a signal from a plurality of clock signals; and a switch between the selector and a node for outputting the selected clock signal, the circuit being configured such that application of a control signal for selecting one of the clock signals sequentially causes the switch to turn off, select the signal via the selector, and turn on the switch.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATION(S)

[0002] This application claims the benefit of priority to French patent application No. FR2310260, filed on September 27, 2023, entitled “Circuit de fourniture d'unsignal d'horloge”, which is hereby incorporated herein by reference to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to circuits for supplying clock signals and associated methods. Background Art

[0004] Most digital circuits use multiple clock signals to control the synchronization of their operations. When using these circuits, the selection and transfer from one clock signal to another requires special attention to the risk of glitches. Current schemes for clock signal selection are very energy-consuming and occupy a large chip surface area. Summary of the invention

[0005] There is a need to limit glitches during the selection of the clock signal while limiting power consumption and necessary chip surface area.

[0006] Embodiments overcome all or part of the disadvantages of known electronic circuits.

[0007] An embodiment provides a circuit for supplying a clock signal, comprising:

[0008] A selector for selecting one signal from among a plurality of clock signals;

[0009] a switch between the selector and a node for outputting the selected clock signal,

[0010] The circuit is configured such that application of a control signal for selecting one of the clock signals sequentially results in turning off the switch, selecting the signal via the selector, and turning on the switch.

[0011] An embodiment provides a method of operating a circuit for supplying a clock signal, the method comprising the following consecutive steps as a result of applying a control signal for selecting a signal:

[0012] - a turn-off switch coupled to a selector for selecting a clock signal from a plurality of clock signals and an output node;

[0013] -selecting a signal via a selector; and

[0014] - Turn on the switch.

[0015] In an embodiment, the circuit is configured to turn off the switch when a change in the selection control signal is detected.

[0016] In an embodiment, the circuit is configured to select the signal after a first delay of at least two rising edges of the shift signal after detecting the change.

[0017] In an embodiment, the circuit is configured to, after selection, turn on the switch after a second delay of at least two rising edges of the shift signal.

[0018] In an embodiment, the electronic circuit is configured to generate a first signal using the first circuit when a change is detected.

[0019] In an embodiment, the circuit is configured to generate a second signal using a second circuit, the second signal being derived from the first signal and shifted in time by the first delay.

[0020] In an embodiment, the second circuit includes an SR-type latch, an output of which is coupled to an inverter, which is connected in series with an input of a shift register including at least two stages and / or delay cells;

[0021] A second signal is generated at an output of the shift register;

[0022] A first input terminal of the SR-type latch is configured to receive a first signal, and a second input terminal of the SR-type latch is configured to receive a second signal.

[0023] In an embodiment, the circuit comprises a third circuit configured to propagate a selection control signal to a signal selector according to an output authorization of the first logic block, the first logic block being capable of performing a NOR function based on a signal present at an output of the inverter and a second signal.

[0024] In an embodiment, the third circuit comprises one latch per control signal forming a selection control signal, each latch having:

[0025] a gate input terminal coupled to an output terminal of the first logic block,

[0026] a data input terminal configured to receive a corresponding control signal, and

[0027] Coupled to the output terminal of the signal selector.

[0028] In an embodiment, the shift signal is a clock signal having a frequency less than or equal to a frequency of a signal having a smallest frequency among the plurality of clock signals.

[0029] In an embodiment, the switch comprises a first block having:

[0030] coupled to the clock input of the selector,

[0031] a first enable input terminal coupled to the output terminal of the first logic block; and

[0032] an output terminal coupled to a second enable input terminal of a second block of switches; and

[0033] An output terminal of the second block of switches is coupled to the output node, and a clock input terminal of the second block is coupled to the output terminal of the selector.

[0034] In an embodiment, when the output of the first logic block is at a low level, the switch is configured to be turned off.

[0035] In an embodiment, when the output of the first logic block is at a high level, the switch is configured to be turned on and then the selected clock signal is at the output node.

[0036] In an embodiment, the first block of the switch includes a first flip-flop and a second flip-flop connected in series, the clock input of the first block is the clock input of the first flip-flop, and the output of the second flip-flop is coupled to the second enable input of the second block.

[0037] An embodiment provides a microcontroller comprising circuitry for supplying a clock signal such as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above features and advantages and other features and advantages will be described in detail in the following disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0039] Figure 1 A simplified view of an example of an electronic circuit is shown;

[0040] Figure 2 Very schematically shown Figure 1 Examples of implementations of electronic circuit blocks;

[0041] Figure 3 Very schematically shows a Figure 1 Blocks of electronic circuits;

[0042] Figure 4 It shows that according to the embodiment Figure 3 The circuit of the block;

[0043] Figure 5 It shows that according to the embodiment Figure 3 The circuit of the block;

[0044] Figure 6 It shows that according to the embodiment Figure 3 The circuit of the block;

[0045] Figure 7 It shows that according to the embodiment Figure 3 The circuit of the block; and

[0046] Figure 8 yes Figure 3 A timing diagram of the operation of the block. DETAILED DESCRIPTION

[0047] Similar features in the various figures are denoted by similar reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0048] For clarity, only the steps and elements that are useful for understanding the embodiments are illustrated and described in detail.

[0049] Unless otherwise specified, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0050] In the following description, when terms indicating absolute positions, such as terms "front", "back", "up", "down", "left", "right", etc., or terms indicating relative positions, such as terms "above", "below", "upper", "lower", etc., or terms indicating directions, such as terms "horizontal", "vertical", etc., are mentioned, unless otherwise specified, they refer to the orientation of the drawing.

[0051] Unless otherwise indicated, the expressions "about", "approximately", "substantially" and "around" mean plus or minus 10%, preferably plus or minus 5%.

[0052] Figure 1 A simplified view of an example of an electronic circuit 100 is shown.

[0053] The circuit 100 includes a memory 120 (flash memory), for example of a non-volatile memory type or a flash memory type, which is able to communicate with, for example, a memory interface 130 (flash memory interface) via a communication bus 110, and the memory interface 130 is configured to write data to the non-volatile memory 120 or read data from the non-volatile memory 120.

[0054] The circuit 100 further comprises, for example, a processing unit 150 (CPU), which comprises one or more processors controlled by instructions stored in an instruction memory 170 (INSTRMEM). The instruction memory 170 is, for example, a volatile memory of the random access memory (RAM) type. The processing unit 150 and the memory 170 communicate, for example, via a system (data, address and control) bus 160. The memory 120 is coupled to the system bus 160 via a non-volatile memory interface 130 and the bus 110. The device 100 further comprises, for example, an input / output interface 140 (I / O interface), which is coupled to the system bus 160 to communicate with the outside.

[0055] The circuit 100 may integrate Figure 1 Other circuits that implement other functions (eg, one or more volatile and / or non-volatile memories, other processing units) that are not shown in the figure. Among these other circuits, the circuit 100 includes, for example, a read-only or static memory.

[0056] Some or all of the different elements 110, 120, 130, 140, 150, 160, 170 may have digital operation. In this case, the clocking of their operation is obtained, for example, by using one or more clock signals forming a sequence of pulses alternating between a high state (1) and a low state (0), for example in the form of square wave pulses.

[0057] The circuit 100 comprises a block 180 for supplying one or more clock signals (CLKS provider). The supply block is coupled to (preferably connected to) one or all of the elements 110, 120, 130, 140, 150, 160, 170, for example.

[0058] Supply block 180 may need to modify the clock signal it supplies to the elements connected thereto, for example using a higher or lower frequency signal. Such modification is performed, for example, by selecting a clock signal from a plurality of clock signals made available by a clock signal generating circuit (not shown).

[0059] Selecting a clock signal from among multiple clock signals requires special care because this can generate glitches if the clock signal to be changed is interrupted at the wrong time, such as when it is in a high state or during a switch from one clock signal to another.

[0060] Figure 2 Very schematically shown Figure 1 More particularly, Figure 2 An example of an implementation of a supply block 180 is illustrated.

[0061] Figure 2 Examples include, for example, first, second, third, and fourth switch circuits 225 that are similar to each other.

[0062] For example, each switch 225 comprises a first block 202 forming a reclocking unit. For example, the first block 202 comprises a first flip-flop 210 and a second flip-flop 220 connected in series, such as a D flip-flop. In an example, these flip-flops form a shift register. In another example, the two flip-flops 210 and 220 are of the rising edge detection type. The first flip-flop 210 comprises a clock input CP, a reset input R and a so-called enable input D. The output of the first flip-flop 210 is coupled to the input of the second flip-flop 220. The clock CP input and the reset R input of the first flip-flop 210 of the switch 225 correspond to the clock input CP and the reset input R of the corresponding switch 225, respectively.

[0063] The clock input terminal CP of each switch 225 is configured to be coupled to a track receiving clock signals C25, CK50, CK100, CK200, which have different frequencies or duty cycles from one switch 225 to another switch 225. In an example, the signal CK25 has a frequency of, for example, 25 MHz, the frequency of the signal CK50 is twice the frequency of the signal CK25, the frequency of the signal CK100 is twice the frequency of the signal CK50, and the frequency of the signal CK200 is twice the frequency of the signal CK100. The D input terminal of each first trigger 210 of each switch 225 is configured to receive corresponding enable signals A_EN_25, A_EN_50, A_EN_100, A_EN_200. The D input terminal of each first trigger 210 corresponds to the enable input terminal D of the corresponding switch 225.

[0064] In the example shown, each switch 225 further includes a second block 230. The Q output of the second flip-flop 220 of each switch 225 is coupled to an enable input E of the second block 230 of the corresponding switch 225. The corresponding enable input E of each second block 230 is configured to receive an enable signal S_EN_25, S_EN_50, S_EN_100, S_EN_200, which corresponds to the output signal on the Q output of the second flip-flop 220 of the corresponding first block 202. In general, the corresponding enable signal is referred to as S_EN_CK, which corresponds to the output signal on the Q output of the second flip-flop 220 of the first block 202 corresponding to the clock signal CK. In the example, the second block 230 is formed with a D flip-flop.

[0065] The second block 230 further includes a clock input terminal CP coupled to a first corresponding rail receiving one of the clock signals CK25, CK50, CK100, CK200. The Q output terminal of the second block 230 is coupled to the output nodes NOUT, NOUT2, NOUT3 and NOUT4 of the corresponding switches 225.

[0066] The switch 225 acts as a clock gating unit via the second block 230 by stopping the propagation of the clock signal to the corresponding output nodes NOUT, NOUT2, NOUT3, NOUT4 only when the clock signal is in a low state to avoid glitches and in the case where the enable signal of the second block 230 is stopped or propagated in synchronization with the clock signal. The first block 202 enables the enable signal of the second block 230 to be stopped or propagated in synchronization with the clock signal.

[0067] In operation, the switch 225 can be in an off state or an on state. In the so-called on state, the switch 225 allows the clock signal received at its clock input terminal CP (in other words, the clock input terminal common to the first flip-flop 210 and the second block) to propagate to its corresponding output nodes NOUT, NOUT2, NOUT3, NOUT4. In the so-called off state, the switch 225 no longer allows the clock signal to propagate to the corresponding output nodes NOUT, NOUT2, NOUT3, NOUT4.

[0068] In the following operation examples, both flip-flops 210 and 220 are of rising edge detection type.

[0069] For the switch 225, in order to switch from the off mode to the on mode, the corresponding enable signals A_EN_25, A_EN_50, A_EN_100, A_EN_200 of the first block are in a low state, and the enable signals S_EN_25, S_EN_50, S_EN_100, S_EN_200 of the second block 230 and the signals on the corresponding output nodes NOUT, NOUT2, NOUT3, NOUT4 are also in a low state. Then, the corresponding enable signals A_EN_25, A_EN_50, A_EN_100, A_EN_200 of the first block rise to a high state. Then, the enable signals S_EN_25, S_EN_50, S_EN_100, S_EN_200 of the second block 230 also rise to a high state after receiving two rising edges (corresponding to the number of flip-flops 210, 220 present) on the clock input. The clock signal propagates to the corresponding output node after receiving the third rising edge at the clock input.

[0070] To switch from the on mode to the off mode, the corresponding enable signals A_EN_25, A_EN_50, A_EN_100, A_EN_200 of the first block are in a high state, and the enable signals S_EN_25, S_EN_50, S_EN_100, S_EN_200 of the second block 230 are also in a high state. In the on mode, the signal propagated on the corresponding output nodes NOUT, NOUT2, NOUT3, NOUT4 is the clock signal received at the clock input. Then, the corresponding enable signals A_EN_25, A_EN_50, A_EN_100, A_EN_200 of the first block fall back to a low state. Then, the enable signals S_EN_25, S_EN_50, S_EN_100, S_EN_200 of the second block 230 fall back to a low state after receiving two rising edges (corresponding to the number of flip-flops 210, 220 present) at the clock input. Then, after receiving the third rising edge at the clock input, the clock signal no longer propagates on the corresponding output node.

[0071] In the example shown, the supply block 180 comprises two logic blocks 240 , 280 which are configured to perform a NOR-type function based on the signals present on the nodes NOUT, NOUT2 and NOUT3 , NOUT4 , respectively.

[0072] In the example shown, the supply block 180 also comprises a logic block 290 configured to perform a NAND-type function based on the signals present at the outputs of the logic blocks 240 and 280 , respectively.

[0073] Depending on the state of the respective enable signal A_EN_25 , A_EN_50 , A_EN_100 , A_EN_200 of each switch 225 , the supply block 180 allows the selection of a clock signal at the output of the logic block 290 from among the possible signals CK25 , CK50 , CK100 and CK200 .

[0074] Figure 2 The fact that the circuit requires as many switches 225 as clock signals to be selected means that the chip surface area and energy consumption are high. For example, in the case of a microcontroller, these two factors are crucial and it is appropriate to limit them while maintaining the glitch filtering capability.

[0075] To this end, the embodiment provides a circuit for supplying a clock signal, comprising:

[0076] A selector for selecting one signal from among a plurality of clock signals;

[0077] a switch between the selector and a node for supplying the selected clock signal,

[0078] The electronic circuit is configured such that application of a control signal for selecting one of the clock signals sequentially results in turning off the switch, selecting the signal via the selector, and turning on the switch.

[0079] The fact that a single switch is provided for all available clock signals makes it possible to improve the chip surface area and also reduce power consumption. The fact that the switch is turned off before selecting the clock signal to be supplied makes it possible to avoid propagating glitches that may be generated when selecting the clock signal. Once a new clock signal has been selected and has therefore stabilized, the switch can be turned on to propagate the selected clock signal.

[0080] Figure 3 Very schematically shows a Figure 1 A block of electronic circuit 100.

[0081] More precisely, Figure 3 An embodiment of a supply block 180 is illustrated.

[0082] exist Figure 3 In the example of FIG. 1 , the supply block 180 includes a selector 320 (MUX) having a switch (e.g., similar to Figure 2 The output terminal of the switch 225 of the selector 320 is configured so that the signal (CK_DIG_RAW) present at the output terminal of the selector 320 is also present at the clock input terminal CP of the switch 225.

[0083] In the example shown, the selector 320 is configured to select one of the clock signals CK50, CK100, CK200 and six other signals (not shown) based on the control signal (MUX_CTRL_FILT<8:0>). The symbol <8:0> is a symbol that concatenates nine different signals and is designated by references 0 to 8. The control signal MUX_CTRL_FILT<8:0> originates from the control unit 330 (CTRL), which generates the original selection control signal (MUX_CTRL<8:0>). The propagation of these original selection control signals MUX_CTRL<8:0> to the selector 320 is controlled by the latch circuit 360 (LATCH STD) according to the state of the signal (CHANGE_DELAYED).

[0084] In the example shown, the supply block 180 includes a circuit 340 (CHANGE DETECT) configured to detect a change in the original selection control signal MUX_CTRL<8:0>. When a change is detected, a signal (CHANGE_PULSE) is, for example, in the form of a pulse.

[0085] Circuit 340 is coupled to (preferably connected to) circuit 310 (DELAY), which is configured to generate a signal (CHANGE_DELAYED) based on signal CHANGE_PULSE and is shifted in time by a first time offset.

[0086] Circuit 310 receives as input a clock signal CK25 having a frequency twice that of the slowest available clock signal (here CK50) or a clock signal having a frequency half that of the slowest clock signal. Circuit 310 is also configured to receive as input a reset signal RESET sent by control unit 330.

[0087] The circuit 310 is configured to deliver a signal (CHANGE) and a signal (CHANGE_DELAYED) as outputs. The signals CHANGE and CHANGE_DELAYED are looped in the circuit 310 so that when there is a positive pulse on the signal CHANGE_PULSE, the signal CHANGE rises, and when the signal CHANGE_DELAYED rises, the signal CHANGE falls. The signal CHANGE_DELAYED corresponds to an image of the signal CHANGE with a time offset of at least two, preferably at least three rising edges of the clock signal CK25 at the input of the circuit 310.

[0088] In the example shown, the D input of switch 225 is coupled (preferably connected) to circuit 310 via logic block 325 which is configured to perform a NOR type function based on signals CHANGE and CHANGE_DELAYED. The output of logic block 325 is enable signal A_EN for first block 202 of switch 225.

[0089] Figure 3 The method of operating the supply circuit 180 includes performing the following consecutive steps as a result of applying the signal selection control signal:

[0090] - turning off the switch 225, which couples the selector 320 that selects a clock signal from a plurality of clock signals and the output node NOUT;

[0091] - selecting a signal via selector 320; and

[0092] - Turn on switch 225.

[0093] In operation, circuit 340 is configured to turn off switch 225 when one or more changes occur in signal MUX_CTRL<8:0>, which generates a pulse on signal CHANGE_PULSE. Circuit 310 receives pulse CHANGE_PULSE, which goes low at its output signal CHANGE, which switches to a low state signal A_EN, which ultimately turns off switch 225.

[0094] The signal CHANGE is looped back in the circuit 310 and becomes the signal CHANGE_DELAYED after at least two clock pulses of the clock signal CK25, whose frequency is two times less than the slowest selectable signal (here CK50). The signal CHANGE_DELAYED is then in a high state, which triggers the locking signal MUX_CTRL<8:0> through the circuit 360, so that they propagate to the selector. The selected clock signal is then delivered to the clock input terminal CP of the switch 225, which is still turned off at this time.

[0095] Signal CHANGE_DELAYED is also looped in circuit 310 , and a rising edge of signal CHANGE_DELAYED resets signal CHANGE to a low state.

[0096] Then, the low state of signal CHANGE propagates to become signal CHANGE_DELAYED after at least two rising edges of clock signal CK25. Signals CHANGE and CHANGE_DELAYED are in the low state, and signal A_EN switches to the high state, which turns on switch 225 and enables signal CK_DIG to propagate on output node NOUT of switch 225, which is the new clock signal that has been selected.

[0097] Figure 4 It shows that according to the embodiment Figure 3 More specifically, Figure 4 An example of a circuit 340 is shown.

[0098] In the illustrated example, the circuit 340 includes nine similar branches that are configured to each receive one of the selection control signals MUX_CTRL<8:0> at a different input node.

[0099] Each branch includes one or more time shift circuits 402, 404, which are connected in series between the corresponding input nodes N0, N1, N2, N3, N4, N5, N6, N7, N8 of the branch that respectively receives one of the signals MUX_CTRL<8:0> and the input terminal of the logic block 410 of the same branch. The other input of the logic block 410 is looped back on the input node of its corresponding branch.

[0100] Each logic block 410 is configured to perform an XOR function based on the signal present at the input node of the corresponding branch and based on the signal that has traveled through the time shift circuit 402, 404. Therefore, the selection control signal MUX_CTRL<8:0> present at the input node of the branch will be processed by the corresponding logic block 410 in its time shifted version. This makes it possible to detect changes that have occurred on the selection control signal MUX_CTRL<8:0> during the time shift introduced by the circuits 402 and 404 (in other words, during the delay period). The number of time shift circuits 402, 404 connected in series in each branch can be greater than two or equal to one. The number of time shift circuits has an impact on the pulse duration of the signal CHANGE_PULSE. Those skilled in the art can adjust this number to ensure that the circuit 310 can operate normally under all conditions of use of the integrated circuit. The output of each logic block 410, respectively denoted as CHG_PULSE<8:0>, is coupled (preferably connected) to a logic block configured to perform a NOR-type function. In the example shown, logic block 450 is configured to perform a NOR function based on signals CHG_PULSE1, CHG_PULSE2, and CHG_PULSE3, logic block 460 is configured to perform a NOR function based on signals CHG_PULSE4, CHG_PULSE5, and CHG_PULSE6, and logic block 480 is configured to perform a NOR function based on signals CHG_PULSE0, CHG_PULSE7, and CHG_PULSE8.

[0101] Circuit 340 also includes a logic block 470 that is configured to perform a NAND-type function based on the outputs of logic blocks 450, 460, and 480. A signal CHANGE_PULSE is generated at the output of logic block 470 that indicates whether a change has occurred in one or more of the select control signals MUX_CTRL<8:0>. In other words, logic blocks 450, 460, 470, and 480 together form an OR-type logic block that combines signals CHG_PULSE<8:0> to generate a pulse on signal CHANGE_PULSE when a change is detected.

[0102] Figure 5 It shows that according to the embodiment Figure 3 More specifically, Figure 5 An embodiment of a circuit 310 is shown.

[0103] In the example shown, the circuit 310 includes a logic block 585 coupled (preferably connected) to the output of the block 470 of the circuit 340. The logic block 585 is configured to perform an AND-type function based on the enable signal ENABLE and the signal CHANGE_PULSE. The output of the logic block 585 is coupled (preferably connected) to the input (e.g., S) of the SR-type latch 502. In other words, when the signal ENABLE is activated, the pulse of the signal CHANGE_PULSE also appears on the S input. Another input (e.g., R input) of the latch 502 is coupled to the output of the shift register 512. The output of the latch 502 is coupled to the input of the shift register 512 via an inverter 535 connected in series with the time shift block 575 (optional). The signal at the output of the inverter 535 is the signal CHANGE.

[0104] In the example shown, the shift register 512 is formed by two flip-flops 565, 555 (e.g., D flip-flops) connected in series. Those skilled in the art can select a shift register having more than two flip-flops connected in series. The D input of the flip-flop 565 is optionally coupled (preferably connected) to the output of the inverter 535 via a time shift block 575. The reset input R of the flip-flop 565 is configured to receive the signal ENABLE_N, and its clock input CP is configured to receive the slowest clock signal, here CK25. The Q output of the flip-flop 555 is coupled to the R input of the latch 502.

[0105] In the example, the latch 502 is formed by two cross-coupled logic gates 525 , 545 , for example of the NOR type, or possibly the NAND type.

[0106] In the example shown, gate 525 includes three inputs, an R input receiving a signal CHANGE_DELAYED from shift register 512, one input configured to receive an enable signal ENABLE_N, and one input coupled to the output of logic gate 545. One input of logic gate 545 includes an S input, and another input of logic gate 545 is coupled to the output of logic gate 525.

[0107] In operation, when the signals on the R and S inputs are in a low state, the output of latch 502 remains stable. If the signal on the S input is a high pulse and the signal on the R input remains low, the output signal changes and then remains therein, including when the signal on the S input returns to a low state. Similarly, if the signal CHANGE_DELAYED is a rising pulse and the signal on the S input remains in a low state, the output signal of latch 502 changes and remains therein, including when the signal CHANGE_DELAYED switches to a low state. Therefore, when there is a positive pulse on the signal CHANGE_PULSE, the signal CHANGE switches to a high state, and when the signal CHANGE_DELAYED switches to a high state, the signal CHANGE switches to a low state. On the other hand, the signal CHANGE_DELAYED is an image of the three rising edges of the signal CHANGE shifted in time by the slowest clock signal (here CK25). Thus, the time shift between the signals CHANGE and CHANGE_DELAYED will enable switch 225 to turn on after the clock signal has been selected and delivered to the output of selector 320, which enables it to exclude glitches that occur during selection.

[0108] The time shift block 575 enables avoiding retention degradation of the output of the latch 502 when the signal CHANGE_DELAYED rises to a high state, which may generate a falling edge on the signal CHANGE.

[0109] Figure 6 It shows that according to the embodiment Figure 3 More specifically, Figure 6 An embodiment of a circuit 360 is shown.

[0110] In the example shown, circuit 360 includes a single illustrated branch. Other branches corresponding to the processing of all signals MUX_CTRL<8:0> are not shown, but are similar. Circuit 360 includes a logic block 610, which is configured to perform an OR-type function based on the signal CHANGE_DELAYED and the enable signal ENABLE_N. Each branch includes a latch 620. The output terminal LATCH of the logic block 610 is coupled to the control input terminal G of each latch 620 (LATCH). Therefore, the signal LATCH arrives at the G input terminal of the latch 620 of each branch. The D input terminal of the latch 620 is configured to receive one of the corresponding selection control signals MUX_CTRL<8:0>. Once propagated on the Q output terminal of the latch 620, the signal MUX_CTRL<8:0> becomes the signal MUX_CTRL_FILT<8:0>. Therefore, the signal LATCH corresponding to the propagation signal CHANGE_DELAYED controls the propagation of the original selection control signal MUX_CTRL<8:0> before it propagates to the selector 320. The signal LATCH is preferably at a high level only when the clock signal CK_DIG_RAW at the output of the selector 320 is at a low state, otherwise there may be parasitic pulses.

[0111] In the example, latch 620 is replaced by a D flip-flop (which basically consists of two latches in series), which is more secure but takes up twice as much space as a simple latch.

[0112] Figure 7 It shows that according to the embodiment Figure 3 More specifically, Figure 7 An embodiment of a selector 320 is shown.

[0113] In the example shown, circuit 320 includes four logic blocks 710, 712, 714, 716, which are configured to perform OR-type functions based on signals MUX_CTRL_FILT4, CK200; MUX_CTRL_FILT3, CK100; MUX_CTRL_FILT2, CK50; MUX_CTRL_FILT1, CK150, respectively; signal CK150 is, for example, a clock signal having a frequency between the frequencies of signals CK100 and CK200.

[0114] In the example shown, the circuit 320 also includes two logic blocks 718 , 720 that are configured to perform a NOR function based on the outputs of the logic blocks 714 , 716 and 710 , 712 , respectively.

[0115] Circuit 320 also includes logic block 730 that is configured to perform a NAND function based on the outputs of logic blocks 718 and 720. The combination of logic blocks 718, 720, and 730 enables an OR-type logic function to be performed based on the outputs of logic blocks 710, 712, 714, and 716. The output signal of block 730 is the selected clock signal CK_DIG_RAW before it travels through switch 225.

[0116] In the example shown, only four logic blocks 710, 712, 714, 716 are shown, however, Figure 7 The architecture shown in can be replicated so that the selection of the clock signal is performed based on a greater number of available clock signals.

[0117] In order to select a single clock signal at a time, the signal MUX_CTRL_FILT<8:0> is preferably exclusive.When one of the signals MUX_CTRL_FILT<8:0> is at a high level, then the clock signal present on the other input of the logic blocks 710, 712, 714, 716 is propagated to the output of the selector 320 and becomes the signal CK_DIG_RAW.

[0118] Figure 8 yes Figure 3 More specifically, Figure 8 The time variations of signals CK100, CK50, CK_DIG_RAW, CK_DIG, MUX_CTRL, MUX_CTRL_FILT, CHANGE_PULSE, A_EN, S_EN_CK, EN_CK50, EN_CK100, RESET, CHANGE, CHANGE_DELAYED, LATCH, and CK25 are shown. In the example shown, signal MUX_CTRL is a selection control signal among signals MUX_CTRL<8:0>, which controls the selection of signal CK100.

[0119] The example shown illustrates Figure 3 Selection and transmission from signal CK50 to signal CK100 at node NOUT.

[0120] Between time t1 and time t7 , signals CK25 , CK50 , and CK100 are alternately in high and low states, with a duty cycle close to or equal to 50%, and the frequency of CK100 is twice that of CK50 and four times that of CK25 .

[0121] Between time t1 and time t3 before time t7 , the signal CK_DIG_RAW selected and propagated by the selector 320 is the signal CK50 .

[0122] At time t1, circuit 340 detects a change in the selection control signal MUX_CTRL<8:0>, and the signal MUX_CTRL switches from a low level to a high level and then remains stable at a high level. A pulse is then generated on the signal CHANGE_PULSE, which causes the signal A_EN to switch from a high state to a low state, and after the rising edge of the clock signal CK25, at time t2 before time t3, the second block 230 of the switch 225 switches from a high state to a low state and interrupts the propagation of the signal CK50. The output signal CK_DIG then becomes zero or stabilizes at a low state.

[0123] At time t1, a positive pulse is sent on signal RESET, which resets latch 502 of circuit 310, and signal CHANGE switches from a low state to a high state and then remains stable. At the end of the pulse of signal CHANGE_PULSE and the third rising edge of clock signal CK25 after this reset, i.e., at time t3, signal CHANGE_DELAYED switches from a low state to a high state.

[0124] Circuit 360 blocks modification of signal MUX_CTRL between time t1 and time t3. At time t3, signal LATCH and signal EN_CK100 are switched from low state to high state, which enables propagation of selection control signal MUX_CTRL through corresponding latches. At time t3, signal EN_CK50 is switched from high state to low state to stop selection of signal CK50. Clock signal CK100 is selected by selector 320 and forms signal CK_DIG_RAW. However, this clock signal change has caused a glitch (designated as GLITCH in the timing diagram). However, since switch 225 is turned off at this stage, the glitch is not propagated.

[0125] At time t3, SR latch 502 is reset by the rise of signal CHANGE_DELAYED, and signal CHANGE switches from high state to low state. The state of signal CHANGE propagates to the state of signal CHANGE_DELAYED at the third rising edge of clock signal CK25 at time t4 after t3.

[0126] At time t4, the signal CHANGE_DELAYED switches from a high state to a low state, and thus the signal LATCH is also the same. The signal A_EN switches from a low state to a high state, and after the next two rising edges of the clock signal CK100, at time t5, the signal S_EN_CK switches from a low state to a high state. Then, after the next rising edge of the signal CK100, the second block 230 of the switch 225 implements the propagation of the signal CK100 on the output node NOUT of the switch 225, and the signal CK_DIG then becomes the signal CK100.

[0127] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art. In particular, the number of flip-flops in series of the block 202 of switches may be greater than two, and the type of flip-flop of the block may be different from a D flip-flop.

[0128] In another example, the shift register 512 may be replaced by a re-clocking unit of the same type as block 202. This enables a reduction in the jitter risk associated with potential desynchronization of the selection control signal and the clock signal used as the clock input of the shift register.

[0129] In general, the example of circuit 310 shows an example of generating a time shift between turning off switch 225 and selecting a new clock signal, and then also between selecting a clock signal and turning on switch 225. Those skilled in the art can apply their knowledge to perform such a time shift using other circuit architectures, as long as the time shift is at least three, preferably four, rising edges of a clock signal (CK25) that has a frequency that is two times lower than the slowest clock signal (CK50) to be selected.

[0130] Figure 7 An example of the selector 320 is disclosed in , however, those skilled in the art can use their knowledge to implement a circuit that selects one signal from a plurality of signals based on a selection control signal. Such a circuit is, for example, a multiplexer (MUX).

[0131] Finally, based on the functional indications given above, the practical implementation of the described embodiments and variants is within the capabilities of a person skilled in the art. In particular, with regard to the switch 225, they may, for example, only include the second block 230, without the first block 202, as long as the clock signal is stopped from propagating on the output node NOUT only when the clock signal is in a low state to avoid glitches, and the enable signal S_EN_CK of the second block 230 is synchronized with the clock signal to be stopped or propagated.

[0132] A supply circuit 180 such as described above may be integrated in, for example, a low power microcontroller.

Claims

1. A circuit for supplying a clock signal, comprising: A selector, used to select a signal from multiple clock signals; a switch located between the selector and a node for outputting the selected clock signal; The circuit is configured such that application of a selection control signal for selecting one of the clock signals sequentially results in turning off the switch, selecting one of the plurality of clock signals via the selector, and turning on the switch.

2. The circuit of claim 1, wherein the circuit is further configured to turn off the switch upon detecting a change in the selection control signal.

3. The circuit of claim 2, wherein the circuit is further configured to select the signal after a first delay of at least two rising edges of the shift signal after the change is detected. 4 . The circuit of claim 3 , wherein the circuit is further configured to, after the selecting, turn on the switch after a second delay of at least two rising edges of the shift signal.

5. The circuit of claim 2, wherein the circuit is further configured to generate a first signal using the first circuit when a change is detected.

6. The circuit of claim 3, wherein the circuit is further configured to generate a second signal using a second circuit, the second signal being derived from the first signal and time-shifted by the first delay.

7. The circuit of claim 6, wherein the second circuit comprises: An SR type latch having an output terminal coupled to an inverter connected in series with an input terminal of a shift register including at least two stages and / or delay units; wherein a second signal is generated at an output of the shift register; and A first input terminal of the SR-type latch is configured to receive a first signal, and a second input terminal of the SR-type latch is configured to receive a second signal.

8. The circuit of claim 1 , comprising a third circuit configured to propagate a selection control signal to a signal selector according to an output authorization of the first logic block, the first logic block being capable of performing a NOR function based on a signal present at an output terminal of the inverter and a second signal.

9. The circuit of claim 8, wherein the third circuit comprises a latch for each control signal forming a selection control signal, each latch having: a gate input terminal coupled to the output terminal of the first logic block; A data input terminal configured to receive a corresponding control signal; and Coupled to the output terminal of the signal selector.

10. The circuit of claim 3, wherein the shift signal is a clock signal having a frequency less than or equal to a frequency of a signal having a smallest frequency among the plurality of clock signals.

11. The circuit of claim 8, wherein the switch comprises a first block comprising: coupled to a clock input terminal of the selector; a first enable input terminal coupled to the output terminal of the first logic block; an output terminal coupled to a second enable input terminal of a second block of the switch; and An output terminal of the second block of switches is coupled to the output node, and a clock input terminal of the second block is coupled to the output terminal of the selector.

12. The circuit of claim 8, wherein the switch is configured to be turned off when the output of the first logic block is at a low level.

13. The circuit of claim 1, wherein when the output of the first logic block is at a high level, the switch is configured to be turned on, and the selected clock signal then also appears at the output node.

14. The circuit of claim 11, wherein the first block of the switch comprises a first flip-flop and a second flip-flop connected in series, the clock input of the first block is the clock input of the first flip-flop, and the output of the second flip-flop is coupled to the second enable input of the second block.

15. A method of operating a circuit for supplying a clock signal, the method comprising successively performing the following as a result of applying a selection control signal for selecting a signal: a turn-off switch coupled to a selector that selects a clock signal from a plurality of clock signals and the output node; selecting a signal via a selector; and Turn on the switch.

16. The method of claim 15, further comprising turning off the switch when a change in the select control signal is detected.

17. The method of claim 16, further comprising selecting the signal after a first delay of at least two rising edges of the shift signal after detecting the change. 18 . The method of claim 17 , further comprising turning on the switch after a second delay of at least two rising edges of the shift signal after the signal is selected via the selector.

19. The method of claim 16, further comprising generating a first signal using a first circuit when a change is detected.

20. A microcontroller comprising the circuit for supplying a clock signal according to claim 1.

Images