Full CMOS reset circuit and working method thereof
By designing a full CMOS reset circuit, combining the bias module, comparator module, hysteresis generation module and output module, the problem of the reset circuit being difficult to take into account low power consumption and reducing the layout area, achieving the effects of low power consumption, low cost and long standby time.
Patent Information
- Application Number
- CN202411771261.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-04
- Publication Date
- 2025-03-28
AI Technical Summary
The reset circuit design of existing integrated circuits is difficult to take into account low power consumption and reduced layout area, resulting in a shorter system standby time and increased cost.
A full CMOS reset circuit is designed. Through the combination of bias module, comparator module, hysteresis generation module and output module, the detection of power supply voltage and the output signal output are realized, avoiding the use of large resistance resistors, thereby reducing the circuit layout area and power consumption.
The same reset effect on digital circuits as existing designs is achieved, while reducing circuit layout area, reducing chip cost, and extending the standby time of the system.
Smart Images
Figure CN119727686A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of integrated circuit design, and in particular to a full CMOS reset circuit and a working method thereof. Background Art
[0002] The power-on reset circuit is an essential functional module in various chip systems. Its purpose is to detect the voltage stability of the chip power supply voltage during power on and power off, and then generate a POR enable signal to determine whether the chip can start or stop working.
[0003] Many integrated circuits today are used in portable devices, powered by batteries, and power consumption will affect the working time of the system. Therefore, the power consumption needs to be as low as possible in the system standby state, and the reset circuit must be turned on when the system is in standby, so its power consumption has a great impact on the overall standby power consumption. In order to reduce power consumption, the traditional reset circuit needs to use a resistor with a large resistance value. As the integrated circuit process develops towards advanced processes, although the size of transistors is getting smaller and smaller, the size of resistors cannot be reduced synchronously. Therefore, if the traditional reset circuit uses a resistor with a large resistance value to reduce power consumption, the circuit structure will occupy a large layout area. And as the proportion of the layout area of large resistance resistors in the overall circuit layout increases, packaging and cost will also be limited. If it is necessary to minimize the circuit layout area, a resistor with a large resistance value cannot be used. In the case where a resistor with a large resistance value cannot be used, the power consumption of the reset circuit will increase, affecting the overall power consumption of the system. It can be seen that in the existing integrated circuit architecture, it is difficult to balance low power consumption and reduced layout area in the reset circuit design.
[0004] Therefore, providing a reset circuit and method that can reduce the layout area of circuit design and reduce power consumption is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention
[0005] In order to solve the above technical problems, the present disclosure provides a full CMOS reset circuit to solve the problem that the power-on reset circuit in the existing integrated circuit structure cannot take into account both low power consumption and reduced layout area.
[0006] The present disclosure provides a full CMOS reset circuit, comprising a bias module, a comparator module, a hysteresis generation module and an output module which are electrically connected; wherein:
[0007] The output end of the bias module is electrically connected to the input end of the comparator module, and the bias module is used to generate a bias voltage for use by the comparator module;
[0008] The comparator module is used to compare whether the power supply voltage provided by the power supply terminal exceeds the bias voltage, and feed back the comparison result to the input terminal of the hysteresis generation module;
[0009] The hysteresis generation module is used to realize the hysteresis of the power-down reset voltage during the power-down reset process of the full CMOS reset circuit, so that the power-down reset voltage is lower than the power-on reset voltage;
[0010] The output terminal of the output module is used to output a reset signal;
[0011] The bias module only includes multiple electrically connected PMOS tubes and NMOS tubes, the comparator module only includes multiple electrically connected PMOS tubes and NMOS tubes, the hysteresis generation module only includes multiple electrically connected PMOS tubes, a first inverter and a first buffer, and the output module includes an electrically connected second inverter and a second buffer.
[0012] Optionally, the bias module includes a first PMOS tube and a first NMOS tube, the comparator module includes a second PMOS tube, a third PMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube, the hysteresis generation module includes a fourth PMOS tube, a fifth PMOS tube, a first buffer and a first inverter, and the output module includes a second inverter and a second buffer;
[0013] The sources of the first PMOS tube, the second PMOS tube, the third PMOS tube, and the fourth PMOS tube are all electrically connected to the power supply terminal, and the gate of the first PMOS tube, the sources of the first NMOS tube, and the second NMOS tube are all grounded;
[0014] The drain of the first PMOS tube is electrically connected to the gate and drain of the first NMOS tube, the gate of the second NMOS tube, and the gate of the fourth NMOS tube respectively; the drain of the second NMOS tube is electrically connected to the source of the third NMOS tube and the source of the fourth NMOS tube respectively; the gate and drain of the second PMOS tube are electrically connected, and are electrically connected to the gate of the third PMOS tube, the gate of the fifth PMOS tube, and the gate and drain of the third NMOS tube respectively; the drain of the third PMOS tube is electrically connected to the drain of the fourth NMOS tube, the drain of the fifth PMOS tube, and the input end of the first inverter respectively; the drain of the fourth PMOS tube is electrically connected to the source of the fifth PMOS tube, and the output end of the first inverter is electrically connected to the input end of the second inverter and the input end of the first buffer respectively; the output end of the first buffer is electrically connected to the gate of the fourth PMOS tube, the output end of the second inverter is electrically connected to the input end of the second buffer, and the output end of the second buffer outputs a reset signal.
[0015] Further optionally, the output module also includes a delay structure, and the delay structure is electrically connected to the output end of the second inverter.
[0016] Further optionally, the delay structure includes a fifth NMOS tube, a gate of the fifth NMOS tube is electrically connected to the output end of the second inverter, and a source and a drain of the fifth NMOS tube are both grounded.
[0017] Optionally, the width of the first PMOS tube is W P1 , the length of the first PMOS tube is L P1 , where L P1 >W P1 .
[0018] Optionally, the width of the first NMOS tube is twice the width of the second NMOS tube, and the length of the first NMOS tube is the same as the length of the second NMOS tube.
[0019] Optionally, the width-to-length ratio of the second PMOS tube is the same as the width-to-length ratio of the third PMOS tube.
[0020] Optionally, the width-to-length ratio of the third NMOS tube is the same as the width-to-length ratio of the fourth NMOS tube.
[0021] Based on the same inventive concept, the present disclosure also provides a working method of a full CMOS reset circuit, which is used for the above-mentioned full CMOS reset circuit; the working method comprises:
[0022] The power supply terminal provides power supply voltage, and the power supply voltage starts to rise from zero. During the power supply voltage rising process:
[0023] When the power supply voltage is lower than the turn-on voltage of the first PMOS tube in the bias module, the gate voltage of the output end of the bias module, i.e., the first NMOS tube, is zero, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the second PMOS tube, and the third PMOS tube in the comparator module are in the cut-off state, and the output end of the comparator module maintains the output low level. After passing through the first inverter of the hysteresis generation module, the second inverter of the output module, and the second buffer, the reset signal output by the output module is low level;
[0024] When the power supply voltage is higher than the turn-on voltage of the first PMOS tube in the bias module:
[0025] If the gate potential of the third NMOS tube in the comparator module is lower than the gate potential of the fourth NMOS tube, the output end of the comparator module maintains the output low level, and the reset signal output by the output module is still at a low level;
[0026] If the gate potential of the third NMOS tube in the comparator module is higher than the gate potential of the fourth NMOS tube, the output end of the comparator module outputs a high level, and after passing through the first inverter of the hysteresis generation module, the second inverter of the output module, and the second buffer, the reset signal output by the output module is a high level; at this time, the value of the power supply voltage is the power-on reset voltage;
[0027] After the power-on reset is completed, the power-off reset process begins, the output end of the comparator module outputs a high level, and after passing through the first inverter and the first buffer of the hysteresis generation module, the output end of the first buffer outputs a low level, and the fourth PMOS tube is turned on;
[0028] The output end of the comparator module re-outputs a low level, and after passing through the first inverter of the hysteresis generation module, the second inverter of the output module, and the second buffer, the reset signal output by the output module is a low level; at this time, the value of the power supply voltage is the power-off reset voltage, and the value of the power-off reset voltage is lower than the value of the power-on reset voltage.
[0029] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:
[0030] The full CMOS reset circuit provided by the present invention can be used in the architecture of integrated circuits and is responsible for detecting the power supply voltage at the power supply end. When the power supply voltage is lower than the lowest operable voltage of the digital circuit, the output module outputs a valid reset signal to reset the digital circuit; after the power supply voltage rises above the power-on reset voltage, the output module outputs a non-valid reset signal, and the digital circuit enters a normal working mode; after the power supply voltage drops to the power-off reset voltage, the output module outputs a valid reset signal again, and the digital circuit enters a reset state and stops normal working. In addition, the circuit structure of the bias module in the full CMOS reset circuit disclosed in the present invention only includes a plurality of electrically connected PMOS tubes and NMOS tubes, the circuit structure of the comparator module also only includes a plurality of electrically connected PMOS tubes and NMOS tubes, the circuit structure of the hysteresis generation module also only includes an electrically connected PMOS tube, a first inverter and a first buffer, and the circuit structure of the output module includes an electrically connected second inverter and a second buffer, which can achieve the same reset effect on the digital circuit as the existing design, and can also make the reset circuit structure only include CMOS tubes and the matching structure of the inverter and the buffer. Since the entire circuit structure does not use large-sized electronic components such as resistors that require a large area of layout, the circuit layout area can be reduced, thereby reducing the chip cost, and is more suitable for the current advanced process technology. In addition, large-sized electronic components such as resistors that require a large area of layout are not used, and CMOS tube design is adopted. The circuit of the CMOS tube has the characteristics of low power consumption, high integration, high speed and high reliability, thereby making the power consumption of the entire reset circuit lower, and can extend the standby time of the chip system. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0033] Figure 1 It is a schematic diagram of the module electrical connection structure of a full CMOS reset circuit provided by an embodiment of the present disclosure;
[0034] Figure 2 yes Figure 1 A schematic diagram of an electrical connection structure of each module;
[0035] Figure 3 yes Figure 1 Another schematic diagram of the electrical connection structure of each module;
[0036] Figure 4 yes Figure 3 A schematic diagram showing how the node PORB of the reset circuit in FIG. 1 changes with the power supply voltage at the power supply end obtained through simulation. DETAILED DESCRIPTION
[0037] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.
[0038] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.
[0039] Please refer to Figure 1 , Figure 1 is a schematic diagram of the module electrical connection structure of a full CMOS reset circuit provided in an embodiment of the present disclosure. This embodiment provides a full CMOS reset circuit 000, including an electrically connected bias module 10, a comparator module 20, a hysteresis generation module 30 and an output module 40; wherein,
[0040] The output end of the bias module 10 is electrically connected to the input end of the comparator module 20, and the bias module 10 is used to generate a bias voltage for use by the comparator module 20; it can be understood that in this embodiment, the output end of the bias module 10 is defined as a node BIAS;
[0041] The comparator module 20 is used to compare whether the power supply voltage provided by the power supply terminal VDD exceeds the bias voltage, and feed back the comparison result to the input terminal of the hysteresis generation module 30; it can be understood that in this embodiment, the output terminal of the comparator module 20, i.e., the comparison result feedback terminal, is defined as the node COUT;
[0042] The hysteresis generating module 30 is used to realize the hysteresis of the power-down reset voltage during the power-down reset process of the full CMOS reset circuit 000, so that the power-down reset voltage is lower than the power-on reset voltage;
[0043] The output end of the output module 40 is used to output a reset signal; it can be understood that the output end of the output module 40 in this embodiment is used to output a reset enable signal of a digital circuit electrically connected thereto, so the output end of the output module 40 can be defined as a node PORB in this embodiment.
[0044] The reset circuit designed in this embodiment can be used in the architecture of an integrated circuit. The reset circuit is responsible for detecting the power supply voltage of the power supply terminal VDD. When the power supply voltage is lower than the lowest operable voltage of the digital circuit, the output module 40 outputs a valid reset signal to reset the digital circuit; after the power supply voltage rises to above the power-on reset voltage, the output module 40 outputs a non-valid reset signal, and the digital circuit enters a normal working mode; after the power supply voltage drops to the power-off reset voltage, the output module 40 outputs a valid reset signal again, and the digital circuit enters a reset state and stops normal operation. Generally, there will be disturbances on the power supply voltage. After the power supply voltage rises to above the power-on reset voltage, it falls below the power-on reset voltage due to the disturbance, and the reset signal is prone to pulse glitches, which will affect the normal operation of the digital circuit. Therefore, the hysteresis generating module 30 provided in this embodiment is used to realize the hysteresis of the power-off reset voltage during the power-off reset process of the reset circuit, so that the power-off reset voltage is lower than the power-on reset voltage to ensure that there are no pulse glitches on the reset signal. The difference between the power-on reset voltage and the power-off reset voltage is called the hysteresis voltage.
[0045] The reset circuit designed in this embodiment is a full CMOS reset circuit. Specifically, Figure 2 As shown, Figure 2 yes Figure 1A schematic diagram of an electrical connection structure of each module in the embodiment of the present invention is shown in FIG. 1 , wherein the circuit structure of the bias module 10 only includes a plurality of electrically connected PMOS tubes and NMOS tubes, the circuit structure of the comparator module 20 also only includes a plurality of electrically connected PMOS tubes and NMOS tubes, the circuit structure of the hysteresis generating module 30 also only includes an electrically connected PMOS tube, a first inverter I1 and a first buffer B1, and the circuit structure of the output module 40 includes an electrically connected second inverter I2 and a second buffer B2. It can be seen that the reset circuit provided in this embodiment can achieve the same reset effect on the digital circuit as the existing design through the electrical connection of the bias module 10, the comparator module 20, the hysteresis generating module 30 and the output module 40. In addition, the reset circuit structure composed of the bias module 10, the comparator module 20, the hysteresis generating module 30 and the output module 40 in this embodiment only includes the electrical connection of the CMOS tube, and the matching structure of the inverter and the buffer, so as to achieve the reset effect on the digital circuit. Since the entire circuit structure does not use large-sized electronic components such as resistors that require a large area of layout, the circuit layout area can be reduced, thereby reducing the chip cost, which is more suitable for the current advanced process technology, and does not use large-sized electronic components such as resistors that require a large area of layout. CMOS tube design is adopted. The circuit of the CMOS tube has the characteristics of low power consumption, high integration, high speed and high reliability, thereby making the power consumption of the entire reset circuit lower and extending the standby time of the chip system.
[0046] In some optional embodiments, such as Figure 2 As shown, this embodiment provides an electrical connection structure of a full CMOS reset circuit 000, the bias module 10 includes a first PMOS transistor P1 and a first NMOS transistor N1, the comparator module 20 includes a second PMOS transistor P2, a third PMOS transistor P3, a second NMOS transistor N2, a third NMOS transistor N3 and a fourth NMOS transistor N4, the hysteresis generation module 30 includes a fourth PMOS transistor P4, a fifth PMOS transistor P5, a first buffer B1 and a first inverter I1, and the output module 40 includes a second inverter I2 and a second buffer B2;
[0047] Specifically, the sources of the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, and the fourth PMOS transistor P4 are all electrically connected to the power supply terminal VDD, and the gate of the first PMOS transistor P1, the sources of the first NMOS transistor N1, and the second NMOS transistor N2 are all connected to the ground GND;
[0048] The drain of the first PMOS tube P1 is electrically connected to the gate and drain of the first NMOS tube N1, the gate of the second NMOS tube N2, and the gate of the fourth NMOS tube N4; the drain of the second NMOS tube N2 is electrically connected to the source of the third NMOS tube N3 and the source of the fourth NMOS tube N4; the gate and drain of the second PMOS tube P2 are electrically connected, and are electrically connected to the gate of the third PMOS tube P3, the gate of the fifth PMOS tube P5, and the gate and drain of the third NMOS tube N3; the drain of the third PMOS tube P3 is electrically connected to the drain of the fourth NMOS tube N4, the drain of the fifth PMOS tube P5, and the ... 5 is electrically connected to the drain of the fourth PMOS tube P4 and the input end of the first inverter I1; the drain of the fourth PMOS tube P4 is electrically connected to the source of the fifth PMOS tube P5, and the output end of the first inverter I1 is electrically connected to the input end of the second inverter I2 and the input end of the first buffer B1 respectively, that is, the first inverter I1 and the second inverter I2 are cascaded; the output end of the first buffer B1 is electrically connected to the gate of the fourth PMOS tube P4, the output end of the second inverter I2 is electrically connected to the input end of the second buffer B2, and the output end of the second buffer B2 (that is, the output end of the output module 40, that is, the node PORB) outputs a reset signal.
[0049] The structure of the full CMOS reset circuit 000 of the present embodiment allows the entire circuit design to avoid the use of large-sized electronic components such as resistors that require a large layout area, thereby reducing the circuit layout area, reducing chip costs, and having lower power consumption. While being able to extend the standby time of the chip system, it can also achieve the same reset effect on the digital circuit as the prior art.
[0050] Optional, such as Figure 1 and Figure 3 As shown, Figure 3 yes Figure 1 1 is another schematic diagram of the electrical connection structure of each module in the embodiment. The output module 40 in this embodiment further includes a delay structure 401, and the delay structure 401 is electrically connected to the output end of the second inverter I2.
[0051] The delay structure 401 includes a fifth NMOS transistor N5 , a gate of the fifth NMOS transistor N5 is electrically connected to the output end of the second inverter I2 , and a source and a drain of the fifth NMOS transistor N5 are both grounded GND.
[0052] Since the output end of the first inverter I1 in the hysteresis generation module 30 is electrically connected to the input end of the first buffer B1, and no other devices are connected to the path of the second inverter I2, the delay is very small, which is not conducive to the reset signal output by the node PORB meeting the pulse width requirement of the digital circuit reset. Therefore, a delay structure 401 made of a fifth NMOS tube N5 is arranged between the output end of the second inverter I2 and the input end of the second buffer B2, which can not only ensure that the entire circuit is a full CMOS design, but also generate a certain delay when the power supply voltage is quickly powered on, so that the reset signal output by the output end of the second inverter I2 does not jump immediately after the power supply voltage rises to the power-on reset voltage, but jumps after a delay for a period of time, and after the delay, the waveform of the reset signal output by the output end of the second inverter I2 has a certain slope, which is not conducive to clearing the subsequent digital circuit (because the reset signal output by the final node PORB is used to clear the subsequent digital circuit). Therefore, in this embodiment, a second buffer B2 is further provided between the output end of the output module 40 and the output end of the second inverter I2. The second buffer B2 makes the waveform slope of the reset signal outputted from the final node PORB steeper, so that the digital circuit can be reset normally.
[0053] This embodiment explains that a delay structure 401 may also be provided at the output end of the second inverter I2. The delay structure 401 is also made of CMOS tubes. For example, the delay structure 401 includes a fifth NMOS tube N5. The gate of the fifth NMOS tube N5 is electrically connected to the output end of the second inverter I2. The source and drain of the fifth NMOS tube N5 are both grounded GND. The fifth NMOS tube N5 has the same function as the delay capacitor, which is to increase the delay of the output signal when the power supply voltage is quickly powered on, so that the pulse width of the reset signal outputted from the output end of the output module 40, i.e., the node PORB, meets the timing requirement of resetting the digital circuit.
[0054] For the on and off conditions of CMOS tubes, the on condition of NMOS tubes is its V G -V S >V thn (V thn The turn-on voltage of the NMOS tube is also called the threshold voltage. The V thn There are differences, but they are all positive; V G is the gate voltage, V S is the source voltage), the conduction condition of the PMOS tube is V G -V S <V thp (V thp The turn-on voltage of the PMOS tube is also called the threshold voltage. The V thpThere are differences, but they are all negative values). When the NMOS tube and PMOS do not meet the conduction conditions, they are not turned on and the current cannot flow through, which is equivalent to being understood as the tube being disconnected.
[0055] In some optional embodiments, please continue to refer to Figure 3 This embodiment provides a method for Figure 3 The working method of the full CMOS reset circuit 000 shown in the embodiment includes:
[0056] The power supply terminal VDD provides the power supply voltage, and the power supply voltage starts to rise from zero. During the power supply voltage rising process:
[0057] When the power supply voltage is lower than the turn-on voltage of the first PMOS transistor P1 in the bias module 10, the gate voltage of the first NMOS transistor N1, which is the output end of the bias module 10, is zero, the second NMOS transistor N2, the third NMOS transistor N4, the second PMOS transistor P2, and the third PMOS transistor P3 in the comparator module 20 are in the cut-off state, and the output end of the comparator module 20 maintains the output low level. After passing through the first inverter I1 of the hysteresis generation module 30, the second inverter I2 of the output module 40, and the second buffer B2, the reset signal output by the output module 40 is low level;
[0058] When the power supply voltage is higher than the turn-on voltage of the first PMOS tube P1 in the bias module 10:
[0059] If the gate potential of the third NMOS transistor N3 in the comparator module 20 is lower than the gate potential of the fourth NMOS transistor N4, the output terminal of the comparator module 20 maintains the output low level, and the reset signal output by the output module 40 is still at a low level;
[0060] If the gate potential of the third NMOS transistor N3 in the comparator module 20 is higher than the gate potential of the fourth NMOS transistor N4, the output end of the comparator module 20 outputs a high level. After passing through the first inverter I1 of the hysteresis generation module 30, the second inverter I2 of the output module 40, and the second buffer B2, the reset signal output by the output module 40 is a high level. At this time, the value of the power supply voltage is the power-on reset voltage.
[0061] After the power-on reset is completed, the power-off reset process begins, the output end of the comparator module 20 outputs a high level, and after passing through the first inverter I1 and the first buffer B1 of the hysteresis generation module 30, the output end of the first buffer B1 outputs a low level, and the fourth PMOS tube P4 is turned on;
[0062] The output end of the comparator module 20 re-outputs a low level, and after passing through the first inverter I1 of the hysteresis generation module 30, the second inverter I2 of the output module 40, and the second buffer B2, the reset signal output by the output module 40 is a low level; at this time, the value of the power supply voltage is the power-off reset voltage, and the value of the power-off reset voltage is lower than the value of the power-on reset voltage.
[0063] like Figure 3 As shown, the working process of the full CMOS reset circuit 000 provided in this embodiment can be:
[0064] During the power-on reset process, the power supply voltage provided by the power supply terminal VDD starts to rise from zero. When the power supply voltage is lower than the turn-on voltage of the first PMOS tube P1 in the bias module 10, the voltage V BIAS =0, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, the second PMOS transistor P2, and the third PMOS transistor P3 in the comparator module 20 are all in the cut-off state, and the voltage V COUT Maintaining a low level, after passing through the cascaded first inverter I1, the second inverter I2, and the second buffer B2, the output end of the output module 40, namely the node PORB, outputs a low level.
[0065] Optionally, in this embodiment, the width of the first PMOS tube P1 is set to W P1 , the length of the first PMOS tube P1 is L P1 , where L P1 >W P1 The length of the first PMOS tube P1 is greater than its width, and the width-to-length ratio of the first PMOS tube P1 is less than 1. The smaller the width-to-length ratio, the greater the channel resistance of the PMOS tube, and the smaller the current of the PMOS tube. Therefore, the current of the bias module 10 is reduced, which is beneficial to reducing the overall power consumption of the reset circuit of this embodiment.
[0066] When the power supply voltage provided by the power supply terminal VDD continues to rise and the value of the power supply voltage is higher than the turn-on voltage of the first PMOS transistor P1 in the bias module 10, the current flowing through the first PMOS transistor P1 is Where W P1 is the width of the first PMOS tube P1, L P1 is the length of the first PMOS tube P1, V thp is the threshold voltage of the PMOS tube in the process, μ is the electron mobility, and COX is the gate oxide capacitance per unit area (the definitions of μ and COX will not be repeated later).
[0067] Since the first PMOS transistor P1 is connected in series with the first NMOS transistor N1, the current I flowing through the first NMOS transistor N1 N1It is also equal to the current I flowing through the first PMOS tube P1 P1 , then the voltage of the gate and drain of the first NMOS tube N1 is also the voltage at the node BIAS Where W N1 is the width of the first NMOS tube N1, L N1 is the length of the first NMOS tube N1, V thn is the threshold voltage of the NMOS transistor in the process.
[0068] Optionally, in this embodiment, the width W of the first NMOS transistor N1 is set to N1 is the width W of the second NMOS transistor N2 N2 twice the length L of the first NMOS tube N1 N1 The length L of the second NMOS tube N2 N2 The same, then the current I flowing through the second NMOS tube N2 N2 is the current I flowing through the first NMOS tube N1 N1 twice, that is, the current I flowing through the second NMOS tube N2 in the comparator module 20 N2 =2I P1 .
[0069] Optionally, in this embodiment, the width-to-length ratio of the second PMOS tube P2 is set to be the same as the width-to-length ratio of the third PMOS tube P3, that is, the sizes of the two are the same, then the current I flowing through the second PMOS tube P2 is P2 Equal to the current I flowing through the third PMOS tube P2 P3 ,Right now
[0070] like Figure 3 As shown, at this time, the voltage of the node VDET in the comparator module 20 is Where W P2 is the width of the second PMOS tube P2, L P2 is the length of the second PMOS transistor P2.
[0071] The third NMOS transistor N3 and the fourth NMOS transistor N4 in the comparator module 20 are differential input structures. The width-to-length ratio of the third NMOS transistor N3 is the same as that of the fourth NMOS transistor N4, and the sizes are consistent. If the gate voltage of the third NMOS transistor N3 (that is, the voltage V DET ) and the gate voltage of the fourth NMOS transistor N4 (ie, the voltage V BIAS ) is compared, if the gate voltage of the third NMOS transistor N3 (i.e., the voltage V DET) is higher than the gate voltage of the fourth NMOS transistor N4 (ie, the voltage V BIAS ), the output terminal of the comparator module 20, namely the node COUT, outputs a high level; if the gate voltage of the fourth NMOS tube N4 (ie, the voltage V of the node VBIAS) BIAS ) is higher than the gate voltage of the third NMOS transistor N3 (i.e., the voltage V DET ), the output terminal of the comparator module 20, namely the node COUT, outputs a low level.
[0072] Therefore, as the power supply voltage of the power supply terminal VDD gradually increases, when V DET Lower than V BIAS When , the output terminal of the comparator module 20, namely the node COUT, outputs a low level. At this time, through the cascaded first inverter I1, the second inverter I2, and the second buffer B2, the node PORB outputs a low level.
[0073] Then the power supply voltage continues to increase, when V DET Higher than V BIAS After that, the output terminal of the comparator module 20, namely the node COUT, outputs a high level, and after passing through the cascaded first inverter I1, the second inverter I2, and the second buffer B2, the node PORB outputs a high level. At this time, the power supply voltage is the power-on reset voltage.
[0074] After the reset circuit is powered on, it starts the power-off reset process. The output terminal of the comparator module 20, i.e., the node COUT, outputs a high level. After passing through the cascaded first inverter I1 and the first buffer B1, a low level is output from the output terminal of the first buffer B1. The fourth PMOS transistor P4 is turned on. The fourth PMOS transistor P4 and the fifth PMOS transistor P5 play a role in controlling the hysteresis voltage. At this time, the current I flowing through the fourth NMOS transistor N4 N4 =I P3 +I P4 At this time, the current I flowing through the third NMOS tube N3 N3 =I P2 .
[0075] If the current I N4 Greater than the current I of the third NMOS tube N3 N3 ,need The output terminal of the comparator module 20, namely the node PORB, can be changed to a low level again, that is, the power-down reset voltage must be lower than the power-on reset voltage; wherein W N4 is the width of the fourth NMOS tube N4, L N4 is the length of the fourth NMOS tube N4, W N3 is the width of the third NMOS tube N3, L N3 is the length of the third NMOS tube N3.
[0076] As can be seen from the above, the full CMOS reset circuit 000 provided in this embodiment avoids the use of large-sized electronic components such as resistors that require a large area of layout in each module, thereby reducing the circuit layout area and chip cost, and has lower power consumption. It can extend the standby time of the chip system and can also achieve the same reset effect of the digital circuit as the prior art.
[0077] In some optional embodiments, please refer to Figure 3 and Figure 4 , Figure 4 yes Figure 3 A schematic diagram of the reset circuit in FIG. 1 obtained by simulation of the node PORB changing with the power supply voltage of the power supply terminal, wherein the abscissa is the power supply voltage provided by the power supply terminal VDD, and the ordinate is the reset signal output by the node PORB;
[0078] Before the power supply voltage rises to the power-on reset voltage, the reset signal output by the node PORB is at a low level (valid reset signal). At this time, the reset circuit resets the digital circuit connected to the reset circuit. At this time, the reset signal output by the node PORB is at a low level. Figure 4 The stage indicated by the dashed arrow K1;
[0079] When the power supply voltage rises to the power-on reset voltage (the power-on reset voltage is as Figure 4 After the reset signal of the node PORB is high (not a valid reset signal), the reset circuit stops resetting and the digital circuit connected to the reset circuit enters the normal working mode; the reset signal of the node PORB is high (not a valid reset signal). Figure 4 The stage indicated by the dashed arrow K2;
[0080] After that, the power supply voltage drops to the power-down reset voltage (the power-down reset voltage is as follows Figure 4 After the reset signal output by the node PORB is changed to the low level reset signal PORB (valid reset signal), the reset circuit resets the digital circuit connected to the reset circuit again, and the digital circuit enters the reset state and stops the normal working mode; at this time, the reset signal output by the node PORB is low level. Figure 4 The stage is indicated by the dashed arrow K3.
[0081] The full CMOS reset circuit of this embodiment can make the power-on reset voltage higher than the power-off reset voltage, thereby ensuring the anti-interference capability of the circuit when the power supply voltage is close to the power-on reset voltage.
[0082] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0083] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A full CMOS reset circuit, characterized in that: It includes a bias module, a comparator module, a hysteresis generation module and an output module which are electrically connected; wherein, The output end of the bias module is electrically connected to the input end of the comparator module, and the bias module is used to generate a bias voltage for use by the comparator module; The comparator module is used to compare whether the power supply voltage provided by the power supply terminal exceeds the bias voltage, and feed back the comparison result to the input terminal of the hysteresis generation module; The hysteresis generating module is used to realize the hysteresis of the power-off reset voltage during the power-off reset process of the full CMOS reset circuit, so that the power-off reset voltage is lower than the power-on reset voltage; The output end of the output module is used to output a reset signal; The bias module only includes a plurality of electrically connected PMOS tubes and NMOS tubes, the comparator module only includes a plurality of electrically connected PMOS tubes and NMOS tubes, the hysteresis generation module only includes a plurality of electrically connected PMOS tubes, a first inverter and a first buffer, and the output module includes an electrically connected second inverter and a second buffer.
2. The full CMOS reset circuit according to claim 1, characterized in that: The bias module includes a first PMOS tube and a first NMOS tube, the comparator module includes a second PMOS tube, a third PMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube, the hysteresis generation module includes a fourth PMOS tube, a fifth PMOS tube, a first buffer and a first inverter, and the output module includes a second inverter and a second buffer; The sources of the first PMOS tube, the second PMOS tube, the third PMOS tube, and the fourth PMOS tube are all electrically connected to the power supply end, and the gate of the first PMOS tube and the sources of the first NMOS tube and the second NMOS tube are all grounded; The drain of the first PMOS tube is electrically connected to the gate and drain of the first NMOS tube, the gate of the second NMOS tube, and the gate of the fourth NMOS tube respectively; the drain of the second NMOS tube is electrically connected to the source of the third NMOS tube and the source of the fourth NMOS tube respectively; the gate and drain of the second PMOS tube are electrically connected, and are electrically connected to the gate of the third PMOS tube, the gate of the fifth PMOS tube, and the gate and drain of the third NMOS tube respectively; the drain of the third PMOS tube is electrically connected to the drain of the fourth NMOS tube, the drain of the fifth PMOS tube, and the input end of the first inverter respectively; the drain of the fourth PMOS tube is electrically connected to the source of the fifth PMOS tube, and the output end of the first inverter is electrically connected to the input end of the second inverter and the input end of the first buffer respectively; the output end of the first buffer is electrically connected to the gate of the fourth PMOS tube, the output end of the second inverter is electrically connected to the input end of the second buffer, and the output end of the second buffer outputs a reset signal.
3. The full CMOS reset circuit according to claim 2, characterized in that: The output module further includes a delay structure, and the delay structure is electrically connected to the output end of the second inverter.
4. The full CMOS reset circuit according to claim 3, characterized in that: The delay structure includes a fifth NMOS tube, a gate of the fifth NMOS tube is electrically connected to the output end of the second inverter, and a source and a drain of the fifth NMOS tube are both grounded.
5. The full CMOS reset circuit according to claim 2, characterized in that: The width of the first PMOS tube is W P1 , the length of the first PMOS tube is L P1 , where L P1 >W P1 .
6. The full CMOS reset circuit according to claim 2, characterized in that: The width of the first NMOS tube is twice the width of the second NMOS tube, and the length of the first NMOS tube is the same as the length of the second NMOS tube.
7. The full CMOS reset circuit according to claim 2, characterized in that: The width-to-length ratio of the second PMOS tube is the same as the width-to-length ratio of the third PMOS tube.
8. The full CMOS reset circuit according to claim 2, characterized in that: The width-to-length ratio of the third NMOS tube is the same as the width-to-length ratio of the fourth NMOS tube.
9. A method for operating a full CMOS reset circuit, characterized in that: A full CMOS reset circuit according to any one of claims 2 to 7; the working method comprising: The power supply terminal provides a power supply voltage, and the power supply voltage starts to rise from zero; during the rising process of the power supply voltage: When the power supply voltage is lower than the turn-on voltage of the first PMOS tube in the bias module, the output end of the bias module, i.e., the gate voltage of the first NMOS tube, is zero, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the second PMOS tube, and the third PMOS tube in the comparator module are in a cut-off state, and the output end of the comparator module maintains an output low level. After passing through the first inverter of the hysteresis generation module, the second inverter of the output module, and the second buffer, the reset signal output by the output module is a low level; When the power supply voltage is higher than the turn-on voltage of the first PMOS tube in the bias module: If the gate potential of the third NMOS tube in the comparator module is lower than the gate potential of the fourth NMOS tube, the output end of the comparator module maintains the output low level, and the reset signal output by the output module is still at a low level; If the gate potential of the third NMOS tube in the comparator module is higher than the gate potential of the fourth NMOS tube, the output end of the comparator module outputs a high level, and after passing through the first inverter of the hysteresis generation module, the second inverter of the output module, and the second buffer, the reset signal output by the output module is a high level; at this time, the value of the power supply voltage is a power-on reset voltage; After the power-on reset is completed, the power-off reset process starts, the output end of the comparator module outputs a high level, and after passing through the first inverter and the first buffer of the hysteresis generation module, the output end of the first buffer outputs a low level, and the fourth PMOS tube is turned on; The output end of the comparator module re-outputs a low level, and after passing through the first inverter of the hysteresis generation module, the second inverter of the output module, and the second buffer, the reset signal output by the output module is a low level; at this time, the value of the power supply voltage is a power-down reset voltage, and the value of the power-down reset voltage is lower than the value of the power-on reset voltage.