Input pair circuit and DC-DC circuit

Abstract

The invention discloses an input pair circuit and a DC-DC circuit. The input pair circuit comprises a reference voltage providing circuit, an input pair transistor, a reverse coupling circuit and an output circuit. The reference voltage providing circuit is used for providing reference voltage to the input geminate transistors according to reference current; the input pair transistor comprises a first transistor and a second transistor, a first end of the first transistor and a first end of the second transistor are connected with the reference voltage, a body end of the first transistor is connected with a body end of the second transistor, and a control end of the first transistor and a control end of the second transistor are coupled with an input signal; the reverse coupling circuit is used for providing a reverse voltage for the body end of the first transistor and the body end of the second transistor when the reference current changes, so as to at least partially offset a deviation voltage generated at the control end of the first transistor and the control end of the second transistor due to the change of the reference current; the output circuit is used for comparing the voltage at the control end of the first transistor with the voltage at the control end of the second transistor and outputting a comparison result.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to an input pair circuit and a DC-DC circuit. Background Art

[0002] Since the DC-DC system does not always operate under high load, when it is in light load and standby state, it usually needs to maintain a high efficiency to improve battery life and the life of the power supply (such as battery). Generally speaking, light load has low output power, and the static power consumption and drive loss account for a large proportion, which makes the efficiency often not high.

[0003] Although the driving loss can be reduced by reducing the switching times by lowering the frequency, and the static loss can also be reduced by reducing the static current when there is no switching action for a long time, this involves the problem of current switching. For the same circuit, the current under current saving may be only 1 / 1000 of that under normal operation or even lower. This may cause circuit output errors during the current change process. For example, the traditional input pair circuit may cause output errors when switching between current saving and non-current saving. Summary of the invention

[0004] In view of the above situation, the embodiments of the present application propose an input pair circuit and a DC-DC circuit to overcome or at least partially overcome the deficiencies of the prior art.

[0005] In a first aspect, an input pair circuit provided by an embodiment of the present application includes a reference voltage providing circuit, an input pair tube, a reverse coupling circuit and an output circuit;

[0006] The reference voltage providing circuit is used to provide a reference voltage to the input pair tube according to the reference current;

[0007] The input transistor pair includes a first transistor M3 and a second transistor M4, a first end of the first transistor M3 and a first end of the second transistor M4 are connected to the reference voltage, a body end of the first transistor M3 and a body end of the second transistor M4 are connected, and a control end of the first transistor M3 and a control end of the second transistor M4 are coupled to an input signal;

[0008] The reverse coupling circuit is used to provide a reverse voltage to the body terminal of the first transistor M3 and the body terminal of the second transistor M4 when the reference current changes, so as to at least partially offset the deviation voltage generated at the control terminal of the first transistor M3 and the control terminal of the second transistor M4 due to the change of the reference current;

[0009] The output circuit is used for comparing the voltages at the control end of the first transistor M3 and the control end of the second transistor M4 and outputting the comparison result.

[0010] In one embodiment, the reverse coupling circuit further comprises:

[0011] The bias circuit is used to obtain a bias current as a feedback current.

[0012] A switch circuit, connected to the bias circuit, configured to receive an external conduction control signal and open or close a switch according to the external conduction control signal to control the on and off of the feedback current;

[0013] The voltage feedback circuit is connected to the switch circuit and generates the reverse voltage according to the provided feedback current.

[0014] In one embodiment, the bias circuit is connected between a power supply terminal VCC and ground, and includes transistors M9-M12 and a resistor R4, wherein the transistor M9 and the transistor M10 form a current mirror, the gates of the transistors M9 and M10 are connected to each other, the sources of the transistors M9 and M10 are connected to the power supply terminal VCC, the gates of the transistors M11 and M12 are connected, the drain and gate of the transistor M11 are connected to the drain of the transistor M9, the drain of the transistor M12 is connected to the drain and gate of the transistor M10, and the resistor R4 is arranged between the source of the transistor M12 and ground.

[0015] In one embodiment, the switch circuit includes transistors M7-M8, the source of the transistor M7 is connected to the drain of the transistor M8, the transistor M8 and the transistor M11 form a current mirror, and the transistor M8 mirrors the bias current passing through the resistor R4 to generate the feedback current; the gate of the transistor M7 is connected to the external conduction control signal, and the external conduction control signal is related to the reference current change.

[0016] In one embodiment, the voltage feedback circuit has a resistor R3, a first end of the resistor R3 is connected to the power supply end VCC, a second end is connected to the body end of the first transistor M3 and the body end of the second transistor M4, and the resistor R3 is used to obtain a reverse voltage.

[0017] In one embodiment, a first end of the reference voltage providing circuit is connected to a power supply terminal VCC, and the other end is connected to sources of a first transistor M3 and a second transistor M4 of the input pair of transistors. The reference voltage providing circuit comprises a transistor M1, a transistor M2 and a current source. A first end of the current source is connected to a drain of the transistor M1, and a second end is connected to ground. The transistor M1 and the transistor M2 form a current mirror. The current source provides a reference current for the transistor M1. The transistor M2 replicates the reference current of the transistor M1 and converts the reference current into a reference voltage.

[0018] In one embodiment, the input pair of tubes further includes a capacitor C1, a resistor R1, a capacitor C2, and a resistor R2;

[0019] The control end of the first transistor M3 is connected to the input signal VIN1, and the control end of the second transistor M4 is connected to the input signal VIN2. The capacitor C1 and the resistor R1 form an R1C1 parallel circuit, and the capacitor C2 and the resistor R2 form an R2C2 parallel circuit. One end of the R1C1 parallel circuit is coupled to the gate of the first transistor M3, and the other end is grounded. One end of the R2C2 parallel circuit is coupled to the gate of the second transistor M4, and the other end is grounded.

[0020] In one embodiment, the output circuit includes a transistor M5 and a transistor M6, wherein the gates of the transistor M5 and the transistor M6 are connected to each other, the source terminals and the body terminals of the transistor M5 and the transistor M6 are grounded, the transistor M5 and the transistor M6 form a current mirror, the drain and the gate of the transistor M5 are connected to the drain of the first transistor M3, the drain of the transistor M6 is connected to the drain of the second transistor M4, the output node is located between the drain D of the second transistor M4 and the drain D of the transistor M6, and the output node is used to output the comparison result, and the comparison result is the voltage difference V_OUT of the input signals VIN1 and VIN2.

[0021] In a second aspect, an embodiment of the present application provides a DC-DC circuit, comprising the input pair circuit described above.

[0022] At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects:

[0023] In this embodiment, a reverse coupling circuit is provided to provide a reverse voltage to the body terminal of the first transistor and the body terminal of the second transistor when the reference current changes, so as to at least partially offset the deviation voltage generated at the control terminal of the first transistor and the control terminal of the second transistor due to the change of the reference current, so that the gate input signals VIN1 and VIN2 of the first transistor M3 and the second transistor M4 are stable, thereby avoiding output signal errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0025] Figure 1 A schematic diagram of the input pair circuit structure according to the first embodiment of the present application is shown;

[0026] Figure 2The waveform diagram when the input to the circuit voltage is restored according to the present application is shown.

[0027] Figure 3 A schematic diagram of the input pair circuit structure according to a second embodiment of the present application is shown;

[0028] Figure 4 A logic block diagram of an input pair circuit according to a second embodiment of the present application is shown.

[0029] Figure 5 This is the timing diagram of the external conduction control signal. DETAILED DESCRIPTION

[0030] Exemplary embodiments of the present disclosure will now be described in detail, examples of which are shown in the accompanying drawings. The same reference numerals are used throughout the drawings to represent the same or similar parts as much as possible. In the specification, it should be noted that similar reference numerals that have been used to represent similar parts in other drawings are used for these elements as much as possible. In the following description, when functions and configurations known to those skilled in the art are not related to the basic configuration of the present disclosure, their detailed description will be omitted. The terms described in the specification should be understood as follows.

[0031] The advantages and features of the present disclosure and their implementation methods will be described through the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments described herein. Rather, these embodiments are provided to make the present disclosure comprehensive and complete, so as to fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0032] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings used to describe the embodiments of the present disclosure are merely examples, and the present disclosure is therefore not limited to the illustrated details. Similar reference numerals always represent similar elements. In the following description, when it is determined that a detailed description of a related known function or construction will inevitably obscure the focus of the present disclosure, the detailed description will be omitted.

[0033] As those skilled in the art can fully understand, the features of the various embodiments of the present disclosure can be partially or completely combined or combined with each other, and can interoperate and technically drive each other in various ways. The embodiments of the present disclosure can be performed independently of each other, or can be performed together in a mutually dependent relationship.

[0034] In the present application, a MOS tube (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first end, a second end and a control end. When the MOS tube is in the on state, current flows from the first end to the second end. The first end, the second end and the control end of the PMOS tube are the source D, the drain S and the gate G, respectively, and the first end, the second end and the control end of the NMOS tube are the drain D, the source S and the gate G, respectively.

[0035] In the prior art, when the DC-DC system switches states, for example, when switching between the standby state and the load state, the reference current I_REF will be different, which involves the problem of current switching. For the same circuit, the reference current I_REF in the standby state (current saving state) is only 1 / 1000 of that in the normal working state or even lower. This may cause circuit output errors during the current change process. The present application adopts the following solution to solve the above defects, which are as follows:

[0036] like Figure 1 As shown, the input pair circuit of the first embodiment of the present application includes a reference voltage providing circuit, an input pair tube, and an output circuit. The current mirror is connected between the power supply terminal VCC and the ground, the input pair tube circuit is connected between the output end of the current mirror and the input end of the output circuit, and the output circuit is connected between the output end of the input pair tube and the ground.

[0037] The reference voltage providing circuit is used to convert the reference current into a reference voltage and provide it to the input pair of transistors. The first end of the reference voltage providing circuit 100 is connected to the power supply terminal VCC, and the other end is connected to the common source of the input pair of transistors. Specifically, the reference voltage providing circuit has a transistor M1, a transistor M2 and a current source. The transistor M1 and the transistor M2 are both PMOS transistors. The first ends of the transistor M1 and the transistor M2 are connected to the power supply terminal VCC. The first end of the current source is connected to the drain D and the gate G of the transistor M1. The second end of the current source is connected to the ground. The current source provides a reference current for the transistor M1. The transistor M1 and the transistor M2 form a current mirror, which is used to copy the reference current I_REF of the transistor M1. The reference current I_REF is provided to the input pair of transistors through the drain of the transistor M2 as the tail current of the transistor M2. The drain of the transistor M2 is a reference voltage node. The reference voltage VS of the reference voltage node is the input voltage of the source S of the first transistor M3 and the second transistor M4.

[0038] Reference Figure 1As shown, the input pair includes a first transistor M3 and a second transistor M4, the sources of the first transistor M3 and the second transistor M4 are connected to each other, and the source S of the first transistor M3 and the source S of the second transistor M4 are both connected to the drain of the transistor M2. The gates G of the first transistor M3 and the second transistor M4 are connected to the input signals of different load systems. When the reference voltage of the source S suddenly changes, the parasitic capacitance voltage of the input pair is coupled to the gate G, causing the input signal to generate a deviation voltage. The first transistor M3 and the second transistor M4 are both PMOS transistors, and the first terminal and the body terminal of the first transistor M3 and the second transistor M4 are both connected to the reference voltage node.

[0039] Reference Figure 1 As shown, the input pair tube (M3, M4) is controlled by the reference current of the current mirror. When exiting from the current saving state, the source S reference current of the input pair tube changes. Since the gate of the input pair tube is connected to the equivalent input resistance and capacitance and the transistor itself has parasitic capacitance, at the moment when the source S reference current suddenly changes, the increased source S voltage and body terminal voltage will be coupled to the gate G of the input pair tube through the parasitic capacitance, thereby causing the input signal of the gate G of the input pair tube to change.

[0040] like Figure 1 As shown, there is a parasitic capacitor C_GS3 between the gate-source terminal of the first transistor M3, and a parasitic capacitor C_GB3 between the control terminal and the body terminal. Similarly, there is a parasitic capacitor C_GS4 between the gate-source terminal of the second transistor M4, and a parasitic capacitor C_GB4 between the control terminal and the body terminal. The control terminal of the first transistor M3 is connected to the input signal VIN1, and the control terminal of the second transistor M4 is connected to the input signal VIN2. The input signals VIN1 and VIN2 are output signals of different load systems respectively. Since the input signals of the input pair are provided by different load systems, there are equivalent output capacitors and resistors as inputs at the same time.

[0041] In the present application, capacitor C1 and resistor R1 are the output capacitor and resistor of input signal VIN1, and capacitor C2 and resistor R2 are the output capacitor and resistor of input signal VIN2. Capacitor C1 and resistor R1 form a R1C1 parallel circuit, the first end of the R1C1 parallel circuit is coupled to the control end of the first transistor M3, and the second end is grounded. Capacitor C2 and resistor R2 form a R2C2 parallel circuit, the first end of the R2C2 parallel circuit is coupled to the control end of the second transistor M4, and the second end is grounded. In the above scheme, since input signals VIN1 and VIN2 are output signals of different load systems, the equivalent resistance and capacitance R1 / C1 of input signal VIN1 and the equivalent resistance and capacitance R2 / C2 of input signal VIN2 are usually different. When there is no switching action under light load, the static current will be reduced to improve efficiency, so that the reference current I_REF will become smaller. When switching is required, this current will return to normal, so there will be a switching of the reference current I_REF from large to small under light load.

[0042] Taking the reference current I_REF as an example, when the standby state (current saving state) is restored to the light load state, the reference current I_REF is relatively small in the standby state. At the moment of recovery from the standby state, the tail current of the transistor M2 mirror will also increase, and then the source S and the body of the first transistor M3 and the second transistor M4 will increase the current, so that the current of the first transistor M3 and the second transistor M4 will also increase. However, due to the parasitic capacitance between the gate-source GS and GB, such as C_GS3 / C_GB3, the increased source S and the body will be coupled to the control end of the first transistor M3 through the parasitic capacitance. In this way, at this moment, the voltage coupled to the control end becomes the voltage divided by the parasitic capacitance and the original input capacitance. The capacitor series also has a voltage dividing function, but the characteristic of the capacitor is that the smaller the capacitance, the greater the voltage divided. If the input capacitance is larger, the instantaneous coupled voltage will be lower. As time goes by, the coupled voltage will gradually decrease. The time of reduction is determined by the RC constant of the capacitor. At this time, the larger the capacitance and resistance, the larger the time constant, which will cause the voltage to drop to normal for a longer time.

[0043] like Figure 1 As shown, assuming Figure 1In the middle, capacitor C1 is smaller than capacitor C2, and resistor R1 is the same as resistor R2. Thus, when the reference current I_REF increases, since the capacitance of capacitor C1 is smaller than that of capacitor C2, the characteristic of the capacitor is that the smaller the capacitance, the larger the voltage. The input signal VIN1 rises higher due to the coupling, but since R1*C1 is smaller than R2*C2, its falling speed is also faster. Although the input signal VIN2 rises slowly, it falls very slowly. Thus, there may be a time when the input signal VIN2 is greater than the input signal VIN1. If the input signal VIN2 is less than the input signal VIN1 before the coupling, the coupling will cause the input signal of the control end to be reversed. If the input end is in an incorrect state for a long time, the output may also be wrong.

[0044] The output circuit is used to compare the input signal and output the comparison result. Therefore, due to the defects of the above solution, the comparison result output by the output circuit is inaccurate. Figure 1 The output circuit includes a transistor M5, a transistor M6 and an output node. The transistor M5 and the transistor M6 form a current mirror, wherein the transistor M5 and the transistor M6 are NMOS tubes, wherein the source end / body end of the transistor M5 and the transistor M6 are grounded. The current flowing through the first transistor M3 is mirror-copied to the transistor M6 and then output to the output node, and the current at the second end of the second transistor M4 is output to the output node. The output node is located between the drain D of the second transistor M4 and the drain D of the transistor M6, and is used to output a comparison result, which is a voltage difference VOUT between the input signal VIN1 and the input signal VIN2 of the first transistor M3 and the second transistor M4.

[0045] Since the voltage difference VOUT of the output node depends on the size of VIN1 and VIN2, such as Figure 2 , if it appears Figure 2 As shown in the waveforms of the input signals VIN1 and VIN2, at the rising edge of the reference voltage VS, the peak voltage of the input signal VIN1 is greater than the peak voltage of the input signal VIN2, and later the peak voltage of the input signal VIN1 is less than the peak voltage of the input signal VIN2, so the voltage difference V-OUT will also change, causing V-OUT to change when VS changes, resulting in V-OUT being unexpectedly uncontrollable, so the comparison result is uncontrollable.

[0046] Therefore, for this type of current saving and recovery structure, without any processing, it is necessary to make the capacitance and resistance of the control terminals of the first transistors M3 and M4 as similar as possible, which greatly limits the scope of the circuit that can save current.

[0047] The input pair circuit in the first embodiment described above will quickly pull down the highly coupled input signals VIN1 and VIN2 to normal values ​​through the pull-down circuit, and pull up again when in reverse (entering current saving). However, it is difficult to control the amplitude of the pull-up and pull-down. If the amplitude is too large, the input signal may deviate greatly from the original normal value, resulting in output errors. If it is too small, the effect is not obvious.

[0048] The above problem mainly lies in the fact that the current flowing through the same MOS tube is different when saving current and when not saving current. Assuming that the reference current I_REF is I1 when saving current and I2 when not saving current, the gate-source voltages corresponding to the currents I1 and I2 flowing through the MOS are VGS1 and VGS2 respectively. When the reference current I_REF changes from I1 to I2, the gate-source voltage of the MOS tube in the stable state needs to change from VGS1 to VGS2, where the control terminal voltage is a fixed value, so the source S voltage needs to change, and the source S voltage change is VGS2-VGS1. At this time, if a reverse voltage is generated, the amplitude of the reverse voltage is k times the voltage added by the source S. The k value can be determined by the ratio of the influence of the source S on the control terminal and the body terminal on the control terminal, which is mainly related to the parasitic capacitance, thereby offsetting the influence of the source S voltage change on the control terminal.

[0049] Based on the above analysis of the first embodiment, the second embodiment of the present application proposes an input pair circuit, see Figure 3 , Figure 4 The input pair circuit includes a reference voltage providing circuit 100, an input pair tube 200, a reverse coupling circuit 300, and an output circuit 400. The input pair circuit of the present application can accurately and quickly restore the coupled signal (input signal VIN1 and VIN2) by adding the reverse coupling circuit 300. Compared with the first embodiment, the present embodiment has the reference voltage providing circuit 100 and the output circuit 400 in the first embodiment, and the circuit structure and principle are the same as those of the first embodiment, which will not be described in detail in this embodiment.

[0050] It should be noted that the input pair of pipes 200 in this embodiment is different from the input pair of pipes in the first embodiment. Figure 3 , Figure 1In the first embodiment, the input pair includes a first transistor M3 and a second transistor M4. The source S and the body of the first transistor M3 and the second transistor M4 are coupled to the reference voltage node. The difference between this embodiment and the first embodiment is that in this embodiment, the first end of the first transistor M3 and the first end of the second transistor M4 are connected to the reference voltage, the body of the first transistor M3 and the body of the second transistor M4 are connected, and the control end of the first transistor M3 and the control end of the second transistor M4 are coupled to the input signal. In this embodiment, the body of the first transistor M3 and the second transistor M4 are no longer coupled to the reference voltage node. In addition to the above differences, the other circuit structures of the input pair 200 in this embodiment are the same as those in the first embodiment.

[0051] The reverse coupling circuit of this embodiment is used to provide a reverse voltage to the body terminal of the first transistor M3 and the body terminal of the second transistor M4 when the reference current changes, so as to at least partially offset the deviation voltage generated at the control terminal of the first transistor M3 and the control terminal of the second transistor M4 due to the change of the reference current.

[0052] Specifically: The reverse coupling circuit includes a bias circuit, a switch circuit, and a voltage feedback circuit. The bias circuit is used to obtain a bias current as a feedback current. The switch circuit is connected to the bias circuit, and is used to receive an external conduction control signal and open or close the switch according to the conduction control signal to control the on and off of the feedback current; the voltage feedback circuit is connected to the switch circuit, and is used to generate a reverse voltage according to the provided feedback current, and the reverse voltage is used to offset the voltage change value of the gate input signal caused by the source voltage change. The reverse coupling circuit is used to adjust the offset caused by the gate-source voltage of the first transistor M3 and the second transistor M4, which is beneficial to improve the accuracy of the output result. The following content is the specific structure of the reverse coupling circuit.

[0053] like Figure 3As shown, the bias circuit is connected between the power supply terminal VCC and the ground, and the bias circuit includes transistors M9-M12 and a resistor R4, wherein the transistors M9 and M10 form a current mirror, and the transistor M9 is connected to the gate of the transistor M10. The transistors M9-M10 are PMOS tubes, the transistors M11-M12 are NMOS tubes, and there is a certain ratio between the transistors M11 and M12. The gates of the transistors M11 and M12 are connected, the drain and gate of the transistor M11 are connected to the drain of the transistor M9, the drain of the transistor M12 is connected to the drain and gate of the transistor M10, and the resistor R4 is connected between the source of the transistor M12 and the ground to obtain the bias current. The bias current flowing through the resistor R4 is (VGS11-VGS12) / R4, and the bias current has information related to the VGS difference, wherein VGS11 is the gate-source voltage of the transistor M11, and VGS12 is the gate-source voltage of the transistor M12.

[0054] Continue to refer to Figure 3 The first end of the switch circuit is connected to the gate of the transistor M11 and the transistor M12, and the other end is connected to the common body end of the input pair 200 (the first transistor M3 and the second transistor M4). The switch circuit includes a transistor M7 and a transistor M8. The transistor M7 and the transistor M8 are NMOS transistors. The drain of the transistor M7 is connected to the body end of the first transistor M3, and the drain of the transistor M7 is connected to the body end of the second transistor M4. The source of the transistor M7 is connected to the drain of the transistor M8. The transistor M8 and the transistor M11 form a current mirror. The transistor M8 mirrors the bias current passing through the resistor R4 to generate the feedback current. Since the transistor M8 also forms a current mirror with the transistor M11, the transistor M8 mirrors the current passing through the resistor R4, and uses the bias current as the feedback current.

[0055] Continue to refer to Figure 3 The gate of the transistor M7 is connected to an external conduction control signal, and the external conduction control signal is related to the change of the reference current. The external conduction control signal V_CTRL controls the opening or closing of the transistor M7 to control the on-off of the feedback current.

[0056] See Figure 5 , Figure 5It is the timing diagram of the external conduction control signal V_CTRL. It is always open when exiting the current saving mode and is always closed after entering the current saving mode. Among them, V_M3.4S is the voltage timing diagram of the source S of the first transistor M3 and the first transistor M4, and V_M3.4B is the voltage timing diagram of the body terminal B of the first transistor M3 and the first transistor M4. The external conduction control signal V_CTRL is related to the current saving signal. When exiting the current saving mode, the external conduction control signal V_CTRL will become high, turn on the transistor M7, let the current flow through R3, and let the input to the body terminal B of the tube 200 generate a pull-down voltage to offset the upward voltage of the source S. After that, this current can always exist. In the steady state, the voltage of the body terminal B is lower than the power supply voltage (VGS11-VGS12)*R3 / R4, which reduces the threshold voltage Vth of the transistor M3 / 4. When entering current saving, the external conduction control signal V_CTRL changes from high to low, the current is removed, and an upward voltage is generated to offset the downward voltage of the source S when entering current saving. Therefore, the external conduction control signal V_CTRL can be set as a signal synchronized with the current saving signal. When the current saving becomes high, the external conduction control signal V_CTRL becomes low, and when the current saving becomes low, the external conduction control signal V_CTRL becomes high. Some adjustments can also be made according to actual simulations, for example, the change can be advanced or postponed a little relative to the current saving signal.

[0057] Continue to refer to Figure 3 , a voltage feedback circuit is connected to the switch circuit, and generates the reverse voltage according to the feedback current provided. The voltage feedback circuit includes a resistor R3, a first end of which is connected to the power supply terminal VCC, and a second end is connected to the body end of the first transistor M3 and the body end of the second transistor M4. When the current saving is exited, the transistor M7 is timely turned on by the external conduction control signal V_CTRL, and the current flows through the resistor R3, so that the body end voltage of the first transistor M3 and the body end voltage of the second transistor M4 decrease, and the decrease amplitude is (VGS11-VGS12)*R3 / R4. Since the rising voltage of the source of the first transistor M3 and the second transistor M4 is also related to the gate-source voltage, by adjusting R3 and R4 to control the magnitude of the falling voltage of the body end of the first transistor M3 and the second transistor M4, the influence of the rising source S of the first transistor M3 and the second transistor M4 can be relatively accurately weakened or even eliminated, so that the gate input signals VIN1 and VIN2 of the first transistor M3 and the second transistor M4 are stable.

[0058] Please refer to Figure 3The output circuit has the same structure as that of the first embodiment, including transistors M5, M6 and an output node. The voltage difference of the gate input signals VIN1 and VIN2 of the first transistor M3 and the second transistor M4 is output through the output node. The input signals VIN1 and VIN2 of the control terminals of the first transistor M3 and the second transistor M4 are relatively stable. For example, the input signals VIN1 and VIN2 are relatively stable within a preset range, thereby avoiding errors in the output signals.

[0059] The present application also provides a DC-DC circuit, comprising the input pair circuit.

[0060] For example, the input pair circuit can be applied to a DC-DC circuit with a constant on-time COT architecture and used as a comparator of the DC-DC circuit. The input signal VIN1 of the input pair circuit of the present application is the feedback voltage FB of the DC-DC circuit, and the input signal VIN2 is the reference voltage REF of the DC-DC circuit. Whether to turn on the power tube is determined by detecting the magnitude of the feedback voltage FB and the reference voltage REF. If an error flip causes the power tube to be turned on by mistake or not turned on when it should be turned on, the entire loop will be wrong. In order to reduce delay, the current of the input pair circuit is usually larger when it is not saving current, so the current changes more when saving current, which can easily cause errors. Therefore, it is urgent to output accurate comparison results of the input pair circuit.

[0061] It should be noted that although in this article, the device is described as a certain N-channel or P-channel device, or a certain N-type or P-type doped region, it can be understood by those skilled in the art that complementary devices can also be realized according to the present invention. It can be understood by those skilled in the art that the conductivity type refers to the mechanism by which the conduction occurs, such as conduction by holes or electrons, so the conductivity type does not involve the doping concentration but the doping type, such as P-type or N-type. It can be understood by those skilled in the art that the words "during", "when" and "when..." used in this article in connection with the operation of the circuit are not strict terms indicating the action that occurs immediately when the start-up action begins, but there may be some small but reasonable one or more delays between it and the reaction action initiated by the start-up action, such as various transmission delays, etc. The words "approximately" or "substantially" used in this article mean that the element value has a parameter that is expected to be close to the declared value or position. However, as is well known in the art, there are always slight deviations that make it difficult for the value or position to be strictly the declared value. It has been well established in the art that a deviation of at least ten percent (10%) (or at least twenty percent (20%) for semiconductor doping concentrations) is a reasonable deviation from the exact ideal goal described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive logic or negative logic is used.

[0062] In addition, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0063] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. An input pair circuit, characterized in that It includes a reference voltage providing circuit, an input pair of tubes, a reverse coupling circuit and an output circuit; The reference voltage providing circuit is used to provide a reference voltage to the input pair tube according to the reference current; The input transistor pair includes a first transistor M3 and a second transistor M4, a first end of the first transistor M3 and a first end of the second transistor M4 are connected to the reference voltage, a body end of the first transistor M3 and a body end of the second transistor M4 are connected, and a control end of the first transistor M3 and a control end of the second transistor M4 are coupled to an input signal; The reverse coupling circuit is used to provide a reverse voltage to the body terminal of the first transistor M3 and the body terminal of the second transistor M4 when the reference current changes, so as to at least partially offset the deviation voltage generated at the control terminal of the first transistor M3 and the control terminal of the second transistor M4 due to the change of the reference current; The output circuit is used for comparing the voltages at the control end of the first transistor M3 and the control end of the second transistor M4 and outputting the comparison result.

2. The input pair circuit according to claim 1, characterized in that The reverse coupling circuit further comprises: The bias circuit is used to obtain a bias current as a feedback current. A switch circuit, connected to the bias circuit, configured to receive an external conduction control signal and open or close a switch according to the external conduction control signal to control the on and off of the feedback current; The voltage feedback circuit is connected to the switch circuit and generates the reverse voltage according to the provided feedback current.

3. The input pair circuit according to claim 2, characterized in that The bias circuit is connected between the power supply terminal VCC and the ground. The bias circuit includes transistors M9-M12 and a resistor R4, wherein the transistor M9 and the transistor M10 form a current mirror, the gates of the transistors M9 and M10 are connected to each other, the sources of the transistors M9 and M10 are connected to the power supply terminal VCC, the gates of the transistors M11 and M12 are connected, the drain and gate of the transistor M11 are connected to the drain of the transistor M9, the drain of the transistor M12 is connected to the drain and gate of the transistor M10, and the resistor R4 is arranged between the source of the transistor M12 and the ground.

4. The input pair circuit according to claim 3, characterized in that The switch circuit includes transistors M7-M8, the source of the transistor M7 is connected to the drain of the transistor M8, the transistor M8 and the transistor M11 form a current mirror, and the transistor M8 mirrors the bias current passing through the resistor R4 to generate the feedback current; the gate of the transistor M7 is connected to the external conduction control signal.

5. The input pair circuit according to claim 2, characterized in that The voltage feedback circuit comprises a resistor R3, a first end of the resistor R3 is connected to the power supply end VCC, a second end of the resistor R3 is connected to the body end of the first transistor M3 and the body end of the second transistor M4, and the resistor R3 is used to obtain a reverse voltage.

6. The input pair circuit according to claim 1, characterized in that The first end of the reference voltage providing circuit is connected to the power supply terminal VCC, and the other end is connected to the source of the first transistor M3 and the second transistor M4 of the input pair. The reference voltage providing circuit has a transistor M1, a transistor M2 and a current source. The first end of the current source is connected to the drain and the gate of the transistor M1, and the second end is connected to the ground. The transistor M1 and the transistor M2 form a current mirror. The current source provides a reference current for the transistor M1. The transistor M2 replicates the reference current of the transistor M1 and converts the reference current into a reference voltage.

7. The input pair circuit according to claim 6, characterized in that The input pair of transistors also includes a capacitor C1, a resistor R1, a capacitor C2, and a resistor R2; the control end of the first transistor M3 is connected to the input signal VIN1, the control end of the second transistor M4 is connected to the input signal VIN2, the capacitor C1 and the resistor R1 form an R1C1 parallel circuit, the capacitor C2 and the resistor R2 form an R2C2 parallel circuit, one end of the R1C1 parallel circuit is coupled to the gate of the first transistor M3, and the other end is grounded, and one end of the R2C2 parallel circuit is coupled to the gate of the second transistor M4, and the other end is grounded.

8. The input pair circuit according to claim 9, characterized in that The output circuit includes a transistor M5 and a transistor M6, wherein the gates of the transistor M5 and the transistor M6 are connected to each other, the source terminals and the body terminals of the transistor M5 and the transistor M6 are grounded, the transistor M5 and the transistor M6 form a current mirror, the drain and the gate of the transistor M5 are connected to the drain of the first transistor M3, the drain of the transistor M6 is connected to the drain of the second transistor M4, the output node is located between the drain D of the second transistor M4 and the drain D of the transistor M6, and the output node is used to output the comparison result, which is the voltage difference V OUT of the input signals VIN1 and VIN2.

9. A DC-DC circuit, characterized in that: The invention comprises the input pair circuit as claimed in any one of claims 1 to 8.

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