Orthogonal divide-by-2 frequency divider based on injection locking and active inductance technology

Abstract

The invention discloses an orthogonal divide-by-2 frequency divider based on an injection locking and active inductance technology, and belongs to the field of divide-by-2 frequency dividers. The quadrature frequency divide-by-2 divider is formed by cascading D latches of active inductance loads of two tailless current sources. According to the invention, the structure of a divide-by-2 frequency divider of current mode logic is improved, an injection locking technology is introduced, a tail current source is removed, and an active inductor is used as a load, so that the orthogonal injection locking frequency divider is formed. While the power consumption is reduced, the problem that the working frequency range of the injection locking frequency divider is limited is solved.

Description

Technical Field

[0001] The invention belongs to the field of binary frequency dividers, and in particular relates to an orthogonal binary frequency divider based on injection locking and active inductance technology. Background Art

[0002] S-band (operating frequency 2-4GHz) RF wireless transceivers have a wide range of application scenarios in wireless communications, weather radar, satellite communications, and astronauts' extravehicular activity radio. In particular, there are a large number of civilian products in the 2.4GHz frequency band, such as wireless LAN, Bluetooth, etc.

[0003] Figure 1 The block diagram of a commonly used low-IF wireless receiver is shown, which includes an antenna, an RF filter, a low-noise amplifier, a local oscillator source, a divider, a quadrature mixer, and an image suppression filter. The input of the RF filter is connected to the antenna, and the output is connected to the low-noise amplifier; the input of the low-noise amplifier is connected to the output of the RF filter, and the output is connected to the upper plate of the DC-blocking capacitor; the output of the local oscillator source is connected to the divider; the input of the divider is connected to the local oscillator source, and the output is connected to the quadrature mixer; the input of the quadrature mixer is connected to the lower plate of the DC-blocking capacitor and the output of the divider, and the output is connected to the image suppression filter; the input of the image suppression filter is connected to the output of the quadrature mixer, and the output is connected to the subsequent circuit. In the design of RF receivers, two sets of differential local oscillator signals with a duty cycle of 25% and a phase difference of 90° are often required to drive the quadrature mixer, so as to achieve image suppression in the subsequent complex filtering circuit. The local oscillator signal generation circuit is shown in Figure 1. Figure 2 As shown, on the left side of the figure, two D latches are used to divide the input clock signal by 2 and generate a four-phase local oscillator signal with a phase difference of 90° and a duty cycle of 50%; then, a non-overlapping 25% duty cycle orthogonal local oscillator signal is obtained through the logic gate processing on the right side of the figure. Figure 2The specific circuit structure is as follows: CKP and CKN are the input local oscillator source differential signals, where CKP connects the clock trigger positive terminal of D latch 1 and the clock trigger negative terminal of D latch 2; CKN connects the clock trigger negative terminal of D latch 1 and the clock trigger positive terminal of D latch 2; the output positive terminal of D latch 1 is connected to the input positive terminal of D latch 2, and the connection is named "DIV2_IP"; the output negative terminal of D latch 1 is connected to the input negative terminal of D latch 2, and the connection is named "DIV2_IN"; the output positive terminal of D latch 2 is connected to the input negative terminal of D latch 1, and the connection is named "DIV2_QP"; the output negative terminal of D latch 2 is connected to the input positive terminal of D latch 2, and the connection is named "DIV2_QN". DIV2_IP, DIV2_IN, DIV2_QP and DIV2_QN are orthogonal clock signals with a duty cycle of 50% after being divided by 2. DIV2_IP, DIV2_IN, DIV2_QP and DIV2_QN generate non-overlapping 25% duty cycle local oscillator signals through a clock logic processing circuit composed of four groups of NAND gates and NOT gates. DIV2_IP and DIV2_QN are respectively connected to the two inputs of the NAND gate, and the output of the NAND gate is connected to the NOT gate, and finally the output is LO_IP. DIV2_IN and DIV2_QP are respectively connected to the two inputs of the NAND gate, and the output of the NAND gate is connected to the NOT gate, and finally the output is LO_IN. DIV2_QP and DIV2_IP are respectively connected to the two inputs of the NAND gate, and the output of the NAND gate is connected to the NOT gate, and finally the output is LO_QP. DIV2_QN and DIV2_IN are respectively connected to the two inputs of the NAND gate, and the output of the NAND gate is connected to the NOT gate, and finally the output is LO_QN. Finally, the four-phase local oscillator signals LO_IP, LO_IN, LO_QP and LO_QN with a duty cycle of 25% are generated for controlling the orthogonal mixer.

[0004] For fully integrated RF wireless receivers on a chip, the traditional solution is to design the on-chip local oscillator source to be twice the frequency of the required orthogonal signal, generate an orthogonal local oscillator signal through a two-way divider, and drive the mixer. This solution improves integration while also avoiding the frequency pulling problem.

[0005] but Figure 2The maximum operating frequency of the binary divider composed of two D latches is largely limited by the process. It is difficult to achieve signal division above 4GHz in the standard 130nm CMOS process. If the D latch of current mode logic (CML) with resistors as loads is used, although the operating frequency can be effectively increased, it requires very high power consumption. Some scholars have applied injection locking technology on the basis of current mode logic to achieve the division of signals up to 19GHz at the 120nm process node, but the power consumption has reached 66mW0. Some scholars have also added passive inductive loads to current mode logic and used injection locking technology to further increase the operating frequency, achieving the division of signals up to 38GHz with a power consumption of only 12mW0, but the operating frequency range is limited, and the on-chip inductor requires thick metal process support, occupies a large area, and has a high cost. Therefore, some scholars have proposed a compromise solution between area, power consumption and operating frequency range, that is, using active inductors as the load of current mode logic and using injection locking technology to achieve frequency division of signals up to 20GHz with a power consumption of only 4.3mW0.

[0006] In summary, the prior art has the following defects:

[0007] 1. In the prior art, if the divider adopts a current mode structure with a resistor as the load, a higher operating frequency can only be achieved at the cost of high power consumption, and the cascade between D latches needs to be carefully considered. It is not suitable for application scenarios with low power supply voltage, and the design process is relatively complicated.

[0008] 2. In the prior art, if the binary divider adopts a current mode structure with a passive inductive load, although the operating frequency can be effectively increased, the high power consumption problem is still severe, and due to the addition of passive inductance, the chip will occupy a larger area.

[0009] 3. In the prior art, if the binary divider adopts a current mode structure with a passive inductive load and uses injection locking technology, although it can further increase the operating frequency and alleviate the high power consumption problem, the operating frequency range is limited, and it is not suitable for standard CMOS technology, and the chip area is difficult to reduce.

[0010] 4. In the prior art, if the divider adopts a current mode structure with active inductive load and uses injection locking technology, it can simultaneously expand the operating frequency range and alleviate the high power consumption problem, effectively reducing the chip area. However, due to the existence of tail current, it is not suitable for low power supply voltage applications, and the active inductor constructed is not symmetrical, which is not conducive to generating differential signals.

[0011] The technical problems to be solved by the binary frequency divider in the prior art can be summarized as follows:

[0012] 1. The divider needs to operate at a higher frequency and achieve a wider operating frequency range.

[0013] 2. It is necessary to construct an active inductor that can provide a differential inductive load, improve the symmetry of the divider, simplify its design process, and reduce the design freedom.

[0014] 3. As the chip power supply voltage gradually decreases, application scenarios suitable for low power supply voltage are needed.

[0015] 4. High power consumption needs to be avoided.

[0016] 5. Reduce chip area and reduce costs.

[0017] 6. It can be produced using standard CMOS technology, reducing process requirements and reducing costs.

[0018] References are as follows:

[0019] [1]H..-D.Wohlmuth,D.Kehrer and W.Simburger,"A high sensitivitystatic2:1frequency divider up to 19GHz in 120nm CMOS,"2002IEEE RadioFrequency Integrated Circuits(RFIC)Symposium.Digest of Papers(Cat.No.02CH37280), Seattle, WA, USA, 2002, pp.231-234, doi:10.1109 / RFIC.2002.1012038.

[0020] [2]U.Singh and MMGreen, "High-frequency CML clock dividers in 0.13- / spl mu / m CMOS operating up to 38GHz," in IEEE Journal of Solid-State Circuits, vol.40, no.8, pp.1658-1661, Aug.2005, doi:10.1109 / JSSC.2005.852420.keywords:

[0021] [3] C.Zhou, L.Zhang, L.Zhang, Y.Wang, Z.Yu and H.Qian, "Injection-Locking-Based Power and Speed ​​Optimization of CML Dividers," in IEEE Transactions onCircuits and Systems II:Express Briefs, vol.58, no.9, pp.565-569, Sept.2011, doi:10.1109 / TCCSII.2011.2161163. Summary of the invention

[0022] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide an orthogonal binary frequency divider based on injection locking and active inductance technology. The present invention intends to adopt a new way of constructing a differential active inductor and remove the tail current source to avoid high power consumption and large area, and is suitable for low power supply voltage and can be applied to S-band receiver systems.

[0023] The specific technical solutions adopted by the present invention are as follows:

[0024] An orthogonal binary frequency divider based on injection locking and active inductance technology is formed by cascading two D latches with active inductance loads without tail current sources;

[0025] The two D latches have the same structure, and each D latch is composed of a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first resistor and a second resistor;

[0026] One end of the first resistor and the second resistor are both connected to the power supply, the other end of the first resistor is connected to the drain of the first NMOS tube and the gate of the second NMOS tube, and the other end of the second resistor is connected to the drain of the second NMOS tube and the gate of the first NMOS tube;

[0027] The source of the first NMOS tube serves as the first connection terminal, and is connected to the source of the third NMOS tube, the drain of the fourth NMOS tube, the drain of the fifth NMOS tube, and the gate of the sixth NMOS tube;

[0028] The source of the second NMOS tube serves as the second terminal and is connected to the drain of the third NMOS tube, the drain of the sixth NMOS tube, the drain of the seventh NMOS tube and the gate of the fifth NMOS tube;

[0029] The gate of the fourth NMOS tube serves as the third terminal, the gate of the seventh NMOS tube serves as the fourth terminal, and the source of the fourth NMOS tube, the source of the fifth NMOS tube, the source of the sixth NMOS tube, and the source of the seventh NMOS tube are all grounded;

[0030] The first terminal of the first D latch is connected to the third terminal of the second D latch through the first connection line, the second terminal of the first D latch is connected to the fourth terminal of the second D latch through the second connection line, the third terminal of the first D latch is connected to the second terminal of the second D latch through the third connection line, and the fourth terminal of the first D latch is connected to the first terminal of the second D latch through the fourth connection line;

[0031] The gates of the third NMOS tubes in the two D latches are respectively used to input a pair of local oscillator source differential signals.

[0032] Preferably, the aspect ratio of the first NMOS tube and the second NMOS tube is 40um / 130nm.

[0033] Preferably, the aspect ratio of the third NMOS tube is 32um / 130nm.

[0034] Preferably, the aspect ratio of the fourth NMOS tube and the seventh NMOS tube is 32um / 130nm.

[0035] Preferably, the aspect ratio of the fifth NMOS tube and the sixth NMOS tube is 80um / 130nm.

[0036] Preferably, the first resistor and the second resistor are P-well polysilicon resistors.

[0037] Preferably, the resistance of the first resistor and the second resistor is 120Ω.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] 1. The current mode structure with resistor as load in the prior art has high power consumption, requires high power supply voltage, and needs to carefully consider the cascade of D latch. However, the present invention removes the tail current source, is suitable for lower power supply voltage, simplifies the output common mode level design of D latch, and uses injection locking technology to reduce power consumption.

[0040] 2. Although the current mode structure with passive inductance as load in the prior art significantly improves the operating frequency, the high power consumption problem is still severe, and thick metal process support is required, and the chip will occupy a larger area. The present invention uses resistors and field effect transistors to form active inductors, which increases the operating frequency to a certain extent, saves area, and uses injection locking technology to reduce power consumption, which is suitable for standard CMOS process.

[0041] 3. The current mode structure of the passive inductive load using injection locking technology in the prior art can further increase the operating frequency and alleviate the high power consumption problem, but the operating frequency range is limited and the chip area is difficult to reduce. The present invention uses resistors and field effect transistors to form an active inductor, which expands the operating frequency range while saving a large amount of chip area, and is suitable for standard CMOS technology, reducing the requirements for the process.

[0042] 4. The current mode structure of active inductive load using injection locking technology in the prior art can simultaneously expand the operating frequency range and alleviate the high power consumption problem, effectively reducing the chip area. However, due to the existence of tail current, it is not suitable for low power supply voltage applications, and the constructed active inductor is not symmetrical enough, which is not conducive to generating differential signals. The active inductor used in the present invention is more symmetrical, and the tail current source is removed, which is suitable for low power supply voltage applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a block diagram of a low intermediate frequency wireless receiver;

[0044] Figure 2 A 25% duty cycle clock signal generating circuit;

[0045] Figure 3 The orthogonal binary frequency divider proposed by the present invention;

[0046] Figure 4 The device parameters for the specific implementation of the orthogonal binary divider;

[0047] Figure 5 The simulation results of the orthogonal binary frequency divider proposed by the present invention;

[0048] Figure 6 Circuit simulation results are generated for a 25% duty cycle clock signal. DETAILED DESCRIPTION

[0049] In order to make the above-mentioned purpose, features and advantages of the present invention more obvious and easy to understand, the specific implementation mode of the present invention is described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The technical features in each embodiment of the present invention can be combined accordingly without conflicting with each other.

[0050] In the description of the present invention, it is to be understood that when an element is considered to be "connected" to another element, it may be directly connected to the other element or indirectly connected, that is, there are intermediate elements. On the contrary, when an element is said to be "directly" connected to another element, there are no intermediate elements.

[0051] In the description of the present invention, it should be understood that the terms "first" and "second" are only used for the purpose of distinguishing descriptions, and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features.

[0052] In order to overcome the difficulty of compromising the operating frequency range and power consumption of a binary divider in current receiver circuit design, the present invention provides an orthogonal binary divider based on injection locking and active inductor technology. The device improves the binary divider structure of current mode logic, introduces injection locking technology, removes the tail current source, and uses active inductance as a load to form an orthogonal injection locked divider. While reducing power consumption, it solves the problem of limited operating frequency range of the injection locked divider.

[0053] The orthogonal binary frequency divider based on injection locking and active inductance technology is cascaded by two D latches (which can also be regarded as oscillators) with active inductance loads without tail current sources. The two D latches have the same structure, and the components of each D latch include 2 resistors and 7 MOS tubes, among which the 7 MOS tubes are all standard N-type MOS tubes. Figure 3As shown, in a preferred embodiment of the present invention, 2 resistors and 7 MOS tubes are completely identical and symmetrical in two D latches. In each D latch, one end of the first resistor and the second resistor are connected to the power supply VDD, the other end of the first resistor is connected to the drain of the first NMOS tube and the gate of the second NMOS tube, and the other end of the second resistor is connected to the drain of the second NMOS tube and the gate of the first NMOS tube; the source of the first NMOS tube serves as the first wiring terminal, and is connected to the source of the third NMOS tube, the drain of the fourth NMOS tube, the drain of the fifth NMOS tube, and the gate of the sixth NMOS tube; the source of the second NMOS tube serves as the second wiring terminal, and is connected to the drain of the third NMOS tube, the drain of the sixth NMOS tube, the drain of the seventh NMOS tube, and the gate of the fifth NMOS tube; the gate of the fourth NMOS tube serves as the third wiring terminal, and the gate of the seventh NMOS tube serves as the fourth wiring terminal. The gate of the NMOS tube serves as the fourth terminal, and the source of the fourth NMOS tube, the source of the fifth NMOS tube, the source of the sixth NMOS tube and the source of the seventh NMOS tube are all grounded; the first terminal of the first D latch is connected to the third terminal of the second D latch through the first connecting line, the second terminal of the first D latch is connected to the fourth terminal of the second D latch through the second connecting line, the third terminal of the first D latch is connected to the second terminal of the second D latch through the third connecting line, and the fourth terminal of the first D latch is connected to the first terminal of the second D latch through the fourth connecting line; the gates of the third NMOS tubes in the two D latches are respectively used to input a pair of local oscillator source differential signals, the positive signal is input to the gate of the third NMOS tube in the first D latch, and the negative signal is input to the gate of the third NMOS tube in the second D latch.

[0054] exist Figure 3In the figure, for the convenience of description, the seven MOS tubes are numbered differently, as follows: the first NMOS tube (called NMOS tube M1 in the first D latch and NMOS tube M3 in the second D latch), the second NMOS tube (called NMOS tube M2 in the first D latch and NMOS tube M4 in the second D latch), the third NMOS tube (called NMOS tube M13 in the first D latch and NMOS tube M14 in the second D latch), the fourth NMOS tube (called NMOS tube M5 in the first D latch and NMOS tube M9 in the second D latch), the fifth NMOS tube (called NMOS tube M16 in the first D latch and NMOS tube M17 in the second D latch), the fifth NMOS tube (called NMOS tube M18 in the first D latch and NMOS tube M19 in the second D latch), the fifth NMOS tube (called NMOS tube M20 in the first D latch and NMOS tube M21 in the second D latch), the fifth NMOS tube (called NMOS tube M21 in the first D latch and NMOS tube M22 in the second D latch), the fifth NMOS tube (called NMOS tube M22 in the first D latch and NMOS tube M23 in the second D latch), the fifth NMOS tube (called NMOS tube M23 in the first D latch and NMOS tube M24 in the second D latch), the fifth NMOS tube (called NMOS tube M24 in the first D latch and NMOS tube M25 in the second D latch), the fifth NMOS tube (called NMOS tube M25 in the first D latch and NMOS tube M26 in the second D latch), the fifth NMOS tube (called NMOS tube M26 in the first D latch and NMOS tube M27 in the second D latch), the fifth NMOS tube (called NMOS tube M27 in the first D latch and NMOS tube M28 in the second D latch), the fifth NMOS tube (called NMOS tube M29 in the first D latch and NMOS tube M30 in the second D latch), the fifth NMOS tube (called NMOS tube M31 in the first D latch and NMOS tube M32 in the second OS transistor (called NMOS transistor M6 in the first D latch, called NMOS transistor M10 in the second D latch), the sixth NMOS transistor (called NMOS transistor M7 in the first D latch, called NMOS transistor M11 in the second D latch), the seventh NMOS transistor (called NMOS transistor M8 in the first D latch, called NMOS transistor M12 in the second D latch), the two resistors are numbered as follows: the first resistor (called resistor R1 in the first D latch, called resistor R3 in the second D latch), the second resistor (called resistor R2 in the first D latch, called resistor R4 in the second D latch). The first connecting line, the second connecting line, the third connecting line, and the fourth connecting line are respectively recorded as DIV2_IP, DIV2_IN, DIV2_QN, and DIV2_QP.

[0055] thus, Figure 3 The cascade relationship of the two D latches is as follows:

[0056] The positive ends of the resistors R1, R2, R3 and R4 are connected to the power supply VDD, and the negative ends are connected to the drains of the NMOS tubes M1, M2, M3 and M4 and the gates of the NMOS tubes M2, M1, M4 and M3 respectively.

[0057] The source of the NMOS tube M1 is connected to the source of the NMOS tube M13, the drains of the NMOS tube M5 and the NMOS tube M6, and is connected to DIV2_IP; the source of the NMOS tube M2 is connected to the drain of the NMOS tube M13, the drains of the NMOS tube M7 and the NMOS tube M8, and is connected to DIV2_IN; the source of the NMOS tube M3 is connected to the source of the NMOS tube M14, the drains of the NMOS tube M9 and the NMOS tube M10, and is connected to DIV2_QP; the source of the NMOS tube M4 is connected to the drain of the NMOS tube M13, the drains of the NMOS tube M11 and the NMOS tube M12, and is connected to DIV2_QN.

[0058] The gate of NMOS tube M5 is connected to DIV2_QN, and the source is grounded; the gate of NMOS tube M6 is connected to DIV2_IN, and the source is grounded; the gate of NMOS tube M7 is connected to DIV2_IP, and the source is grounded; the gate of NMOS tube M8 is connected to DIV2_QP, and the source is grounded; the gate of NMOS tube M9 is connected to DIV2_IP, and the source is grounded; the gate of NMOS tube M10 is connected to DIV2_QN, and the source is grounded; the gate of NMOS tube M11 is connected to DIV2_QP, and the source is grounded; the gate of NMOS tube M12 is connected to DIV2_IN, and the source is grounded. In a pair of local oscillator source differential signals, the positive signal CKP is input to the gate of NMOS tube M13 in the first D latch, and the negative signal CKN is input to the gate of NMOS tube M14 in the second D latch.

[0059] In the above-mentioned orthogonal binary divider based on injection locking and active inductance technology, M1, M2, R1, R2 and M3, M4, R3, R4 respectively form two differential active inductance loads, and M6, M7 and M10, M11 are used to provide negative resistance, so that the D latch can self-resonate without external input. M5, M8 and M9, M12 form feedback, respectively convert the output voltage of this stage into current and inject it into the other stage in proportion, driving the two-stage D latch to generate four signals with a phase difference of 90°. M13 and M14 are injectors, which convert the input signal into current and inject it into the D latch, and at the same time mix it with the self-resonance signal of the D latch, and finally the output is stabilized at half the frequency of the input signal to achieve binary division.

[0060] Bundle Figure 3 The divider-by-two replacement shown Figure 2 In the 25% duty cycle clock signal generating circuit shown in the figure, the input CKP, CKN and the output DIV2_IP, DIV2_IN, DIV2_QP, DIV2_QN are all in one-to-one correspondence. After the four signals with 90° phase difference pass through the clock logic processing circuit, four 25% duty cycle signal outputs are obtained, namely LO_IP, LO_IN, LO_QP, LO_QN.

[0061] In order to better demonstrate the specific technical effect of the two-way frequency divider of the present invention, Figure 3 The circuit structure shown is implemented in 130nm CMOS process node. Figure 4As shown, the parameters of each device are as follows: the aspect ratio of the first NMOS tube M1 and the second NMOS tube M2 is 40um / 130nm. The aspect ratio of the third NMOS tube M13 is 32um / 130nm. The aspect ratio of the fourth NMOS tube M5 and the seventh NMOS tube M8 is 32um / 130nm. The aspect ratio of the fifth NMOS tube M6 and the sixth NMOS tube M7 is 80um / 130nm. The first resistor R1 and the second resistor R2 use P-well polysilicon resistors, and the resistance of the first resistor R1 and the second resistor R2 is 120Ω. The total area occupied by the core circuit of the specifically implemented two-way divider is 3690um 2 (length 82um*width 45um), the input frequency range based on post-simulation is 3GHz-9.5GHz, and when the input frequency reaches the maximum under 1.2V voltage supply, the typical power consumption is 11.5mW. When inputting 6GHz differential signal, the two-way divider outputs four 90° phase difference signals as follows Figure 5 As shown in the figure, the four 25% duty cycle signals after the clock logic processing circuit are as follows Figure 6 shown.

[0062] In summary, the present invention proposes an orthogonal binary divider structure with injection locking without tail current source. After inputting a signal of a certain frequency, four signals with a 90° phase difference of 1 / 2 of the input signal frequency can be directly obtained. The binary divider can achieve low power consumption and low voltage while expanding the operating frequency range.

[0063] The above-described embodiment is only a preferred solution of the present invention, but it is not intended to limit the present invention. A person skilled in the relevant technical field may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, any technical solution obtained by equivalent replacement or equivalent transformation falls within the protection scope of the present invention.

Claims

1. An orthogonal binary frequency divider based on injection locking and active inductance technology, characterized in that: It is composed of two D latches cascaded with active inductive load without tail current source; The two D latches have the same structure, and each D latch is composed of a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first resistor and a second resistor; One end of the first resistor and the second resistor are both connected to the power supply, the other end of the first resistor is connected to the drain of the first NMOS tube and the gate of the second NMOS tube, and the other end of the second resistor is connected to the drain of the second NMOS tube and the gate of the first NMOS tube; The source of the first NMOS tube serves as the first connection terminal, and is connected to the source of the third NMOS tube, the drain of the fourth NMOS tube, the drain of the fifth NMOS tube, and the gate of the sixth NMOS tube; The source of the second NMOS tube serves as the second terminal and is connected to the drain of the third NMOS tube, the drain of the sixth NMOS tube, the drain of the seventh NMOS tube and the gate of the fifth NMOS tube; The gate of the fourth NMOS tube serves as the third terminal, the gate of the seventh NMOS tube serves as the fourth terminal, and the source of the fourth NMOS tube, the source of the fifth NMOS tube, the source of the sixth NMOS tube, and the source of the seventh NMOS tube are all grounded; The first terminal of the first D latch is connected to the third terminal of the second D latch through the first connection line, the second terminal of the first D latch is connected to the fourth terminal of the second D latch through the second connection line, the third terminal of the first D latch is connected to the second terminal of the second D latch through the third connection line, and the fourth terminal of the first D latch is connected to the first terminal of the second D latch through the fourth connection line; The gates of the third NMOS tubes in the two D latches are respectively used to input a pair of local oscillator source differential signals.

2. The orthogonal binary frequency divider based on injection locking and active inductance technology as claimed in claim 1, characterized in that: The aspect ratio of the first NMOS tube and the second NMOS tube is 40um / 130nm.

3. The orthogonal binary frequency divider based on injection locking and active inductance technology as claimed in claim 1, characterized in that: The aspect ratio of the third NMOS tube is 32um / 130nm.

4. The orthogonal binary frequency divider based on injection locking and active inductance technology as claimed in claim 1, characterized in that: The aspect ratio of the fourth NMOS tube and the seventh NMOS tube is 32um / 130nm.

5. The orthogonal binary frequency divider based on injection locking and active inductance technology as claimed in claim 1, characterized in that: The aspect ratio of the fifth NMOS tube and the sixth NMOS tube is 80um / 130nm.

6. The orthogonal binary frequency divider based on injection locking and active inductance technology as claimed in claim 1, characterized in that: The first resistor and the second resistor are P-well polysilicon resistors.

7. The orthogonal binary frequency divider based on injection locking and active inductance technology as claimed in claim 1, characterized in that: The resistance of the first resistor and the second resistor is 120Ω.

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