A quadrature frequency divider based on injection locking and active inductor technology

Abstract

The present invention discloses an orthogonal binary frequency divider based on injection locking and active inductor technology, belonging to the field of binary frequency dividers. The orthogonal binary frequency divider is composed of two cascaded D-type latches with active inductor loads and no tail current sources. The present invention improves the binary frequency divider structure of current mode logic by introducing injection locking technology, removing the tail current source, and using an active inductor as a load to form an orthogonal injection-locked frequency divider. The present invention solves the problem of the limited operating frequency range of injection-locked frequency dividers while reducing power consumption.

Description

Technical Field

[0001] The invention belongs to the field of binary frequency dividers, and in particular relates to an orthogonal binary frequency divider based on injection locking and active inductance technology. Background Art

[0002] S-band (operating frequency 2-4GHz) RF wireless transceivers have a wide range of application scenarios in wireless communications, weather radar, satellite communications, and astronauts' extravehicular activity radio. In particular, there are a large number of civilian products in the 2.4GHz frequency band, such as wireless LAN, Bluetooth, etc.

[0003] Figure 1 The block diagram of a commonly used low-IF wireless receiver is shown, which includes an antenna, RF filter, low-noise amplifier, local oscillator source, divider, quadrature mixer and image rejection filter. The input of the RF filter is connected to the antenna, and the output is connected to the low-noise amplifier; the input of the low-noise amplifier is connected to the output of the RF filter, and the output is connected to the upper plate of the DC-blocking capacitor; the output of the local oscillator source is connected to the divider; the input of the divider is connected to the local oscillator source, and the output is connected to the quadrature mixer; the input of the quadrature mixer is connected to the lower plate of the DC-blocking capacitor and the output of the divider, and the output is connected to the image rejection filter; the input of the image rejection filter is connected to the output of the quadrature mixer, and the output is connected to the subsequent circuit. In the design of RF receivers, two sets of differential local oscillator signals with a 25% duty cycle and a phase difference of 90° are often required to drive the quadrature mixer, so as to achieve image rejection in the subsequent complex filtering circuit. The local oscillator signal generation circuit is shown in Figure 2. Figure 2 As shown in the figure, on the left side, two D latches divide the input clock signal by 2 and generate four-phase local oscillator signals with a phase difference of 90° and a duty cycle of 50%. Then, through the logic gate processing on the right side of the figure, a non-overlapping 25% duty cycle orthogonal local oscillator signal is obtained. Figure 2The specific circuit structure is as follows: CKP and CKN are the input local oscillator differential signals, where CKP connects the positive clock trigger terminal of D-latch 1 and the negative clock trigger terminal of D-latch 2; CKN connects the negative clock trigger terminal of D-latch 1 and the positive clock trigger terminal of D-latch 2; the positive output terminal of D-latch 1 is connected to the positive input terminal of D-latch 2, and the connection is named "DIV2_IP"; the negative output terminal of D-latch 1 is connected to the negative input terminal of D-latch 2, and the connection is named "DIV2_IN"; the positive output terminal of D-latch 2 is connected to the negative input terminal of D-latch 1, and the connection is named "DIV2_QP"; the negative output terminal of D-latch 2 is connected to the positive input terminal of D-latch 2, and the connection is named "DIV2_QN". DIV2_IP, DIV2_IN, DIV2_QP, and DIV2_QN are quadrature clock signals with a duty cycle of 50% after being divided by 2. DIV2_IP, DIV2_IN, DIV2_QP, and DIV2_QN generate non-overlapping 25% duty cycle local oscillator signals through a clocked logic processing circuit consisting of four sets of NAND and NOT gates. DIV2_IP and DIV2_QN are connected to the two inputs of the NAND gates, with the outputs of the NAND gates connected to the NOT gates, ultimately outputting LO_IP. DIV2_IN and DIV2_QP are connected to the two inputs of the NAND gates, with the outputs of the NAND gates connected to the NOT gates, ultimately outputting LO_IN. DIV2_QP and DIV2_IP are connected to the two inputs of the NAND gates, with the outputs of the NAND gates connected to the NOT gates, ultimately outputting LO_QP. DIV2_QN and DIV2_IN are connected to the two inputs of the NAND gates, with the outputs of the NAND gates connected to the NOT gates, ultimately outputting LO_QN. This generates the four-phase local oscillator signals LO_IP, LO_IN, LO_QP, and LO_QN with a 25% duty cycle, which are used to control the quadrature mixer.

[0004] For fully integrated RF wireless receivers on a chip, the traditional approach is to design the on-chip local oscillator at twice the frequency of the required orthogonal signal. A divider-by-two frequency divider generates the orthogonal local oscillator signal to drive the mixer. This approach improves integration while also avoiding frequency pulling issues.

[0005] but Figure 2The maximum operating frequency of a two-way frequency divider composed of two D latches is largely limited by the process technology. It is difficult to achieve frequency division of signals above 4 GHz in a standard 130nm CMOS process. Using a current-mode logic (CML) D latch with a resistor as a load can effectively increase the operating frequency, but this comes at the expense of significant power consumption. Some researchers have applied injection locking technology to CML, achieving frequency division of signals up to 19 GHz at a 120nm process node, but with power consumption reaching 66 mW. Other researchers have added passive inductive loads to CML and used injection locking technology to further increase the operating frequency, achieving frequency division of signals up to 38 GHz with power consumption of only 12 mW. However, the operating frequency range is limited, and on-chip inductors require thick metallization, occupying a large area and resulting in high cost. Therefore, some scholars have proposed a compromise solution between area, power consumption and operating frequency range, that is, using active inductors as the load of current mode logic and using injection locking technology to achieve frequency division of signals up to 20GHz with a power consumption of only 4.3mW0.

[0006] In summary, the existing technology has the following defects:

[0007] 1. In the existing technology, if the binary divider adopts a current-mode structure with a resistor as the load, it has to pay the price of high power consumption in exchange for a higher operating frequency. In addition, the cascade connection between D latches needs to be carefully considered. It is not suitable for low power supply voltage application scenarios and the design process is relatively complicated.

[0008] 2. In the prior art, if the divider adopts a current mode structure with a passive inductive load, although it can effectively increase the operating frequency, the high power consumption problem remains severe, and the chip will occupy a larger area due to the addition of the passive inductor.

[0009] 3. In the existing technology, if the binary divider adopts a current mode structure with a passive inductive load and uses injection locking technology, although it can further increase the operating frequency and alleviate the high power consumption problem, the operating frequency range is limited, and it is not suitable for standard CMOS technology, and the chip area is also difficult to reduce.

[0010] 4. Existing dividers employing a current-mode structure with an active inductive load and injection-locking technology can simultaneously expand the operating frequency range and alleviate high power consumption, effectively reducing chip area. However, due to the presence of tail current, this approach is not suitable for low-supply voltage applications. Furthermore, the lack of symmetry in the active inductor structure hinders differential signal generation.

[0011] The technical problems to be solved by the binary frequency divider in the prior art can be summarized as follows:

[0012] 1. The divider needs to operate at a higher frequency and achieve a wider operating frequency range.

[0013] 2. It is necessary to construct an active inductor that can provide differential inductive load, improve the symmetry of the divider, simplify its design process, and reduce the design freedom.

[0014] 3. As the chip power supply voltage gradually decreases, it is necessary to be suitable for application scenarios with low power supply voltage.

[0015] 4. High power consumption issues need to be avoided.

[0016] 5. Reduce chip area and reduce costs.

[0017] 6. It can be produced using standard CMOS technology, reducing process requirements and costs.

[0018] References are as follows:

[0019] [1]H..-D.Wohlmuth,D.Kehrer and W.Simburger,"A high sensitivitystatic2:1frequency divider up to 19GHz in 120nm CMOS,"2002IEEE RadioFrequency Integrated Circuits(RFIC)Symposium.Digest of Papers(Cat.No.02CH37280), Seattle, WA, USA, 2002, pp.231-234, doi:10.1109 / RFIC.2002.1012038.

[0020] [2]U.Singh and MMGreen, "High-frequency CML clock dividers in 0.13- / spl mu / m CMOS operating up to 38GHz," in IEEE Journal of Solid-State Circuits, vol.40, no.8, pp.1658-1661, Aug.2005, doi:10.1109 / JSSC.2005.852420.keywords:

[0021] [3] C.Zhou, L.Zhang, L.Zhang, Y.Wang, Z.Yu and H.Qian, "Injection-Locking-Based Power and Speed ​​Optimization of CML Dividers," in IEEE Transactions onCircuits and Systems II:Express Briefs, vol.58, no.9, pp.565-569, Sept.2011, doi:10.1109 / TCCSII.2011.2161163. Summary of the Invention

[0022] The present invention aims to overcome the aforementioned shortcomings of the prior art and provide an orthogonal binary frequency divider based on injection locking and active inductor technology. This invention employs a novel method for constructing a differential active inductor and eliminates the tail current source, thus avoiding high power consumption and large area requirements. Furthermore, the invention is suitable for low supply voltages and can be applied to S-band receiver systems.

[0023] The specific technical solutions adopted in the present invention are as follows:

[0024] An orthogonal binary frequency divider based on injection locking and active inductance technology is cascaded by two D latches with active inductive loads and no tail current sources;

[0025] The two D latches have the same structure. Each D latch is composed of a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first resistor, and a second resistor.

[0026] One end of the first resistor and the second resistor are both connected to a power supply, the other end of the first resistor is connected to the drain of the first NMOS transistor and the gate of the second NMOS transistor, and the other end of the second resistor is connected to the drain of the second NMOS transistor and the gate of the first NMOS transistor;

[0027] The source of the first NMOS transistor serves as the first terminal and is connected to the source of the third NMOS transistor, the drain of the fourth NMOS transistor, the drain of the fifth NMOS transistor, and the gate of the sixth NMOS transistor;

[0028] The source of the second NMOS transistor serves as the second terminal and is connected to the drain of the third NMOS transistor, the drain of the sixth NMOS transistor, the drain of the seventh NMOS transistor, and the gate of the fifth NMOS transistor;

[0029] The gate of the fourth NMOS transistor serves as the third terminal, the gate of the seventh NMOS transistor serves as the fourth terminal, and the source of the fourth NMOS transistor, the source of the fifth NMOS transistor, the source of the sixth NMOS transistor, and the source of the seventh NMOS transistor are all grounded;

[0030] The first terminal of the first D latch is connected to the third terminal of the second D latch via a first connection line, the second terminal of the first D latch is connected to the fourth terminal of the second D latch via a second connection line, the third terminal of the first D latch is connected to the second terminal of the second D latch via a third connection line, and the fourth terminal of the first D latch is connected to the first terminal of the second D latch via a fourth connection line;

[0031] The gates of the third NMOS transistors in the two D latches are respectively used to input a pair of local oscillator source differential signals.

[0032] Preferably, the aspect ratio of the first NMOS transistor and the second NMOS transistor is 40 μm / 130 nm.

[0033] Preferably, the aspect ratio of the third NMOS transistor is 32um / 130nm.

[0034] Preferably, the aspect ratio of the fourth NMOS transistor and the seventh NMOS transistor is 32 um / 130 nm.

[0035] Preferably, the aspect ratio of the fifth NMOS transistor and the sixth NMOS transistor is 80 um / 130 nm.

[0036] Preferably, the first resistor and the second resistor are P-well polysilicon resistors.

[0037] Preferably, the resistance of the first resistor and the second resistor is 120Ω.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] 1. Current-mode structures using resistors as loads in the prior art consume high power, require a higher power supply voltage, and require careful consideration of the D-latch cascade. This invention, however, eliminates the tail current source, making it suitable for lower power supply voltages while simplifying the D-latch output common-mode level design. Furthermore, it employs injection locking technology to reduce power consumption.

[0040] 2. While existing current-mode structures using passive inductors as loads significantly increase operating frequencies, they still face significant power consumption challenges and require thick metallization, which increases chip area. This invention, however, employs active inductors composed of resistors and field-effect transistors, significantly increasing operating frequencies and saving area. Furthermore, it employs injection-locking technology to reduce power consumption and is suitable for standard CMOS processes.

[0041] 3. Current-mode structures with passive inductive loads using injection locking technology in existing technologies can further increase operating frequencies and alleviate high power consumption, but this limits the operating frequency range and makes it difficult to reduce chip area. The present invention, however, employs active inductors composed of resistors and field-effect transistors, extending the operating frequency range while saving significant chip area. Furthermore, it is compatible with standard CMOS processes, reducing process requirements.

[0042] 4. Current-mode structures with active inductive loads using injection-locking technology in the prior art can simultaneously expand the operating frequency range and alleviate high power consumption, effectively reducing chip area. However, due to the presence of tail current, these structures are not suitable for low-supply voltage applications. Furthermore, the resulting active inductor is not symmetrical, hindering differential signal generation. The active inductor used in the present invention is more symmetrical and eliminates the tail current source, making it suitable for low-supply voltage applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a block diagram of a low-intermediate-frequency wireless receiver;

[0044] Figure 2 A 25% duty cycle clock signal generating circuit;

[0045] Figure 3 The orthogonal two-way frequency divider proposed by the present invention;

[0046] Figure 4 Specific device parameters for the orthogonal binary divider;

[0047] Figure 5 The simulation results of the orthogonal two-way frequency divider proposed in the present invention are as follows;

[0048] Figure 6 Generate circuit simulation results for a 25% duty cycle clock signal. DETAILED DESCRIPTION

[0049] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The technical features in the various embodiments of the present invention can be combined accordingly without conflicting with each other.

[0050] In the description of the present invention, it should be understood that when an element is considered to be "connected" to another element, it can be directly connected to the other element or indirectly connected, that is, there are intermediate elements. On the contrary, when an element is said to be "directly" connected to another element, there are no intermediate elements.

[0051] In the description of the present invention, it should be understood that the terms "first" and "second" are used solely for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly specifying the number of technical features being described. Therefore, features defined as "first" or "second" may explicitly or implicitly include at least one of such features.

[0052] In order to overcome the difficulty of balancing the operating frequency range and power consumption of the binary divider in current receiver circuit design, the present invention provides an orthogonal binary divider based on injection locking and active inductor technology. The device improves the binary divider structure of current mode logic, introduces injection locking technology, removes the tail current source, and uses active inductance as a load to form an orthogonal injection locked divider. While reducing power consumption, it solves the problem of limited operating frequency range of the injection locked divider.

[0053] This orthogonal binary frequency divider based on injection locking and active inductance technology is composed of two D latches (which can also be regarded as oscillators) with active inductance loads and no tail current source. The two D latches have the same structure. Each D latch consists of two resistors and seven MOS transistors, of which the seven MOS transistors are standard N-type MOS transistors. Figure 3As shown, in a preferred embodiment of the present invention, the two resistors and the seven MOS transistors in the two D latches are completely identical and symmetrical. In each D latch, one end of the first resistor and the second resistor are both connected to the power supply VDD, the other end of the first resistor is connected to the drain of the first NMOS transistor and the gate of the second NMOS transistor, and the other end of the second resistor is connected to the drain of the second NMOS transistor and the gate of the first NMOS transistor; the source of the first NMOS transistor serves as the first terminal and is connected to the source of the third NMOS transistor, the drain of the fourth NMOS transistor, the drain of the fifth NMOS transistor, and the gate of the sixth NMOS transistor; the source of the second NMOS transistor serves as the second terminal and is connected to the drain of the third NMOS transistor, the drain of the sixth NMOS transistor, the drain of the seventh NMOS transistor, and the gate of the fifth NMOS transistor; the gate of the fourth NMOS transistor serves as the third terminal, and the gate of the seventh NMOS transistor serves as the fourth terminal. The gate of the NMOS transistor serves as the fourth terminal, and the sources of the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, and the seventh NMOS transistor are all grounded; the first terminal of the first D latch is connected to the third terminal of the second D latch via a first connecting line, the second terminal of the first D latch is connected to the fourth terminal of the second D latch via a second connecting line, the third terminal of the first D latch is connected to the second terminal of the second D latch via a third connecting line, and the fourth terminal of the first D latch is connected to the first terminal of the second D latch via a fourth connecting line; the gates of the third NMOS transistors in the two D latches are respectively used to input a pair of local oscillator source differential signals, with the positive signal input to the gate of the third NMOS transistor in the first D latch, and the negative signal input to the gate of the third NMOS transistor in the second D latch.

[0054] exist Figure 3In the figure, for the convenience of description, the seven MOS tubes are numbered differently, as follows: the first NMOS tube (called NMOS tube M1 in the first D latch, and NMOS tube M3 in the second D latch), the second NMOS tube (called NMOS tube M2 in the first D latch, and NMOS tube M4 in the second D latch), the third NMOS tube (called NMOS tube M13 in the first D latch, and NMOS tube M14 in the second D latch), the fourth NMOS tube (called NMOS tube M5 in the first D latch, and NMOS tube M9 in the second D latch), the fifth NMOS tube (called NMOS tube M16 in the first D latch, and NMOS tube M17 in the second D latch), the fifth NMOS tube (called NMOS tube M18 in the first D latch, and NMOS tube M19 in the second D latch), the sixth NMOS tube (called NMOS tube M20 in the first D latch, and NMOS tube M21 in the second D latch), the seventh NMOS tube (called NMOS tube M30 in the first D latch, and NMOS tube M31 in the second D latch), the eighth NMOS tube (called NMOS tube M31 in the first D latch, and NMOS tube M32 in the second D latch), the eighth NMOS tube (called NMOS tube M32 in the first D latch, and NMOS tube M33 in the second D latch), the eighth NMOS tube (called NMOS tube M33 in the first D latch, and NMOS tube M34 in the second D latch), the eighth NMOS tube (called NMOS tube M34 in the first D latch, and NMOS tube M35 in the second D latch), the eighth NMOS tube (called NMOS tube M35 in the first D latch, and NMOS tube M36 in the second D latch), the eighth NMOS tube (called NMOS tube M35 in the first D latch, and NMOS tube M37 in the second D latch), the eighth NMOS tube (called NMOS tube M36 in the first D latch, and NMOS tube M37 in the second D latch), the eighth NMOS tube (called NMOS tube M37 The OS transistor (called NMOS transistor M6 in the first D latch and NMOS transistor M10 in the second D latch), the sixth NMOS transistor (called NMOS transistor M7 in the first D latch and NMOS transistor M11 in the second D latch), the seventh NMOS transistor (called NMOS transistor M8 in the first D latch and NMOS transistor M12 in the second D latch), and the two resistors are numbered as follows: the first resistor (called resistor R1 in the first D latch and resistor R3 in the second D latch) and the second resistor (called resistor R2 in the first D latch and resistor R4 in the second D latch). The first connecting line, the second connecting line, the third connecting line, and the fourth connecting line are respectively marked as DIV2_IP, DIV2_IN, DIV2_QN, and DIV2_QP.

[0055] thus, Figure 3 The cascade relationship of the two D latches is as follows:

[0056] The positive ends of the resistors R1, R2, R3 and R4 are connected to the power supply VDD, and the negative ends are connected to the drains of the NMOS transistors M1, M2, M3 and M4 and the gates of the NMOS transistors M2, M1, M4 and M3 respectively.

[0057] The source of the NMOS transistor M1 is connected to the source of the NMOS transistor M13, the drains of the NMOS transistors M5 and M6, and is connected to DIV2_IP; the source of the NMOS transistor M2 is connected to the drain of the NMOS transistor M13, the drains of the NMOS transistors M7 and M8, and is connected to DIV2_IN; the source of the NMOS transistor M3 is connected to the source of the NMOS transistor M14, the drains of the NMOS transistors M9 and M10, and is connected to DIV2_QP; the source of the NMOS transistor M4 is connected to the drain of the NMOS transistor M13, the drains of the NMOS transistors M11 and M12, and is connected to DIV2_QN.

[0058] The gate of NMOS transistor M5 is connected to DIV2_QN, and its source is grounded. The gate of NMOS transistor M6 is connected to DIV2_IN, and its source is grounded. The gate of NMOS transistor M7 is connected to DIV2_IP, and its source is grounded. The gate of NMOS transistor M8 is connected to DIV2_QP, and its source is grounded. The gate of NMOS transistor M9 is connected to DIV2_IP, and its source is grounded. The gate of NMOS transistor M10 is connected to DIV2_QN, and its source is grounded. The gate of NMOS transistor M11 is connected to DIV2_QP, and its source is grounded. The gate of NMOS transistor M12 is connected to DIV2_IN, and its source is grounded. In a pair of local oscillator source differential signals, the positive signal CKP is input to the gate of NMOS transistor M13 in the first D latch, and the negative signal CKN is input to the gate of NMOS transistor M14 in the second D latch.

[0059] In the aforementioned orthogonal binary divider based on injection locking and active inductor technology, M1, M2, R1, R2 and M3, M4, R3, R4 form two differential active inductive loads, respectively. M6, M7 and M10, M11 provide negative resistance, enabling the D-type latch to self-resonate without external input. M5, M8 and M9, M12 form feedback, converting the output voltage of each stage into a current and injecting it proportionally into the other stage, driving the two-stage D-type latch to generate four signals with a 90° phase difference. M13 and M14 are injectors, converting the input signal into a current and injecting it into the D-type latch. This current is then mixed with the D-type latch's self-resonant signal, ultimately stabilizing the output at half the input signal frequency, achieving binary frequency division.

[0060] Bundle Figure 3 The divider shown replaces the Figure 2 In the 25% duty cycle clock signal generation circuit shown, the divider's inputs CKP and CKN correspond to the outputs DIV2_IP, DIV2_IN, DIV2_QP, and DIV2_QN. After the four signals, each with a 90° phase difference, pass through the clock logic processing circuit, four 25% duty cycle output signals, LO_IP, LO_IN, LO_QP, and LO_QN, are generated.

[0061] In order to better demonstrate the specific technical effects of the two-way frequency divider of the present invention, Figure 3 The circuit structure shown is implemented in 130nm CMOS process node. Figure 4As shown, the parameters of each device are as follows: the aspect ratio of the first NMOS tube M1 and the second NMOS tube M2 is 40um / 130nm. The aspect ratio of the third NMOS tube M13 is 32um / 130nm. The aspect ratio of the fourth NMOS tube M5 and the seventh NMOS tube M8 is 32um / 130nm. The aspect ratio of the fifth NMOS tube M6 and the sixth NMOS tube M7 is 80um / 130nm. The first resistor R1 and the second resistor R2 use P-well polysilicon resistors, and the resistance of the first resistor R1 and the second resistor R2 is 120Ω. The total area occupied by the core circuit of the specifically implemented two-way divider is 3690um 2 (82um long * 45um wide), based on the post-simulation input frequency range of 3GHz-9.5GHz, under 1.2V voltage supply when the input frequency reaches the maximum, the typical power consumption is 11.5mW. When the 6GHz differential signal is input, the two-way divider outputs four 90° phase difference signals as follows Figure 5 As shown, the four 25% duty cycle signals after the clock logic processing circuit are as follows Figure 6 shown.

[0062] In summary, the present invention proposes an injection-locked, tail-current-free quadrature divider structure that, upon inputting a signal of a given frequency, directly generates four signals with a 90° phase difference at half the input frequency. This divider can achieve low power consumption and low voltage while extending the operating frequency range.

[0063] The embodiment described above is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Persons skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, any technical solution obtained by equivalent substitution or equivalent transformation falls within the scope of protection of the present invention.

Claims

1. An orthogonal binary frequency divider based on injection locking and active inductance technology, characterized in that: It is composed of two D latches with active inductive load without tail current source in cascade; The two D latches have the same structure. Each D latch is composed of a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first resistor, and a second resistor. One end of the first resistor and the second resistor are both connected to a power supply, the other end of the first resistor is connected to the drain of the first NMOS transistor and the gate of the second NMOS transistor, and the other end of the second resistor is connected to the drain of the second NMOS transistor and the gate of the first NMOS transistor; The source of the first NMOS transistor serves as the first terminal and is connected to the source of the third NMOS transistor, the drain of the fourth NMOS transistor, the drain of the fifth NMOS transistor, and the gate of the sixth NMOS transistor; The source of the second NMOS transistor serves as the second terminal and is connected to the drain of the third NMOS transistor, the drain of the sixth NMOS transistor, the drain of the seventh NMOS transistor, and the gate of the fifth NMOS transistor; The gate of the fourth NMOS transistor serves as the third terminal, the gate of the seventh NMOS transistor serves as the fourth terminal, and the source of the fourth NMOS transistor, the source of the fifth NMOS transistor, the source of the sixth NMOS transistor, and the source of the seventh NMOS transistor are all grounded; The first terminal of the first D latch is connected to the third terminal of the second D latch via a first connection line, the second terminal of the first D latch is connected to the fourth terminal of the second D latch via a second connection line, the third terminal of the first D latch is connected to the second terminal of the second D latch via a third connection line, and the fourth terminal of the first D latch is connected to the first terminal of the second D latch via a fourth connection line; The gates of the third NMOS transistors in the two D latches are respectively used to input a pair of local oscillator source differential signals.

2. The orthogonal two-way frequency divider based on injection locking and active inductance technology according to claim 1, characterized in that: The aspect ratio of the first NMOS transistor and the second NMOS transistor is 40 μm / 130 nm.

3. The orthogonal two-way frequency divider based on injection locking and active inductance technology according to claim 1, characterized in that: The aspect ratio of the third NMOS transistor is 32um / 130nm.

4. The orthogonal binary frequency divider based on injection locking and active inductance technology according to claim 1, wherein: The aspect ratio of the fourth NMOS transistor and the seventh NMOS transistor is 32 μm / 130 nm.

5. The orthogonal binary frequency divider based on injection locking and active inductance technology according to claim 1, wherein: The aspect ratio of the fifth NMOS transistor and the sixth NMOS transistor is 80 μm / 130 nm.

6. The orthogonal two-way frequency divider based on injection locking and active inductance technology according to claim 1, characterized in that: The first resistor and the second resistor are P-well polysilicon resistors.

7. The orthogonal two-way frequency divider based on injection locking and active inductance technology according to claim 1, characterized in that: The resistance of the first resistor and the second resistor is 120Ω.

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