Phase-locked loop reference clock duty ratio calibration circuit

Abstract

The invention discloses a phase-locked loop reference clock duty ratio calibration circuit, which relates to the technical field of signal frequency and phase control, and comprises a duty ratio detection control module and a duty ratio calibration module, the duty ratio detection control module is used for receiving a reference calibration clock output by the duty ratio calibration module and a high-speed calibration clock output by the phase-locked loop, and outputting a control code to the duty ratio calibration module; the duty ratio calibration module is used for receiving an input phase-locked loop reference clock signal and a control code, adjusting the duty ratio of the reference clock signal under the control of the control code, and outputting a reference calibration clock to the duty ratio detection control module and a frequency multiplier of the phase-locked loop. The input reference clock is calibrated, the duty ratio adjusting range is wide, the adjusting precision is high, the occupied area is small, and the structure is simple.

Description

Technical Field

[0001] The invention relates to the technical field of signal frequency and phase control, and in particular to a phase-locked loop reference clock duty cycle calibration circuit. Background Art

[0002] Low-spurious phase-locked loops are crucial in many application areas. They can provide signals with high frequency purity. Therefore, the design and implementation of low-spurious phase-locked loops has become an important research topic. There are many factors that cause phase-locked loop spurs, such as the duty cycle fluctuation of the reference clock multiplier, additional spurs introduced by unstable or unclean power supplies, spurs caused by multiple harmonic crosstalk of the clock signal, and current mismatch of the phase-locked loop charge pump. In order to reduce quantization noise, low-noise phase-locked loops usually use a frequency multiplier to multiply the frequency of the reference clock, so that the quantization noise will be moved to a high frequency and filtered out by the loop low-pass filter. Usually, the frequency multiplier is implemented using a delay unit and an XOR gate. When the duty cycle of the input reference clock is not 50%, the output duty cycle of the frequency multiplier will change alternately with the clock output and is not constant. This will increase the spurious output of the phase-locked loop.

[0003] For a phase-locked loop using a reference clock multiplier, when the duty cycle of the input reference clock differs greatly from 50%, the duty cycle of the multiplied reference clock will fluctuate periodically, resulting in spurious output of the phase-locked loop. Theoretical analysis shows that the closer the duty cycle of the input reference clock is to 50%, the smaller the output spurious output of the phase-locked loop. Therefore, duty cycle calibration of the input reference clock becomes the main solution to reduce the output spurious output of the phase-locked loop with a multiplier. The prior art usually uses analog closed-loop feedback to control the output node of the clock input inverter to charge and discharge current, and the adjustment range is limited. At the same time, due to the use of analog negative feedback loops and low-pass filters, it has the disadvantage of a large area. There is also a prior art method that uses an additional calibration PLL to adjust the duty cycle of the input reference clock. The disadvantage is that an additional calibration PLL design is added, and the structure is relatively complex. Summary of the invention

[0004] In view of the above defects or deficiencies in the prior art, the present invention provides a phase-locked loop reference clock duty cycle calibration circuit, which can realize feedback control of a duty cycle calibration module (DCC) only through a counter, a logic gate circuit and a finite state machine, thereby realizing calibration of an input reference clock. The present invention has the advantages of a wide duty cycle adjustment range, high precision, saving a large-area low-pass filter in an analog feedback loop, and no need for additional calibration of the PLL.

[0005] One aspect of the present invention provides a phase-locked loop reference clock duty cycle calibration circuit, comprising: a duty cycle detection control module and a duty cycle calibration module; the duty cycle detection control module is used to receive the reference calibration clock output by the duty cycle calibration module and the high-speed calibration clock output by the phase-locked loop, and output a control code to the duty cycle calibration module; the duty cycle calibration module is used to receive the input phase-locked loop reference clock signal and the control code, and adjust the duty cycle of the reference clock signal under the control of the control code, and output the reference calibration clock to the duty cycle detection control module and the phase-locked loop multiplier.

[0006] The phase-locked loop reference clock duty cycle calibration circuit provided by the present invention converts the high and low level width information of the reference calibration clock output by the duty cycle calibration module DCC into the count value output by the counter through an 8-frequency division 8-phase generator and a logic gate circuit, thereby realizing the detection of the high and low level width of the reference calibration clock, and the way in which the counter outputs the count value is convenient for comparison by a digital comparator, and the digital finite state machine then feeds back the comparison result to the duty cycle calibration module DCC to control the duty cycle calibration module DCC to calibrate the duty cycle of the reference clock. Therefore, the present invention has the advantages of wide duty cycle calibration range, high duty cycle calibration accuracy, small occupied area, simple structure, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings: Figure 1 It is a schematic diagram of the circuit structure of a phase-locked loop with a reference clock multiplier provided by an embodiment of the present application; Figure 2 is a circuit structure diagram of a duty cycle detection control module provided by an embodiment of the present application; Figure 3 It is a circuit structure diagram of a duty cycle calibration module provided in one embodiment of the present application. DETAILED DESCRIPTION

[0008] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0009] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0010] It should be understood that although the terms first, second, third, etc. may be used to describe the acquisition modules in the embodiments of the present invention, the acquisition modules should not be limited to these terms. These terms are only used to distinguish the acquisition modules from each other.

[0011] The word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0012] It should be noted that the directional words such as "upper", "lower", "left", and "right" described in the embodiments of the present invention are described at the angles shown in the drawings and should not be understood as limiting the embodiments of the present invention. In addition, in the context, it should also be understood that when it is mentioned that an element is formed "on" or "under" another element, it can not only be formed directly "on" or "under" another element, but also be formed "on" or "under" another element indirectly through an intermediate element.

[0013] See also Figure 1 A phase-locked loop 100 with a frequency doubler provided in one embodiment of the present application includes: a duty cycle calibration module (DCC) 101, a frequency doubler (Doubler) 102, a phase frequency detector (PFD) 103, a loop filter (LPF) 104, a voltage controlled oscillator (VCO) 105, etc. Figure 1 Although not shown Figure 2 The duty cycle detection control module 106 in FIG. Figure 1It is clearly shown that the duty cycle detection control module 106 feeds back two control codes dcc_up_ctrl<7:0> and dcc_dn_ctrl<7:0> to the duty cycle calibration module 101. That is to say, in this embodiment, the duty cycle calibration module 101 and the duty cycle detection control module 106 together constitute a detection calibration feedback control circuit of the reference clock of the phase-locked loop 100. Among them, the duty cycle detection control module 106 is used to receive the reference calibration clock Ref_cal_ck output by the duty cycle calibration module 101 and the high-speed calibration clock DCC_cal_ck output by the phase-locked loop, and output two control codes dcc_up_ctrl<7:0> and dcc_dn_ctrl<7:0> to the duty cycle calibration module 101. The duty cycle calibration module 101 is used to receive the input phase-locked loop reference clock signal Ref_ck_in and two control codes, and adjust the duty cycle of the reference clock signal Ref_ck_in under the control of the control code, and output the reference calibration clock Ref_cal_ck to the duty cycle detection control module 106 and the phase-locked loop frequency multiplier 102.

[0014] See also Figure 2 The duty cycle detection control module 106 includes a count error detector 1061 and a digital finite state machine 1062. The count error detector 1061 includes a frequency divider, a reference calibration clock low level counting circuit, a reference calibration clock high level counting circuit and a digital comparator 10611. The count error detector 1061 is used to determine the size of the duty cycle of the reference calibration clock Ref_cal_ck. The digital finite state machine 1062 is used to adjust the size of the control code dcc_up_ctrl<7:0> and dcc_dn_ctrl<7:0> according to the output signal of the digital comparator 10611.

[0015] Furthermore, the frequency divider includes an 8-frequency-8-phase generator 10612, which is used to divide the high-speed calibration clock DCC_cal_ck output by the phase-locked loop by 8 and convert it into 8 clock signals dcc_cal8_ck<7:0> with a phase interval of 45 degrees.

[0016] Furthermore, the reference calibration clock low-level counting circuit includes an inverter 10613, eight first AND gate logic circuits 10614, eight first counters 10615, and a first adder 10616. The inverter 10613 receives the reference calibration clock Ref_cal_ck output by the duty cycle calibration module 101, and outputs the inverted signal to each first AND gate logic circuit 10614. The first input end of each first AND gate logic circuit 10614 receives the output signal of the inverter 10613, and the second input end of each first AND gate logic circuit 10614 receives one of the eight clock signals dcc_cal8_ck<7:0> with a phase interval of 45 degrees output by the 8-frequency division 8-phase generator 10612. The output end of each first AND gate logic circuit 10614 is connected to the input end of each first counter 10615. Each first counter 10615 is used to count the output signal of each first AND gate logic circuit 10614, and the counting result of each first counter 10615 is output to the first adder 10616. The first adder 10616 is used to sum the counting results of the 8 first counters 10615 and output the summed result to the digital comparator 10611.

[0017] Furthermore, the reference calibration clock high level counting circuit includes 8 second AND gate logic circuits 10617, 8 second counters 10618 and a second adder 10619. The first input end of each second AND gate logic circuit 10617 receives the reference calibration clock Ref_cal_ck output by the duty cycle calibration module 101, and the second input end of each second AND gate logic circuit 10617 receives one of the 8 clock signals dcc_cal8_ck<7:0> output by the 8-frequency division 8-phase generator 10612 with a phase interval of 45 degrees; the output end of each second AND gate logic circuit 10617 is connected to the input end of each second counter 10618. Each second counter 10618 is used to count the output signal of each second AND gate logic circuit 10617, and the counting result of each second counter 10618 is output to the second adder 10619. The second adder 10619 is used to sum the counting results of the eight second counters 10618 and output the summed result to the digital comparator 10611 .

[0018] Furthermore, the digital comparator 10611 is used to compare the size of the summation results of the first adder 10616 and the second adder 10619, so as to output the difference counter_error_num between the two summation results and the comparison indication signal Fast / Slow to the digital finite state machine 1062. The comparison indication signal Fast / Slow is used to indicate the size of the two summation results.

[0019] Further, the digital finite state machine 1062 includes a minimum error query 10621, a binary search module 10622, and an optimal control code selector 10623. The binary search module 10622 is used to output the control codes dcc_up_ctrl<7:0> and dcc_dn_ctrl<7:0> to the optimal control code selector 10623 using a binary search method according to the comparison indication signal Fast / Slow. The minimum error query 10621 is used to record the difference between the two summation results corresponding to each control code, and send the control code selection information corresponding to the minimum difference to the optimal control code selector 10623. The optimal control code selector 10623 is used to output the control code corresponding to the minimum difference between the two summation results according to the control code selection information.

[0020] See also Figure 3 The duty cycle calibration module 101 includes a current mirror circuit 1011, a charging current transistor 1012, a discharging current transistor 1013, an input inverter 1014, an adjustment capacitor 1015 and an output buffer 1016. The current mirror circuit 1011 is used to provide a charge and discharge bias current for the duty cycle current formed by the input reference clock signal Ref_ck_in. The charging current transistor 1012 and the discharging current transistor 1013 are used to control the charging and discharging of the duty cycle current formed by the input reference clock signal Ref_ck_in according to the first control code dcc_up_ctrl<7:0> and the second control code dcc_dn_ctrl<7:0>. The input inverter 1014, the charging current transistor 1012 and the discharging current transistor 1013 form a charging and discharging loop.

[0021] Specifically, the current mirror circuit 1011 includes a first P-type MOS transistor mp1, a first N-type MOS transistor mn1, and a second N-type MOS transistor mn2. The gate and drain of the first P-type MOS transistor mp1 are connected, the drain of the first P-type MOS transistor mp1 is connected to the drain of the second N-type MOS transistor mn2, the source of the first P-type MOS transistor mp1 is connected to a power supply, the first N-type MOS transistor mn1 is connected to the gate of the second N-type MOS transistor mn2, the source of the first N-type MOS transistor mn1 is grounded, the drain and gate of the first N-type MOS transistor mn1 are connected to a current source, and the source of the second N-type MOS transistor mn2 is grounded.

[0022] The charging current transistor 1012 includes a second P-type MOS transistor mp2, the discharging current transistor 1013 includes a third N-type MOS transistor mn3, and the input inverter 1014 includes a fourth P-type MOS transistor mp4 and a fifth N-type MOS transistor mn5. Among them, the source of the second P-type MOS transistor mp2 is connected to the power supply, the gate of the second P-type MOS transistor mp2 receives the first control code dcc_up_ctrl<7:0>, the drain of the second P-type MOS transistor mp2 is connected to the source of the fourth P-type MOS transistor mp4, the gate of the fourth P-type MOS transistor mp4 is connected to the gate of the fifth N-type MOS transistor mn5 and the reference clock signal Ref_ck_in, the drain of the fourth P-type MOS transistor mp4 is connected to the drain of the fifth N-type MOS transistor mn5 and the first end of the adjustment capacitor 1015, the second end of the adjustment capacitor 1015 is grounded, the source of the fifth N-type MOS transistor mn5 is connected to the drain of the third N-type MOS transistor mn3, the gate of the third N-type MOS transistor mn3 receives the second control code dcc_dn_ctrl<7:0>, and the source of the third N-type MOS transistor mn3 is grounded.

[0023] The output buffer 1016 includes a third P-type MOS transistor mp3 and a fourth N-type MOS transistor mn4, the gates of the third P-type MOS transistor mp3 and the fourth N-type MOS transistor mn4 are connected to the first end of the adjustment capacitor 1015, the source of the third P-type MOS transistor mp3 is connected to the power supply, the drain of the third P-type MOS transistor mp3 and the drain of the fourth N-type MOS transistor mn4 are connected and serve as the output end of the reference calibration clock Ref_cal_ck, and the source of the fourth N-type MOS transistor mn4 is grounded.

[0024] See also Figure 2 The following describes the working process of the phase-locked loop reference clock duty cycle calibration circuit in this embodiment. The serial numbers are only used to distinguish the steps, and are not used to limit the order of the steps: (1) Set the first control code dcc_up_ctrl<7:0> and the second control code dcc_dn_ctrl<7:0> to the maximum value to ensure that the initial duty cycle calibration module DCC output clock has steep rising and falling edges; (2) After the phase lock is locked, it outputs the high-speed calibration clock DCC_cal_ck and the reference calibration clock Ref_cal_ck; (3) Turn on the duty cycle detection control module to divide the high-speed calibration clock DCC_cal_ck by 8, and output 8 clocks dcc_cal8_ck<7:0> with a phase interval of 45 degrees; (4) After the reference calibration clock Ref_cal_ck is inverted by the inverter, it is ANDed with 8 high-speed calibration clocks dcc_cal8_ck<7:0> with a phase interval of 45 degrees, and then input to 8 first counters. The results of the first counters are then output to the first adder. In this way, the output value of the first adder represents the low level width of the reference calibration clock Ref_cal_ck; (5) The reference calibration clock Ref_cal_ck performs an AND operation with 8 high-speed calibration clocks dcc_cal8_ck<7:0> with a phase interval of 45 degrees, and then inputs them to 8 second counters. The results of the second counters are output to the second adder, so that the output value of the second adder represents the high level width of the reference calibration clock Ref_cal_ck; (6) The digital comparator compares the outputs of the first adder and the second adder. If the output value of the first adder is greater than the output value of the second adder, which means that the duty cycle is less than 50%, the digital finite state machine decreases dcc_up_ctrl<7:0> until the output value of the first adder is less than the output value of the second adder, and then outputs the final dcc_up_ctrl<7:0> and dcc_dn_ctrl<7:0>. (7) The digital comparator compares the outputs of the first adder and the second adder. If the output value of the first adder is smaller than the output value of the second adder, which means the duty cycle is greater than 50%, the digital finite state machine decreases dcc_dn_ctrl<7:0> until the output value of the first adder is greater than the output value of the second adder, and then outputs the final dcc_up_ctrl<7:0> and dcc_dn_ctrl<7:0>. By outputting the optimal values ​​of dcc_up_ctrl<7:0> and dcc_dn_ctrl<7:0> through steps (6) and (7), the calibration process of the duty cycle of the input reference clock of the phase-locked loop is completed.

[0025] See also Figure 3 The following describes the working process of the duty cycle calibration module in this embodiment. The serial numbers are only used to distinguish the steps, and are not used to limit the order of the steps: (1) When the input reference clock Ref_ck_in is less than 50%, the charging current Ibup is reduced by reducing the control signal dcc_up_ctrl<7:0>. After selecting the optimal dcc_up_ctrl<7:0> control value, the duty cycle of the reference calibration clock Ref_cal_ck output by the output buffer is close to 50%; (2) When the input reference clock Ref_ck_in is greater than 50%, the discharge current Ibdn is reduced by reducing the control signal dcc_dn_ctrl<7:0>. After selecting the optimal dcc_dn_ctrl<7:0> control value, the duty cycle of the reference calibration clock Ref_cal_ck output by the output buffer is close to 50%.

[0026] To summarize, in order to reduce the clock frequency of the counter without affecting the calibration accuracy, this embodiment uses an 8-divide-by-8-phase generator to output 8 clock signals with a phase difference of 45 degrees, which are respectively combined with the positive clock signal and the negative clock signal of the reference calibration clock output by the duty cycle calibration module to generate 8 count value outputs, which are then added through the first adder and the second adder. The count value output by the first adder represents the clock low level width output by the duty cycle calibration module, and the count value output by the second adder represents the clock high level width output by the duty cycle calibration module. The output of the first adder is compared with the output of the second adder. If the output value of the first adder is greater than the output value of the second adder, it means that the duty cycle is less than 50%. The digital finite state machine controls dcc_up_ctrl<7:0> to decrease until the output value of the first adder is less than the output value of the second adder, and then outputs the final dcc_up_ctrl<7:0> and dcc_dn_ctrl<7:0>; if the output value of the first adder is less than the output value of the second adder, it means that the duty cycle is greater than 50%. The digital finite state machine controls dcc_dn_ctrl<7:0> to decrease until the output value of the first adder is greater than the output value of the second adder, and then outputs the final dcc_up_ctrl<7:0> and dcc_dn_ctrl<7:0>. Therefore, the phase-locked loop reference clock duty cycle calibration circuit of this embodiment has the advantages of wide duty cycle adjustment range, high precision, saving large-area low-pass filter in the analog feedback loop, and no need for additional calibration of the PLL.

[0027] The above description is only a preferred embodiment of the present invention. Those skilled in the art should understand that the scope of disclosure involved in the present invention is not limited to the technical solution formed by a specific combination of the above technical features, but also should cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present invention (but not limited to) to form a technical solution.

Claims

1. A phase-locked loop reference clock duty cycle calibration circuit, characterized in that: include: Duty cycle detection control module and duty cycle calibration module; The duty cycle detection control module is used to receive the reference calibration clock output by the duty cycle calibration module and the high-speed calibration clock output by the phase-locked loop, and output a control code to the duty cycle calibration module; The duty cycle calibration module is used to receive the input phase-locked loop reference clock signal and control code, and adjust the duty cycle of the reference clock signal under the control of the control code, and output the reference calibration clock to the duty cycle detection control module and the phase-locked loop multiplier.

2. The phase-locked loop reference clock duty cycle calibration circuit according to claim 1, characterized in that: The duty cycle detection control module includes a counting error detector and a digital finite state machine; The counting error detector comprises a frequency divider, a reference calibration clock low level counting circuit, a reference calibration clock high level counting circuit and a digital comparator, and the counting error detector is used to determine the size of the reference calibration clock duty cycle; The digital finite state machine is used to adjust the size of the control code according to the output signal of the digital comparator.

3. A phase-locked loop reference clock duty cycle calibration circuit according to claim 2, characterized in that: The frequency divider includes an 8-frequency-8-phase generator, which is used to divide the high-speed calibration clock output by the phase-locked loop by 8 and convert it into 8 clock signals with phase intervals of 45 degrees.

4. The phase-locked loop reference clock duty cycle calibration circuit according to claim 3, characterized in that: The reference calibration clock low level counting circuit comprises an inverter, eight first AND gate logic circuits, eight first counters and a first adder; The inverter receives the reference calibration clock output by the duty cycle calibration module, and outputs the inverted signal to each first AND gate logic circuit; The first input end of each first AND gate logic circuit receives the output signal of the inverter, and the second input end of each first AND gate logic circuit receives one of the eight clock signals with a phase interval of 45 degrees output by the eight-frequency division eight-phase generator; the output end of each first AND gate logic circuit is connected to the input end of each first counter; Each first counter is used to count the output signal of each first AND gate logic circuit, and the counting result of each first counter is output to the first adder; The first adder is used for summing the counting results of the eight first counters and outputting the summation result to the digital comparator.

5. The phase-locked loop reference clock duty cycle calibration circuit according to claim 4, characterized in that: The reference calibration clock high level counting circuit includes 8 second AND gate logic circuits, 8 second counters and a second adder; The first input end of each second AND gate logic circuit receives the reference calibration clock output by the duty cycle calibration module, and the second input end of each second AND gate logic circuit receives one of the eight clock signals with a phase interval of 45 degrees output by the eight-frequency division eight-phase generator; the output end of each second AND gate logic circuit is connected to the input end of each second counter; Each second counter is used to count the output signal of each second AND gate logic circuit, and the counting result of each second counter is output to the second adder; The second adder is used for summing the counting results of the eight second counters and outputting the summation result to the digital comparator.

6. A phase-locked loop reference clock duty cycle calibration circuit according to claim 5, characterized in that: The digital comparator is used to compare the sizes of the summation results of the first adder and the second adder, so as to output the difference between the two summation results and a comparison indication signal to the digital finite state machine; The comparison indication signal is used to indicate the magnitude of the two summation results.

7. A phase-locked loop reference clock duty cycle calibration circuit according to claim 6, characterized in that: The digital finite state machine includes a minimum error query, a binary search module and an optimal control code selector; The binary search module is used to output the control code to the optimal control code selector using a binary search method according to the comparison indication signal; The minimum error query device is used to record the difference between the two summation results corresponding to each of the control codes, and send the control code selection information corresponding to the minimum difference to the optimal control code selector; The optimal control code selector is used to output the control code corresponding to when the difference between the two summation results is the smallest according to the control code selection information.

8. The phase-locked loop reference clock duty cycle calibration circuit according to claim 7, characterized in that: The duty cycle calibration module includes a current mirror circuit, a charging current transistor, a discharging current transistor, an input inverter, an adjustment capacitor and an output buffer; The current mirror circuit is used to provide a charge and discharge bias current for a duty cycle current formed by an input reference clock signal; The control code includes a first control code and a second control code, and the charging current transistor and the discharging current transistor are used to control the charging and discharging of the duty cycle current formed by the input reference clock signal according to the first control code and the second control code; The input inverter, the charging current transistor and the discharging current transistor form a charging and discharging loop.

9. The phase-locked loop reference clock duty cycle calibration circuit according to claim 8, characterized in that: The current mirror circuit includes a first P-type MOS transistor, a first N-type MOS transistor, and a second N-type MOS transistor. The gate and drain of the first P-type MOS transistor are connected, the drain of the first P-type MOS transistor is connected to the drain of the second N-type MOS transistor, the source of the first P-type MOS transistor is connected to a power supply, the first N-type MOS transistor is connected to the gate of the second N-type MOS transistor, the source of the first N-type MOS transistor is grounded, the drain and gate of the first N-type MOS transistor are connected to a current source, and the source of the second N-type MOS transistor is grounded.

10. The phase-locked loop reference clock duty cycle calibration circuit according to claim 9, characterized in that: The charging current transistor includes a second P-type MOS transistor, the discharging current transistor includes a third N-type MOS transistor, and the input inverter includes a fourth P-type MOS transistor and a fifth N-type MOS transistor; Wherein, the source of the second P-type MOS tube is connected to the power supply, the gate of the second P-type MOS tube receives the first control code, the drain of the second P-type MOS tube is connected to the source of the fourth P-type MOS tube, the gate of the fourth P-type MOS tube is connected to the gate of the fifth N-type MOS tube and the reference clock signal, the drain of the fourth P-type MOS tube is connected to the drain of the fifth N-type MOS tube and the first end of the regulating capacitor, the second end of the regulating capacitor is grounded, the source of the fifth N-type MOS tube is connected to the drain of the third N-type MOS tube, the gate of the third N-type MOS tube receives the second control code, and the source of the third N-type MOS tube is grounded; The output buffer includes a third P-type MOS tube and a fourth N-type MOS tube, the gates of the third P-type MOS tube and the fourth N-type MOS tube are connected to the first end of the regulating capacitor, the source of the third P-type MOS tube is connected to the power supply, the drain of the third P-type MOS tube is connected to the drain of the fourth N-type MOS tube and serves as the output end of the reference calibration clock, and the source of the fourth N-type MOS tube is grounded.

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