A phase-locked loop reference clock duty cycle calibration circuit

Abstract

The present invention discloses a phase-locked loop reference clock duty cycle calibration circuit, relating to the technical field of signal frequency and phase control. The circuit comprises: a duty cycle detection and control module and a duty cycle calibration module; the duty cycle detection and control module is configured to receive a reference calibration clock output by the duty cycle calibration module and a high-speed calibration clock output by the phase-locked loop, and output a control code to the duty cycle calibration module; the duty cycle calibration module is configured to receive an input phase-locked loop reference clock signal and a control code, and under the control of the control code, adjust the duty cycle of the reference clock signal, and output the reference calibration clock to the duty cycle detection and control module and a frequency multiplier of the phase-locked loop. The present invention achieves calibration of the input reference clock, has a wide duty cycle adjustment range, high adjustment accuracy, a small footprint, and a simple structure.

Description

Technical Field

[0001] The present invention relates to the technical field of signal frequency and phase control, and in particular to a phase-locked loop reference clock duty cycle calibration circuit. Background Art

[0002] Low-spurious phase-locked loops (PLLs) are crucial in many applications, providing signals with high frequency purity. Therefore, their design and implementation have become a significant research topic. PLL spurious signals can be caused by a variety of factors, including duty cycle fluctuations in the reference clock multiplier, additional spurious signals introduced by unstable or unclean power supplies, spurious signals caused by multiple harmonic crosstalk of the clock signal, and current mismatch in the PLL charge pump. To reduce quantization noise, low-noise PLL designs typically use a frequency multiplier to multiply the reference clock frequency. This shifts the quantization noise to a higher frequency, where it can be filtered out by the loop's low-pass filter. Frequency multipliers are typically implemented using delay elements and XOR gates. When the input reference clock has a duty cycle other than 50%, the output duty cycle of the frequency multiplier fluctuates with the clock output, resulting in increased spurious signals at the PLL output.

[0003] In a phase-locked loop using a reference clock multiplier, when the duty cycle of the input reference clock differs significantly from 50%, the duty cycle of the multiplied reference clock will fluctuate periodically, resulting in spurious output from the phase-locked loop. Theoretical analysis shows that the closer the duty cycle of the input reference clock is to 50%, the smaller the output spurious output of the phase-locked loop. Therefore, calibrating the duty cycle of the input reference clock becomes the primary solution for reducing spurious output from a phase-locked loop with a multiplier. Existing technologies typically use analog closed-loop feedback to control the output node of the clock input inverter to charge and discharge current, which has a limited adjustment range. Furthermore, due to the use of an analog negative feedback loop and a low-pass filter, it has the disadvantage of a large area. Other existing technologies use an additional calibration PLL method to adjust the duty cycle of the input reference clock. The disadvantage is that an additional calibration PLL design is added, resulting in a more complex structure. Summary of the Invention

[0004] In response to the aforementioned shortcomings and deficiencies in the prior art, the present invention provides a phase-locked loop reference clock duty cycle calibration circuit. This circuit utilizes only a counter, logic gate circuits, and a finite state machine to implement feedback control of a duty cycle calibration module (DCC), thereby calibrating the input reference clock. This circuit offers the advantages of a wide duty cycle adjustment range, high accuracy, and eliminates the need for a large low-pass filter in the analog feedback loop, eliminating the need for additional PLL calibration.

[0005] One aspect of the present invention provides a phase-locked loop reference clock duty cycle calibration circuit, comprising: a duty cycle detection control module and a duty cycle calibration module; the duty cycle detection control module is used to receive the reference calibration clock output by the duty cycle calibration module and the high-speed calibration clock output by the phase-locked loop, and output a control code to the duty cycle calibration module; the duty cycle calibration module is used to receive the input phase-locked loop reference clock signal and the control code, and adjust the duty cycle of the reference clock signal under the control of the control code, and output the reference calibration clock to the duty cycle detection control module and the phase-locked loop frequency multiplier.

[0006] The phase-locked loop reference clock duty cycle calibration circuit provided by the present invention converts the high and low level width information of the reference calibration clock output by the duty cycle calibration module (DCC) into count values output by a counter via a divide-by-8 frequency generator and logic gate circuits, thus enabling detection of the high and low level widths of the reference calibration clock. The counter outputs count values in a manner that facilitates comparison by a digital comparator. A digital finite state machine then feeds the comparison result back to the duty cycle calibration module (DCC) to control the duty cycle calibration module (DCC) to calibrate the reference clock's duty cycle. Therefore, the present invention has the advantages of a wide duty cycle calibration range, high duty cycle calibration accuracy, a small footprint, and a simple structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0008] Figure 1 This is a schematic diagram of the circuit structure of a phase-locked loop with a reference clock multiplier provided by one embodiment of the present application;

[0009] Figure 2 This is a circuit diagram of a duty cycle detection control module provided in one embodiment of the present application;

[0010] Figure 3 This is a circuit structure diagram of a duty cycle calibration module provided in one embodiment of the present application. DETAILED DESCRIPTION

[0011] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0012] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms "a", "an", "the" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0013] It should be understood that although the terms first, second, third, etc. may be used to describe the acquisition modules in the embodiments of the present invention, the acquisition modules should not be limited to these terms. These terms are only used to distinguish the acquisition modules from each other.

[0014] The word "if," as used herein, may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to the determination" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)," depending on the context.

[0015] It should be noted that the directional terms such as "upper," "lower," "left," and "right" described in the embodiments of the present invention are described from the perspectives shown in the accompanying drawings and should not be construed as limiting the embodiments of the present invention. Furthermore, in the context, it should be understood that when an element is referred to as being formed "on" or "under" another element, it can be formed not only directly "on" or "under" the other element, but also indirectly "on" or "under" the other element through an intermediate element.

[0016] See also Figure 1 A phase-locked loop 100 with a frequency multiplier provided in one embodiment of the present application includes: a duty cycle calibration module (DCC) 101, a frequency multiplier (Doubler) 102, a phase frequency detector (PFD) 103, a loop filter (LPF) 104, a voltage-controlled oscillator (VCO) 105, etc. Figure 1 Although not shown Figure 2 The duty cycle detection control module 106 in Figure 1The figure clearly shows the two control codes dcc_up_ctrl<7:0> and dcc_dn_ctrl<7:0> that are fed back from the duty cycle detection and control module 106 to the duty cycle calibration module 101. In other words, in this embodiment, the duty cycle calibration module 101 and the duty cycle detection and control module 106 together constitute a detection and calibration feedback control circuit for the reference clock of the phase-locked loop 100. The duty cycle detection and control module 106 is configured to receive the reference calibration clock Ref_cal_ck output by the duty cycle calibration module 101 and the high-speed calibration clock DCC_cal_ck output by the phase-locked loop, and output the two control codes dcc_up_ctrl<7:0> and dcc_dn_ctrl<7:0> to the duty cycle calibration module 101. The duty cycle calibration module 101 is used to receive the input phase-locked loop reference clock signal Ref_ck_in and two control codes, and adjust the duty cycle of the reference clock signal Ref_ck_in under the control of the control codes, and output the reference calibration clock Ref_cal_ck to the duty cycle detection control module 106 and the phase-locked loop frequency multiplier 102.

[0017] See also Figure 2 Duty cycle detection control module 106 includes a count error detector 1061 and a digital finite state machine 1062. Count error detector 1061 includes a frequency divider, a reference calibration clock low-level counting circuit, a reference calibration clock high-level counting circuit, and a digital comparator 10611. Count error detector 1061 is used to determine the duty cycle of reference calibration clock Ref_cal_ck. Digital finite state machine 1062 is used to adjust the values of control codes dcc_up_ctrl<7:0> and dcc_dn_ctrl<7:0> based on the output signal of digital comparator 10611.

[0018] Furthermore, the frequency divider includes a divide-by-8 8-phase generator 10612, which is used to divide the high-speed calibration clock DCC_cal_ck output by the phase-locked loop by 8 and convert it into 8 clock signals dcc_cal8_ck<7:0> with a phase interval of 45 degrees.

[0019] Furthermore, the reference calibration clock low-level counting circuit includes an inverter 10613, eight first AND gate logic circuits 10614, eight first counters 10615, and a first adder 10616. Inverter 10613 receives the reference calibration clock Ref_cal_ck output by duty cycle calibration module 101 and outputs the inverted signal to each first AND gate logic circuit 10614. A first input of each first AND gate logic circuit 10614 receives the output signal of inverter 10613, and a second input of each first AND gate logic circuit 10614 receives one of the eight clock signals dcc_cal8_ck<7:0>, each with a phase interval of 45 degrees, output by divide-by-8, 8-phase generator 10612. The output of each first AND gate logic circuit 10614 is connected to the input of each first counter 10615. Each first counter 10615 is used to count the output signal of each first AND gate logic circuit 10614, and the counting result of each first counter 10615 is output to the first adder 10616. The first adder 10616 is used to sum the counting results of the 8 first counters 10615 and output the summed result to the digital comparator 10611.

[0020] Furthermore, the reference calibration clock high-level counting circuit includes eight second AND gate logic circuits 10617, eight second counters 10618, and a second adder 10619. Each second AND gate logic circuit 10617 receives a reference calibration clock Ref_cal_ck output by the duty cycle calibration module 101 at its first input, and receives one of eight 45-degree phase-spaced clock signals dcc_cal8_ck<7:0> output by the divide-by-8, 8-phase generator 10612 at its second input. The output of each second AND gate logic circuit 10617 is connected to the input of each second counter 10618. Each second counter 10618 counts the output signal of each second AND gate logic circuit 10617, and the count result of each second counter 10618 is output to the second adder 10619. The second adder 10619 is used to sum the counting results of the eight second counters 10618 and output the summation result to the digital comparator 10611.

[0021] Furthermore, the digital comparator 10611 is used to compare the summation results of the first adder 10616 and the second adder 10619, and output the difference between the two summation results, counter_error_num, and a comparison indication signal Fast / Slow to the digital finite state machine 1062. The comparison indication signal Fast / Slow is used to indicate the size of the two summation results.

[0022] Furthermore, the digital finite state machine 1062 includes a minimum error query unit 10621, a binary search module 10622, and an optimal control code selector 10623. The binary search module 10622 is configured to output the control codes dcc_up_ctrl<7:0> and dcc_dn_ctrl<7:0> to the optimal control code selector 10623 using a binary search method based on the comparison indication signal Fast / Slow. The minimum error query unit 10621 is configured to record the difference between the two summation results corresponding to each control code and send control code selection information corresponding to the minimum difference to the optimal control code selector 10623. The optimal control code selector 10623 is configured to output the control code corresponding to the minimum difference between the two summation results based on the control code selection information.

[0023] See also Figure 3 The duty cycle calibration module 101 includes a current mirror circuit 1011, a charging current transistor 1012, a discharging current transistor 1013, an input inverter 1014, an adjustment capacitor 1015, and an output buffer 1016. The current mirror circuit 1011 is used to provide charge and discharge bias current for the duty cycle current formed by the input reference clock signal Ref_ck_in. The charging current transistor 1012 and the discharging current transistor 1013 are used to control the charging and discharging of the duty cycle current formed by the input reference clock signal Ref_ck_in according to the first control code dcc_up_ctrl<7:0> and the second control code dcc_dn_ctrl<7:0>. The input inverter 1014, the charging current transistor 1012, and the discharging current transistor 1013 form a charge and discharge loop.

[0024] Specifically, the current mirror circuit 1011 includes a first P-type MOS transistor mp1, a first N-type MOS transistor mn1, and a second N-type MOS transistor mn2. The gate and drain of the first P-type MOS transistor mp1 are connected, the drain of the first P-type MOS transistor mp1 is connected to the drain of the second N-type MOS transistor mn2, the source of the first P-type MOS transistor mp1 is connected to a power supply, the first N-type MOS transistor mn1 is connected to the gate of the second N-type MOS transistor mn2, the source of the first N-type MOS transistor mn1 is grounded, the drain and gate of the first N-type MOS transistor mn1 are connected to a current source, and the source of the second N-type MOS transistor mn2 is grounded.

[0025] The charging current transistor 1012 includes a second P-type MOS transistor mp2 , the discharging current transistor 1013 includes a third N-type MOS transistor mn3 , and the input inverter 1014 includes a fourth P-type MOS transistor mp4 and a fifth N-type MOS transistor mn5 . The source of the second P-type MOS transistor mp2 is connected to a power supply, the gate of the second P-type MOS transistor mp2 receives the first control code dcc_up_ctrl<7:0>, the drain of the second P-type MOS transistor mp2 is connected to the source of the fourth P-type MOS transistor mp4, the gate of the fourth P-type MOS transistor mp4 is connected to the gate of the fifth N-type MOS transistor mn5 and the reference clock signal Ref_ck_in, the drain of the fourth P-type MOS transistor mp4 is connected to the drain of the fifth N-type MOS transistor mn5 and the first end of the adjustment capacitor 1015, the second end of the adjustment capacitor 1015 is grounded, the source of the fifth N-type MOS transistor mn5 is connected to the drain of the third N-type MOS transistor mn3, the gate of the third N-type MOS transistor mn3 receives the second control code dcc_dn_ctrl<7:0>, and the source of the third N-type MOS transistor mn3 is grounded.

[0026] Output buffer 1016 includes a third P-type MOS transistor mp3 and a fourth N-type MOS transistor mn4. The gates of the third P-type MOS transistor mp3 and the fourth N-type MOS transistor mn4 are connected to the first end of the adjustment capacitor 1015. The source of the third P-type MOS transistor mp3 is connected to a power supply. The drain of the third P-type MOS transistor mp3 and the drain of the fourth N-type MOS transistor mn4 are connected and serve as the output end of the reference calibration clock Ref_cal_ck. The source of the fourth N-type MOS transistor mn4 is grounded.

[0027] See also Figure 2 The following describes the workflow of the phase-locked loop reference clock duty cycle calibration circuit in this embodiment. The serial numbers are only used to distinguish the steps and are not used to limit the order of the steps:

[0028] (1) Set the first control code dcc_up_ctrl<7:0> and the second control code dcc_dn_ctrl<7:0> to the maximum value to ensure that the initial duty cycle calibration module DCC output clock has steep rising and falling edges;

[0029] (2) After the phase lock is locked, it outputs the high-speed calibration clock DCC_cal_ck and the reference calibration clock Ref_cal_ck;

[0030] (3) Turn on the duty cycle detection control module to divide the high-speed calibration clock DCC_cal_ck by 8, and output 8 clocks dcc_cal8_ck<7:0> with a phase interval of 45 degrees;

[0031] (4) After the reference calibration clock Ref_cal_ck is inverted by the inverter, it is ANDed with the 8 high-speed calibration clocks dcc_cal8_ck<7:0> with a phase interval of 45 degrees, and then input to the 8 first counters. The results of the first counters are then output to the first adder. In this way, the output value of the first adder represents the low-level width of the reference calibration clock Ref_cal_ck;

[0032] (5) The reference calibration clock Ref_cal_ck is ANDed with the eight high-speed calibration clocks dcc_cal8_ck<7:0> with a phase interval of 45 degrees, and then input to the eight second counters. The results of the second counters are output to the second adder, so that the output value of the second adder represents the high level width of the reference calibration clock Ref_cal_ck;

[0033] (6) The digital comparator compares the outputs of the first adder and the second adder. If the output value of the first adder is greater than the output value of the second adder, which means the duty cycle is less than 50%, the digital finite state machine reduces dcc_up_ctrl<7:0> until the output value of the first adder is less than the output value of the second adder, and then outputs the final dcc_up_ctrl<7:0> and dcc_dn_ctrl<7:0>;

[0034] (7) The digital comparator compares the outputs of the first adder and the second adder. If the output value of the first adder is less than the output value of the second adder, which means the duty cycle is greater than 50%, the digital finite state machine decreases dcc_dn_ctrl<7:0> until the output value of the first adder is greater than the output value of the second adder, and then outputs the final dcc_up_ctrl<7:0> and dcc_dn_ctrl<7:0>;

[0035] By outputting the optimal values of dcc_up_ctrl<7:0> and dcc_dn_ctrl<7:0> through steps (6) and (7), the calibration process of the phase-locked loop input reference clock duty cycle is completed.

[0036] See also Figure 3 The following describes the workflow of the duty cycle calibration module in this embodiment. The serial numbers are only used to distinguish the steps and are not used to limit the order of the steps:

[0037] (1) When the input reference clock Ref_ck_in is less than 50%, the charging current Ibup is reduced by reducing the control signal dcc_up_ctrl<7:0>. After selecting the optimal dcc_up_ctrl<7:0> control value, the duty cycle of the reference calibration clock Ref_cal_ck output by the output buffer is close to 50%;

[0038] (2) When the input reference clock Ref_ck_in is greater than 50%, the discharge current Ibdn is reduced by reducing the control signal dcc_dn_ctrl<7:0>. After selecting the optimal dcc_dn_ctrl<7:0> control value, the duty cycle of the reference calibration clock Ref_cal_ck output by the output buffer is close to 50%.

[0039] To summarize, in order to reduce the clock frequency of the counter without affecting the calibration accuracy, this embodiment uses an 8-divide-by-8-phase generator to output 8 clock signals with a phase difference of 45 degrees, which are respectively combined with the positive clock signal and the negative clock signal of the reference calibration clock output by the duty cycle calibration module to generate 8 count value outputs, which are then added through the first adder and the second adder. The count value output by the first adder represents the low-level width of the clock output by the duty cycle calibration module, and the count value output by the second adder represents the high-level width of the clock output by the duty cycle calibration module. The output of the first adder is compared with the output of the second adder. If the output value of the first adder is greater than the output value of the second adder, indicating that the duty cycle is less than 50%, the digital finite state machine controls dcc_up_ctrl<7:0> to decrease until the output value of the first adder is less than the output value of the second adder, and then outputs the final dcc_up_ctrl<7:0> and dcc_dn_ctrl<7:0>. If the output value of the first adder is less than the output value of the second adder, indicating that the duty cycle is greater than 50%, the digital finite state machine controls dcc_dn_ctrl<7:0> to decrease until the output value of the first adder is greater than the output value of the second adder, and then outputs the final dcc_up_ctrl<7:0> and dcc_dn_ctrl<7:0>. Therefore, the phase-locked loop reference clock duty cycle calibration circuit of this embodiment has the advantages of wide duty cycle adjustment range, high precision, saving large-area low-pass filter in the analog feedback loop, and no need for additional PLL calibration.

[0040] The above description is merely a preferred embodiment of the present invention. Those skilled in the art should understand that the scope of the present invention is not limited to technical solutions formed by specific combinations of the above-mentioned technical features. It also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents, without departing from the above-mentioned disclosure. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this invention.

Claims

1. A phase-locked loop reference clock duty cycle calibration circuit, characterized in that: include: Duty cycle detection control module and duty cycle calibration module; The duty cycle detection control module is configured to receive the reference calibration clock output by the duty cycle calibration module and the high-speed calibration clock output by the phase-locked loop, and output a control code to the duty cycle calibration module; The duty cycle calibration module is configured to receive an input phase-locked loop reference clock signal and a control code, adjust the duty cycle of the reference clock signal under the control of the control code, and output the reference calibration clock to the duty cycle detection control module and the phase-locked loop frequency multiplier; The duty cycle detection control module includes a counting error detector and a digital finite state machine; the counting error detector includes a frequency divider, a reference calibration clock low-level counting circuit, a reference calibration clock high-level counting circuit and a digital comparator, the counting error detector is used to determine the size of the reference calibration clock duty cycle; the digital finite state machine is used to adjust the size of the control code according to the output signal of the digital comparator; The frequency divider includes an 8-frequency 8-phase generator, which is used to divide the high-speed calibration clock output by the phase-locked loop by 8 and convert it into 8 clock signals with a phase interval of 45 degrees; The reference calibration clock low-level counting circuit includes an inverter, 8 first AND gate logic circuits, 8 first counters and a first adder; the inverter receives the reference calibration clock output by the duty cycle calibration module, and outputs the inverted signal to each first AND gate logic circuit; the first input end of each first AND gate logic circuit receives the output signal of the inverter, and the second input end of each first AND gate logic circuit receives one of the 8 clock signals with a phase interval of 45 degrees output by the 8-divide-8-phase generator; the output end of each first AND gate logic circuit is connected to the input end of each first counter; each first counter is used to count the output signal of each first AND gate logic circuit, and the counting result of each first counter is output to the first adder; the first adder is used to sum the counting results of the 8 first counters and output the summed result to the digital comparator; The reference calibration clock high-level counting circuit includes 8 second AND gate logic circuits, 8 second counters and a second adder; the first input end of each second AND gate logic circuit receives the reference calibration clock output by the duty cycle calibration module, and the second input end of each second AND gate logic circuit receives one of the 8 clock signals with a phase interval of 45 degrees output by the 8-divide-by-8-phase generator; the output end of each second AND gate logic circuit is connected to the input end of each second counter; each second counter is used to count the output signal of each second AND gate logic circuit, and the counting result of each second counter is output to the second adder; the second adder is used to sum the counting results of the 8 second counters and output the summed result to the digital comparator.

2. The phase-locked loop reference clock duty cycle calibration circuit according to claim 1, wherein: The digital comparator is used to compare the sizes of the summation results of the first adder and the second adder, so as to output a difference between the two summation results and a comparison indication signal to the digital finite state machine; The comparison indication signal is used to indicate the magnitude of the two summation results.

3. The phase-locked loop reference clock duty cycle calibration circuit according to claim 2, wherein: The digital finite state machine includes a minimum error query unit, a binary search module and an optimal control code selector; The binary search module is used to output the control code to the optimal control code selector using a binary search method according to the comparison indication signal; The minimum error query device is used to record the difference between the two summation results corresponding to each control code, and send the control code selection information corresponding to the minimum difference to the optimal control code selector; The optimal control code selector is used to output the control code corresponding to when the difference between the two summation results is the smallest according to the control code selection information.

4. The phase-locked loop reference clock duty cycle calibration circuit according to claim 3, wherein: The duty cycle calibration module includes a current mirror circuit, a charging current transistor, a discharging current transistor, an input inverter, an adjustment capacitor and an output buffer; The current mirror circuit is used to provide a charge and discharge bias current for the duty cycle current formed by the input reference clock signal; The control code includes a first control code and a second control code, and the charging current transistor and the discharging current transistor are used to control the charging and discharging of the duty cycle current formed by the input reference clock signal according to the first control code and the second control code; The input inverter, the charging current transistor and the discharging current transistor form a charging and discharging loop.

5. The phase-locked loop reference clock duty cycle calibration circuit according to claim 4, wherein: The current mirror circuit includes a first P-type MOS transistor, a first N-type MOS transistor, and a second N-type MOS transistor. The gate and drain of the first P-type MOS transistor are connected, the drain of the first P-type MOS transistor is connected to the drain of the second N-type MOS transistor, the source of the first P-type MOS transistor is connected to a power supply, the first N-type MOS transistor is connected to the gate of the second N-type MOS transistor, the source of the first N-type MOS transistor is grounded, the drain and gate of the first N-type MOS transistor are connected to a current source, and the source of the second N-type MOS transistor is grounded.

6. The phase-locked loop reference clock duty cycle calibration circuit according to claim 5, wherein: The charging current transistor includes a second P-type MOS transistor, the discharging current transistor includes a third N-type MOS transistor, and the input inverter includes a fourth P-type MOS transistor and a fifth N-type MOS transistor; The source of the second P-type MOS transistor is connected to a power supply, the gate of the second P-type MOS transistor receives the first control code, the drain of the second P-type MOS transistor is connected to the source of the fourth P-type MOS transistor, the gate of the fourth P-type MOS transistor is connected to the gate of the fifth N-type MOS transistor and a reference clock signal, the drain of the fourth P-type MOS transistor is connected to the drain of the fifth N-type MOS transistor and the first end of the adjustment capacitor, the second end of the adjustment capacitor is grounded, the source of the fifth N-type MOS transistor is connected to the drain of the third N-type MOS transistor, the gate of the third N-type MOS transistor receives the second control code, and the source of the third N-type MOS transistor is grounded. The output buffer includes a third P-type MOS transistor and a fourth N-type MOS transistor. The gates of the third P-type MOS transistor and the fourth N-type MOS transistor are connected to the first end of the adjustment capacitor. The source of the third P-type MOS transistor is connected to a power supply. The drain of the third P-type MOS transistor and the drain of the fourth N-type MOS transistor are connected and serve as the output end of the reference calibration clock. The source of the fourth N-type MOS transistor is grounded.

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