A Multichannel Sampling Synchronization Method and Device for a Radio Frequency Direct Sampling RFSOC System

Abstract

The present invention discloses a method and device for multi-channel sampling synchronization of a radio frequency direct sampling RFSOC system. The method includes: setting relevant parameter configurations for the RF IP core on the PL side of the system; generating a bottom-layer driver framework according to the hardware configuration of the system and the peripheral connection lines; generating register parameters according to the set relevant clocks at the user layer, and the PS side transfers the register parameters to the PL side through DMA; the PL side transfers the register parameters to the clock distribution module through the SPI interface; configuring the clock distribution module through the system SPI interface to output corresponding sampling clocks, synchronization clocks, and data-with-channel clocks, so that the ADC input signal can be collected and converted into analog-to-digital conversion data with a specified number of digits, and controlling the output analog signal of the DAC through the set frequency control word parameters on the PL side; the PS side controls the RF IP core on the PL side through interface functions to achieve multi-channel sampling synchronization of the RFSOC system. The present invention realizes low-latency and high-precision multi-channel sampling synchronization of the system.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and particularly to a multi-channel sampling synchronization method and device for a radio frequency direct sampling RFSOC system. Background Art

[0002] With the gradual maturity of 5G technology, its greatest features are big data, massive connections, and scenario experiences. In the deployment of 5G, large-scale MIMO (multiple input multiple output) and DBF (digital beamforming) technologies account for a large part of the solution. At the same time, in the fields of radar detection and wireless electromagnetic spectrum monitoring, multi-channel direction finding between antenna array units is also a basic technology. To support these technologies, it is required that the radio frequency units of devices close to the antenna end must be more compact, and at the same time have high sampling rate ADC / DAC (analog-to-digital / digital-to-analog) conversion functions or even reach the radio frequency direct sampling ability, as well as programmable signal processing capabilities. The latest RFSOC system integrates radio frequency direct sampling transceiver and signal processing functions to solve the above problems. It integrates multiple channel sampling data converters, a CPU processor, and FPGA programmable signal processing capabilities. The power consumption and size of the system are significantly reduced to 50% - 25% of the traditional system design. The software and hardware functions of the system are flexible and configurable, and it has broad application prospects.

[0003] In an RFSOC (Radio Frequency System-on-Chip) system, to implement MIMO, DBF, and multi-channel direction finding technologies between antenna array units, multi-channel sampling synchronization is the basis and an important link for technical implementation. By constructing a multi-channel sampling synchronization method for the RFSOC system, the signals received and transmitted in multiple channels can meet high-precision synchronization requirements in terms of parameters such as time, frequency, phase, and amplitude, achieving the key indicators of signal MIMO transceiver and DBF, so as to complete the multi-carrier multi-channel transceiver of the system and the digital beam synthesis function of the array signal.

[0004] Although the RFSOC system has high integration and a compact design, it integrates ADC / DAC (analog-to-digital / digital-to-analog) converters for multi-channel sampling, with a maximum of 16 T / R (transmit / receive) channels. However, the system itself does not have a complete multi-channel sampling synchronization function and ability. It is necessary to conduct a new design for the RFSOC system and construct a multi-channel sampling synchronization method to complete the multi-channel sampling synchronization ability, meet the application requirements of subsequent 5G technology development and various wireless communications, radar arrays, wireless electromagnetic spectrum monitoring, and digital signal beam synthesis, and overcome the functional deficiencies of the system.

[0005] Patent application number CN202410595018.4 discloses an audio sampling synchronization method and device thereof, which mainly presets a cache area on the device side, and presets high and low cache capacity alarm lines of the cache area, caches the data information sent by the host side in the cache area, and monitors the cache capacity of the cache area in real time; when the cache capacity of the cache area reaches the high / low cache capacity alarm line, the device side feeds back the current actual playback rate to the host side, and the host side adjusts the rate of sending data information according to the actual playback rate until the data information of the host side is sent. However, the invention does not discuss the method of multi-channel sampling synchronization of the RFSOC system, and its entire method is a method for audio signal processing and cannot be applied to high-speed sampling signal processing of the RFSOC system.

[0006] Patent application number CN202311284326.7 is a multi-channel modulation and forwarding system based on RFSOC, which discloses a multi-channel ADC module for acquiring received RF signals, performing digital-to-analog conversion on received RF signals, and obtaining received baseband signals. The PS end receives identification binding information and forwarding binding information, and the PL end performs digital beamforming, signal identification modulation, and multi-channel transmit beamforming on the received baseband signal according to the identification binding information and forwarding binding information to obtain the baseband signal to be transmitted, and the multi-channel DAC module performs analog-to-digital conversion on the baseband signal to be transmitted to obtain the RF signal to be transmitted. This patent introduces a multi-channel modulation and forwarding method for the RFSOC system, but the invention does not discuss a method for constructing a multi-channel sampling synchronization, and the entire system is an introduction to a method for multi-channel modulation and forwarding that cannot be applied to the application environment of the RFSOC system that requires multi-channel sampling synchronization signal processing. Summary of the invention

[0007] In view of this, through the internal components of the RFSOC system and the peripheral clock distribution circuit, the present invention provides a multi-channel sampling synchronization method and device of the RF direct sampling RFSOC system, which cleverly controls the PL (Programmable Logic) end, PS (Processing System) end and clock distribution module in the RFSOC system, thereby realizing a low-latency, high-precision system multi-channel sampling synchronization method.

[0008] The present invention discloses a multi-channel sampling synchronization method of a radio frequency direct sampling RFSOC system, which comprises:

[0009] Step 1: Set up relevant parameter configurations for the RF IP core at the PL end of the system; the relevant parameter configurations include ADC / DAC sampling clock related parameters, input and output characteristic parameters, and data mode;

[0010] Step 2: Connect the peripheral lines according to the system's hardware configuration to generate a low-level driver framework; the PS side uses the low-level driver framework as the basis of the software platform, generates register parameters according to the set relevant clocks in the user layer, and the PS side transfers the register parameters to the PL side through DMA;

[0011] Step 3: The PL side transfers the register parameters to the clock distribution module through the SPI interface; configure the clock distribution module through the system SPI interface to make it output the corresponding sampling clock, synchronization clock, and data along-channel clock, so that the ADC input signal can be collected and converted into analog-to-digital conversion data with a specified number of digits. On the PL side, control the output analog signal of the DAC through the set frequency control word parameters; the PS side controls the RF IP core on the PL side through the interface function to achieve multi-channel sampling synchronization of the RFSOC system.

[0012] Further, the said Step 1 includes:

[0013] After the system starts up, the PL side initializes the relevant parameters of the configured RF IP core, and the IP core configures the key information related to signal acquisition; the signal sampling modes of the ADC and DAC are both direct RF sampling using the clock source of the peripheral circuit, and multi-channel signals are enabled. The ADC input and DAC output signals are both in AC coupling mode.

[0014] Further, the said Step 2 includes:

[0015] After the PS side completes the system initialization, determine the parameters of the output signal of the clock distribution module according to the clock settings of the PL side, and generate relevant register parameters according to the value of this parameter, referring to the data configuration manual of the clock distribution module; the parameters of the output signal include type, frequency, channel, and level;

[0016] Configure the transfer data bit width and frequency in the DMA transfer modules on the PS side and the PL side according to the type of the register parameters, enable the DMA transfer modules, and the PS side transfers the register configuration parameters to the PL side.

[0017] Further, the said Step 3 includes:

[0018] After the PL side receives the data, set the transfer clock and data type according to the SPI configuration mode required by the clock distribution module, and transfer the register configuration parameters to the clock distribution module for configuration. After the configuration is completed, the clock distribution module writes the clock lock status into the register, and the RFSOC chip reads the value of this register and judges the output clock until it is stable;

[0019] Synchronize the initialization and operation of multiple channels on the PS side, set the initialization delay, and then initialize the data converter and the configuration information of multi-channel synchronization in sequence. After calling the function of multi-channel synchronization and setting the number of channels and channel numbers to be synchronized, the function writes the synchronization information into the corresponding registers of the RF IP core through the data interface for data interaction between the PS side and the PL side to achieve the synchronization function.

[0020] Furthermore, it also includes:

[0021] Judge whether the synchronization is successful by detecting the value returned by calling the synchronization API function. If the ADC synchronization is successful, observe the multi-channel data collected by the ADC on the debugging interface of the VIVADO software and observe the collected spectrum and analyze the multi-channel phase error through the MATLAB software; if the DAC synchronization is successful, set the frequency control word parameters required for the DAC output in the data control interface of the VIVADO software, enable the output, and use an oscilloscope to observe the DAC output signal and analyze the phase error of the signal.

[0022] The present invention also discloses a multi-channel sampling synchronization device for a radio frequency direct sampling RFSOC system, which is composed of an RFSOC chip, a clock distribution module, and the peripheral circuit of the RFSOC chip; the RFSOC chip is respectively connected to the clock distribution module and the peripheral circuit of the RFSOC chip; the RFSOC chip includes a PL side and a PS side; the clock distribution module is connected to the PS side through the PL side.

[0023] Furthermore, the PL side includes an SPI interface module and an RF configuration module; the clock distribution module is used to transmit the sampling clock, the synchronization clock, and the data along-with-clock to the RF configuration module; the PS side is used to transmit the SPI configuration to the clock distribution module; the RF configuration module is used to receive external radio frequency signals and output radio frequency signals.

[0024] Furthermore, the PS side includes an SPI interface module and a function interface module; the SPI interface module is used to transmit the configuration clock parameters to the SPI interface module in the PL side; the function interface module is used to transmit the synchronization control to the RF configuration module.

[0025] Furthermore, the peripheral circuit includes a power supply module, a storage module, and a memory; the power supply module includes multiple independent power supply chips, and the multiple independent power supply chips are respectively connected to the RFSOC chip to provide different types of power supplies for the RFSOC chip.

[0026] Further, the clock distribution module includes a crystal oscillator, a phase-locked loop chip, and a clock buffer chip; the crystal oscillator is connected to the phase-locked loop, the crystal oscillator provides a reference source for the phase-locked loop, the phase-locked loop is connected to the clock buffer chip, the phase-locked loop inputs a multi-channel frequency-multiplied clock to the clock buffer chip, and the clock buffer chip is connected to the RFSOC chip; the clock buffer chip provides multiple required clock sources for the RFSOC chip.

[0027] Due to the adoption of the above technical solution, the present invention has the following advantages:

[0028] 1. In a typical MIMO multiple-input multiple-output and DBF digital beamforming system, in order to minimize the error of multi-channel sampling synchronization and not reduce the overall system performance index, it is generally required that the phase error ≤ 3° after each power-on between multi-channel samplings. A multi-channel sampling synchronization method for a radio frequency direct sampling RFSOC system constructed by this invention patent has a multi-channel sampling phase error better than 3° through actual testing.

[0029] 2. In the case of using a 3GSPS high-speed sampling clock, the ADC multi-channel synchronization phase difference results in the RFSOC system are shown in Table 1 below. It can be seen from the table that after testing, the change in the phase difference between each ADC channel ≤ ±1°, which is equivalent to a multi-channel synchronization time-domain error of 0.92 picoseconds. The DAC multi-channel synchronization phase difference results in the RFSOC system are shown in Table 2. It can be seen from Table 2 that after testing, the change in the phase difference between each DAC channel ≤ ±1°, which is equivalent to a multi-channel synchronization time-domain error of 0.92 picoseconds. Description of the Drawings

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings.

[0031] Figure 1 Schematic diagram of the multi-channel sampling synchronization RFSOC system for the embodiments of the present invention;

[0032] Figure 2 Schematic diagram of the hardware implementation of the multi-channel sampling synchronization RFSOC system for the embodiments of the present invention;

[0033] Figure 3 Flowchart of the multi-channel sampling synchronization method for the RFSOC system of the embodiments of the present invention. Detailed Embodiments

[0034] The present invention will be further described in conjunction with the accompanying drawings and embodiments. The described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art shall fall within the scope of protection of the embodiments of the present invention.

[0035] See Figure 1 , the present invention provides an embodiment of a multi-channel sampling synchronization method for a radio frequency direct sampling RFSOC system, which includes:

[0036] First, after setting the relevant parameters of the ADC / DAC (analog-to-digital / digital-to-analog) sampling clock, input / output characteristic parameters, data mode, etc. through the dedicated RF IP core at the PL end of the system, and according to the hardware configuration of the system and the peripheral connection lines, a low-level driver framework is generated; then, the PS end uses this as the basis of the software platform, generates control register parameters according to the set relevant clocks at the user layer, and transfers them to the PL end through the internal data interface; then, the clock distribution module is configured through the system SPI interface to output the corresponding sampling clock, synchronization clock, and data-with-carrier clock, so that the ADC input signal can be collected and converted into 12-bit analog-to-digital conversion data, and the output analog signal of the DAC is controlled by the set frequency control word parameters at the PL end; finally, the PS end controls the RF IP core at the PL end through the compiled dedicated myRfdcInit() interface function to implement the multi-channel sampling synchronization method of the RFSOC system.

[0037] The specific implementation steps of the multi-channel sampling synchronization method for the signals of the RFSOC system are as follows:

[0038] 1) After the system starts, the PL end initializes and configures the relevant parameters of the RF IP core. The IP core mainly configures the key information related to signal acquisition. Among them, there are 8 radio frequency input channels and 8 radio frequency output channels. The ADC and DAC signal sampling modes both use the clock source of the peripheral circuit for radio frequency direct sampling, the sampling rate is 3GSPS (sampling clock), the Nyquist domain is set in Zone1, and multi-channel signals are enabled. The synchronization signal is set to 5MHz. The ADC input and DAC output signals are both in AC coupling mode. In the same dedicated AXIS clock cycle, the ADC input data is 8 channels, the data bit width is 12 bits, the data-with-carrier clock is set to 375MHz (sampling clock divided by 8), the DAC output data is 8 channels, the data bit width is 16 bits, and the data-with-carrier clock is set to 187.5MHz (sampling clock divided by 16).

[0039] 2) After the PS end completes the system initialization, it determines the type, frequency, channel, level and other parameters of the output signal of the clock distribution module according to the clock settings at the PL end, and generates the relevant register parameters according to these values with reference to the data configuration manual of the clock distribution module.

[0040] 3) Configure the data transfer bit width and frequency in the DMA (Direct Memory Access) transfer modules on the PS side and the PL side according to the register parameter type. After the configuration in step 2) is completed, enable the transfer module, and the PS side will transfer the register configuration parameters to the PL side.

[0041] 4) After the PL side receives the data, set the transfer clock, data type according to the SPI configuration mode required by the clock distribution module, and transfer the register configuration parameters to the clock distribution module for configuration. After the configuration is completed, the clock distribution module writes the clock lock status into a dedicated register, and the RFSOC chip reads the value of this system register and judges the output clock until it is stable.

[0042] 5) The PS side initializes and runs the multiplexed synchronization. First, set the initialization delay, then initialize the RFdc data converter and the configuration information of the multi-channel synchronization in sequence. Finally, call the function of the multi-channel synchronization and set the number of channels and channel numbers to be synchronized. After that, this function writes the synchronization information into the corresponding registers of the RF IP core through the axi4-lite data interface for data interaction between the PS side and the PL side to achieve the synchronization function.

[0043] 6) Finally, judge whether the synchronization is successful by detecting the value returned by calling the synchronization API function. If the ADC synchronization is successful, the multi-channel data collected by the ADC can be observed on the debugging interface of the VIVADO software, and the collected spectrum and the multi-channel phase error analysis can be observed through the MATLAB software; if the DAC synchronization is successful, set the frequency control word parameter required for the DAC output in the VIO data control interface of the VIVADO software, enable the output, and use an oscilloscope to observe the DAC output signal and analyze the phase error of the signal.

[0044] In summary, the multi-channel sampling synchronization method flow of the RFSOC system is as Figure 3 shown.

[0045] The present invention also provides an embodiment of a multi-channel sampling synchronization device for a radio frequency direct sampling RFSOC system, which is composed of an RFSOC chip, a clock distribution module, and the peripheral circuit of the RFSOC chip; the RFSOC chip is respectively connected to the clock distribution module and the peripheral circuit of the RFSOC chip; the RFSOC chip includes a PL side and a PS side; the clock distribution module is connected to the PS side through the PL side.

[0046] In an embodiment of the present application, the PL side includes an SPI interface module and an RF configuration module; the clock distribution module is used to transfer the sampling clock, synchronization clock, and data along-path clock to the RF configuration module; the PS side is used to transfer the SPI configuration to the clock distribution module; the RF configuration module is used to receive external radio frequency signals and output radio frequency signals.

[0047] In one embodiment of the present application, the PS side includes an SPI interface module and a function interface module; the SPI interface module is used to transmit configuration clock parameters to the SPI interface module in the PL side; the function interface module is used to transmit synchronous control to the RF configuration module.

[0048] In one embodiment of the present application, the peripheral circuit includes a power supply module, a storage module, and a memory; the power supply module includes a plurality of independent power supply chips, and the plurality of independent power supply chips are respectively connected to the RFSOC chip to provide different types of power supply for the RFSOC chip.

[0049] In one embodiment of the present application, the clock distribution module includes a crystal oscillator, a phase-locked loop chip, and a clock buffer chip; the crystal oscillator is connected to the phase-locked loop, the crystal oscillator provides a reference source for the phase-locked loop, the phase-locked loop is connected to the clock buffer chip, the phase-locked loop inputs a multiplexed frequency-multiplied clock to the clock buffer chip, and the clock buffer chip is connected to the RFSOC chip; the clock buffer chip provides a multiplexed required clock source for the RFSOC chip.

[0050] The clock distribution circuit consists of a crystal oscillator of model TC53NAGHC-10MHz, a phase-locked loop of model LMK04828, and a clock buffer of model HMC987, and provides the sampling clock used for collecting radio frequency signals, the control clock (abbreviation: control clock) required for realizing multi-channel synchronization, and the accompanying clock for monitoring and controlling data for the RFSOC synchronization system;

[0051] See Figure 2 and Figure 3 , 8-way radio frequency input / output is connected to the RFSOC chip through a radio frequency connector, the 8-way radio frequency input provides the radio frequency input signal to be collected for the RFSOC chip, and the 8-way radio frequency output outputs the analog radio frequency signal generated by the RFSOC chip to the outside;

[0052] See Figure 2 and Figure 3 , the power supply circuit selects the LTM4650 chip of the DCDC power supply type to provide 0.85V chip voltage for the RFSOC synchronization system, and the LTM4644 to provide 0.9V / 1.2V / 1.8V voltage for the digital circuit of the RFSOC synchronization system; selects the LT3083 chip of the LDO power supply type to provide 0.92V / 1.8V analog circuit voltage for the RFSOC synchronization system;

[0053] See Figure 2 and Figure 3, the RFSOC chip uses the XCZU28DR chip produced by Xilinx as the main chip for implementing the synchronization system. This chip includes a programmable logic part (PL part) and a processing system part (PS part). The PL part contains 4,272 digital signal processors, 1,080 38-Mb BRAMs, 425,280 logic cells, 8 CMTs, 2 PCIE3.0X16s, 16 GTYs and other programmable resources; the PS part contains four Cortex-A53 ARM cores and two Cortex-R5 ARM cores.

[0054] See Figure 2 and Figure 3 , the RFSOC chip externally connects 2 pieces of SPI FLASH with a capacity of 2 Gbits (model number MT25QU02GCBB8E12) to store the programming files; the RFSOC chip externally connects 4 pieces of 1-GB DDR3 (model number MT40A512M16) to store, read and write data and payload files. The data bit width is 64 bits and the rate is 2,400 MB / s.

[0055] In the case of using a 3 GSPS high-speed sampling clock, the ADC multi-channel synchronization phase difference results in the RFSOC system are shown in Table 1 below. It can be seen from Table 1 that after testing, the change in the phase difference between each ADC channel ≤ ±1°, which is equivalent to a multi-channel synchronous time domain error of 0.92 picoseconds.

[0056] Table 1 ADC multi-channel synchronization phase difference results

[0057]

[0058] The DAC multi-channel synchronization phase difference results in the RFSOC system are shown in Table 2. It can be seen from Table 2 that after testing, the change in the phase difference between each DAC channel ≤ ±1°, which is equivalent to a multi-channel synchronous time domain error of 0.92 picoseconds.

[0059] Table 2 DAC multi-channel synchronization phase difference results

[0060]

[0061]

[0062] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications or equivalent replacements can still be made to the specific embodiments of the present invention, and any modifications or equivalent replacements that do not depart from the spirit and scope of the present invention should be covered by the protection scope of the claims of the present invention.

Claims

1. A method for multi-channel sampling synchronization of a radio frequency direct sampling RFSOC system, characterized in that, Including: Step 1: Configure relevant parameters of the PL-side RF IP core of the system; The relevant parameter configuration includes ADC / DAC sampling clock-related parameters, input / output characteristic parameters, and data modes; Step 2: Connect the peripheral circuits according to the hardware configuration of the system to generate a bottom-layer driver framework; The PS side uses the bottom-layer driver framework as the basis of the software platform, generates register parameters according to the set relevant clocks in the user layer, and the PS side transfers the register parameters to the PL side through DMA; Step 3: The PL side transfers the register parameters to the clock distribution module through the SPI interface; Configure the clock distribution module through the system SPI interface to make it output the corresponding sampling clock, synchronization clock, and data along-channel clock, so that the ADC input signal can be collected and converted into analog-to-digital conversion data with a specified number of bits. On the PL side, control the output analog signal of the DAC through the set frequency control word parameter; The PS side controls the RF IP core of the PL side through the interface function to achieve multi-channel sampling synchronization of the RFSOC system; The said Step 1 includes: After the system starts up, the PL side initializes the relevant parameters of the configured RF IP core, and the IP core configures the key information related to signal acquisition; The ADC and DAC signal sampling modes both use the clock source of the peripheral circuit for direct RF sampling, enable multi-channel signals, and the ADC input and DAC output signals are both in AC coupling mode; The said Step 2 includes: After the PS side completes the system initialization, determine the parameters of the output signal of the clock distribution module according to the clock setting of the PL side, and generate relevant register parameters according to the value of this parameter with reference to the data configuration manual of the clock distribution module; The parameters of the output signal include type, frequency, channel, and level; Configure the transmission data bit width and frequency in the DMA transmission modules of the PS side and the PL side according to the type of register parameters, enable the DMA transmission module, and the PS side transfers the register configuration parameters to the PL side; The said Step 3 includes: After the PL side receives the data, set the transmission clock and data type according to the SPI configuration mode required by the clock distribution module and transfer the register configuration parameters to the clock distribution module for configuration. After the configuration is completed, the clock distribution module writes the clock lock status into the register, and the RFSOC chip reads the value of this register and judges the output clock until it is stable; The PS side initializes and runs multi-channel synchronization, sets the initialization delay, then initializes the configuration information of the data converter and multi-channel synchronization in sequence, calls the multi-channel synchronization function and sets the number and channel numbers of the channels to be synchronized. After that, this function writes the synchronization information into the corresponding register of the RF IP core through the data interface for data interaction between the PS side and the PL side to achieve the synchronization function.

2. The multi-channel sampling synchronization method of the RF direct sampling RFSOC system according to claim 1, characterized in that, Also including: Determine whether the synchronization is successful by detecting the value returned by the call to the synchronous API function. If the ADC synchronization is successful, observe the multi-channel data collected by the ADC on the debugging interface of the VIVADO software and observe the collected spectrum and perform multi-channel phase error analysis through the MATLAB software; if the DAC synchronization is successful, set the frequency control word parameter required for the DAC output in the data control interface of the VIVADO software, enable the output, and use an oscilloscope to observe the DAC output signal and analyze the phase error of the signal.

3. A multi-channel sampling synchronization device for a radio frequency direct sampling RFSOC system, which implements the multi-channel sampling synchronization method of the radio frequency direct sampling RFSOC system described in claim 1 or 2, characterized in that, It consists of an RFSOC chip, a clock distribution module, and the peripheral circuit of the RFSOC chip; the RFSOC chip is respectively connected to the clock distribution module and the peripheral circuit of the RFSOC chip; the RFSOC chip includes a PL side and a PS side; the clock distribution module is connected to the PS side through the PL side.

4. The multi-channel sampling synchronization device of the radio frequency direct sampling RFSOC system according to claim 3, characterized in that, The PL side includes an SPI interface module and an RF configuration module; the clock distribution module is used to transmit the sampling clock, the synchronization clock, and the data-with-carrier clock to the RF configuration module; The PS side is used to transmit the SPI configuration to the clock distribution module; the RF configuration module is used to receive external radio frequency signals and output radio frequency signals.

5. The multi-channel sampling synchronization device of the radio frequency direct sampling RFSOC system according to claim 4, wherein, The PS side includes an SPI interface module and a function interface module; the SPI interface module is used to transmit the configuration clock parameter to the SPI interface module in the PL side; the function interface module is used to transmit the synchronization control to the RF configuration module.

6. The multi-channel sampling synchronization device of the radio frequency direct sampling RFSOC system according to claim 3, characterized in that, The peripheral circuit includes a power supply module, a storage module, and a memory; the power supply module includes multiple independent power supply chips, and the multiple independent power supply chips are respectively connected to the RFSOC chip to provide different types of power supply for the RFSOC chip.

7. The multi-channel sampling synchronization device of the radio frequency direct sampling RFSOC system according to claim 3, wherein, The clock distribution module includes a crystal oscillator, a phase-locked loop chip, and a clock buffer chip; the crystal oscillator is connected to the phase-locked loop, the crystal oscillator provides a reference source for the phase-locked loop, the phase-locked loop is connected to the clock buffer chip, the phase-locked loop inputs multiple frequency-multiplied clocks to the clock buffer chip, and the clock buffer chip is connected to the RFSOC chip; the clock buffer chip provides multiple required clock sources for the RFSOC chip.

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