Time domain residual error amplifier for assembly line analog-to-digital converter

Abstract

The invention discloses a time domain residual error amplifier for a pipelined analog-to-digital converter. The time domain residual error amplifier comprises a threshold detection circuit, a voltage amplification circuit and a phase discriminator, wherein the voltage amplification circuit is respectively connected with the threshold detection circuit and the phase discriminator; the threshold detection circuit is connected with the phase discriminator; the voltage amplification circuit comprises a first-stage sampling capacitor, a second-stage sampling capacitor and a constant current pull-down charge pump. The constant current pull-down charge pump discharges the first-stage sampling capacitor at a constant speed through the current mirror image current, and converts the residual voltage reserved by the first-stage sampling capacitor into a time signal; and the phase discriminator controls the second-stage sampling capacitor to charge and discharge according to the trigger condition of the threshold detection circuit, and converts the time signal into a voltage signal. According to the time domain residual error amplifier for the pipelined analog-to-digital converter, provided by the invention, voltage gain in a product form of a capacitance proportion and a current mirror current proportion can be realized, and linearity and PVT robustness can be optimized while the characteristic of low power consumption is kept.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a time domain residual amplifier for a pipeline analog-to-digital converter. Background Art

[0002] The pipelined ADC structure is in great demand in high-speed and high-resolution applications, and the pipelined ADC has high requirements for the residual amplifier. The performance of the residual amplifier directly determines the performance of the pipelined ADC. Therefore, the pipelined ADC requires a high-speed, high-linearity and certain gain stability residual amplifier. Traditional residual amplifiers mostly use closed-loop operational amplifiers (MDACs) or dynamic amplifiers (DAs), but these amplifiers have bandwidth, gain and energy efficiency limitations, which restricts their application in modern high-precision ADCs.

[0003] In response to the requirements of high speed and low power consumption, the present invention provides a time domain residual amplifier, which processes the residual voltage by means of a time signal, thereby achieving higher linearity and PVT robustness while maintaining an open-loop structure. Summary of the invention

[0004] In view of the defects in the prior art, the present invention provides a time domain residual amplifier for a pipeline analog-to-digital converter. The technical solution adopted by the present invention is:

[0005] The time domain residual amplifier for a pipeline analog-to-digital converter comprises:

[0006] Threshold detection circuit, voltage amplifier circuit and phase detector; wherein,

[0007] The voltage amplifying circuit is connected to the threshold detection circuit and the phase detector respectively; the threshold detection circuit is connected to the phase detector;

[0008] The voltage amplification circuit includes first-stage sampling capacitors DAC_P and DAC_N, second-stage sampling capacitors DAC2_P and DAC2_N, and a constant current pull-down charge pump.

[0009] The voltage amplification circuit comprises:

[0010] A constant current source; a first current mirror structure composed of 12 NMOS transistors MM1_1~MM1_12; a second current mirror structure composed of 6 PMOS transistors MM2_1~MM2_6; 2 NMOS transistors MD1_1, MD1_2; first-stage sampling capacitors DAC_P and DAC_N; 8 NMOS transistors MD2_1~MD2_8; second-stage sampling capacitors DAC2_P, DAC2_N; 2 NMOS transistors ME1, ME2.

[0011] In the voltage amplifier circuit, the upper plates of the first-stage sampling capacitors DAC_P and DAC_N are respectively connected to the source of MD1_1 and MD1_2 and input the residual voltage Vres, and the lower plates are grounded; the gates of MD1_1 and MD1_2 are connected to the EN enable signal;

[0012] In the voltage amplifier circuit, the upper plates of the second-stage sampling capacitors DAC2_P and DAC2_N are respectively connected to the source of MD2_1 and MD2_5 and output the result Vout, and the lower plates are grounded; the gates of MD2_1 to MD2_8 input UP, UPN, DW, DWN signals

[0013] The threshold detection circuit adopts a continuous time comparator;

[0014] The continuous time comparator adopts a four-stage cascade self-biased open-loop operational amplifier, combined with a five-tube operational amplifier to perform a differential-to-single-ended operation to obtain a single-ended output.

[0015] The phase detector comprises two D flip-flops and a logic AND gate.

[0016] The self-biased open-loop operational amplifier is composed of 7 transistors M1-M7, M1-M3 are NMOS transistors, M4-M6 are PMOS transistors; the gates Vin and Vip of M2 and M3 are respectively connected to the reference threshold voltage Vthres and the upper plate voltage of the first-stage sampling capacitor; the drain voltages Von and Vop of M2 and M3 are output Vout.

[0017] The five-tube operational amplifier is a classic five-tube OTA, Von and Vop are connected to the differential input terminals of the five-tube operational amplifier, and the output single-ended is output VOUT after passing through two inverters.

[0018] The D flip-flops are all rising edge triggered and have a reset terminal Reset.

[0019] The D terminal of the D flip-flop in the phase detector is always connected to a high level; the output signal of the threshold detection circuit is connected to the first two-input AND gate; the output of the first two-input AND gate is connected to the CLK input terminal of the D flip-flop; the Q output terminal of the D flip-flop generates UP and DW rectangular pulse signals; UP and DW are input to the second two-input AND gate; the output of the second two-input AND gate is connected to the Reset terminal of the D flip-flop; UP and DW are respectively connected to an inverter; the inverter outputs UPN and DWN.

[0020] Compared with the prior art, the advantages of the present invention are:

[0021] The invention provides a time domain residual amplifier for a pipeline analog-to-digital converter, wherein the gain is determined by a capacitance ratio and a current ratio, and thus the gain fluctuation is small under different PVT conditions, the amplifier has high linearity and high robustness, and is suitable for high-speed and high-precision application requirements.

[0022] The present invention provides a time domain residual amplifier for a pipeline analog-to-digital converter, which reduces the cost of operational amplifier design and has lower power consumption than a traditional closed-loop amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 1 is a schematic diagram of the structure of a time domain residual amplifier for a pipeline analog-to-digital converter provided by an embodiment of the present invention;

[0025] Figure 2 It is a schematic diagram of working waveforms of a time domain residual amplifier for a pipeline analog-to-digital converter provided by an embodiment of the present invention;

[0026] Figure 3 is a structural diagram of a voltage amplifier circuit provided by an embodiment of the present invention;

[0027] Figure 4 Schematic diagram of a threshold detection circuit and a phase detector provided by an embodiment of the present invention;

[0028] Figure 5 is a structure diagram of a threshold detection circuit provided by an embodiment of the present invention; DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0030] The embodiments of the present invention are further described in detail below with reference to the accompanying drawings.

[0031] Example 1

[0032] like Figure 1As shown, the present invention provides a time domain residual amplifier for a pipeline analog-to-digital converter, comprising:

[0033] Threshold detection circuit, voltage amplifier circuit and phase detector; wherein,

[0034] The voltage amplification circuit includes a first-stage sampling capacitor, a second-stage sampling capacitor, and a constant current pull-down charge pump.

[0035] The first-stage sampling capacitors DAC_P and DAC_N sample the residual voltage Vres; the current Iref of the constant current pull-down charge pump is amplified N times by the current mirror to charge and discharge the first-stage sampling capacitor; the threshold detection circuit compares the threshold voltage Vthres with the voltage on the first-stage sampling capacitor, and inputs the comparison result into the phase detector; the outputs UP and DW of the phase detector are the inputs of the second-stage sampling capacitor to control its charging and discharging; the current Iref of the constant current pull-down charge pump is amplified M times by the current mirror to charge and discharge the second-stage sampling capacitors DAC2_P and DAC2_N; the differential voltage Vout on the second-stage sampling capacitor after the charging and discharging is completed is the final output after amplification.

[0036] In this embodiment, in order to further illustrate the working principle of the residual amplifier of the present invention, the present invention provides the following Figure 2 As shown in the working waveform diagram. Assume that the single-ended capacitance of the first-stage sampling capacitor is CS1 and there is a positive voltage, that is, VDAC_P>VDAC_N, the constant current pull-down charge pump current is ICP1, and the pull-up and pull-down currents of the differential charge pump are both ICP2. When EN is high, the constant current pull-down charge pump starts to discharge DAC_P and DAC_N at the same time with the current ICP1, and the voltage values ​​of the two ports are shown in equations (1) and (2) respectively:

[0037]

[0038] In the formula, VDAC_P(t) and VDAC_N(t) are the upper plate voltages of DAC_P and DAC_N at time t, respectively. Since VDAC_P>VDAC_N at the initial moment, assuming that VDAC_N(t1)=VREF at time t1, the threshold detection circuit is triggered, the phase detector output signal UP is raised to a high level, and UPN is pulled low. The differential charge pump switch makes corresponding switching, that is, charging DAC2_P and discharging DAC2_N. Since the second-stage sampling capacitor is CS2 and has the same initial voltage, the voltage values ​​of the two ports of the second-stage sampling capacitor in the time period after t1 can be expressed as formula (3) and formula (4) respectively:

[0039]

[0040] The first - stage sampling capacitor continues to discharge with ICP1 until VDAC_P(t2) = VREF at time t2. Another threshold - detection circuit is triggered, the output signal DW of the phase - detector is raised to a high level, and DWN is pulled low. At this time, both the UP and DW signals are at a high level, the output of the AND logic gate becomes high, and the output of the phase - detector is reset to a low level. The differential charge - pump switches are all turned off, the second - stage sampling capacitor enters the holding state, and the residual - voltage amplification process ends. At this time, the voltage values at both ports of the second - stage sampling capacitor are respectively as shown in Equation (5) and Equation (6):

[0041]

[0042] In addition, the voltage difference between the two ports of the first - stage sampling capacitor can be expressed as Equation (7):

[0043]

[0044] After the amplification process ends, the voltage difference between the two ports of the second - stage sampling capacitor is Equation (8):

[0045]

[0046] The gain GAIN of the inter - stage amplifier circuit can be expressed as Equation (9):

[0047]

[0048] For the initial case of VDAC_P < VDAC_N, the gain is also as shown in Equation (9). Only by maintaining the linearity of the charge - pump current ratio and the capacitance ratio can a high gain linearity be maintained under PVT variations.

[0049] Refer to Figure 3 , Figure 3 is a structural diagram of a voltage - amplification circuit provided by an embodiment of the present invention. The voltage - amplification circuit includes:

[0050] A constant - current source; a first - group current - mirror structure composed of 12 NMOS transistors MM1_1 to MM1_12; a second - group current - mirror structure composed of 6 PMOS transistors MM2_1 to MM2_6; 2 NMOS transistors MD1_1, MD1_2; a first - stage sampling capacitor DAC_P and DAC_N; 8 NMOS transistors MD2_1 to MD2_8; a second - stage sampling capacitor DAC2_P, DAC2_N; 2 NMOS transistors ME1, ME2;

[0051] The upper plates of the first-stage sampling capacitors DAC_P and DAC_N sample the residual voltage Vres, and the lower plates are grounded; DAC_P and DAC_N are discharged through MD1_1 and MD1_2 with N times IREF current; the gates of MD1_1 and MD1_2 are connected to the EN enable signal;

[0052] In the voltage amplifier circuit, the upper plate voltages of DAC2_P and DAC2_N of the second-stage sampling capacitors are connected to the sources of MD2_1 and MD2_5, respectively, and the lower plates are grounded; DAC2_P and DAC2_N are charged and discharged with M times IREF current through differential pairs MD2_1 to MD2_4 and differential pairs MD2_5 to MD2_8, respectively; the gate input UP, UPN, DW, and DWN signals of MD2_1 to MD2_8 control the disconnection of the differential pairs and thus control the charging and discharging of the second-stage sampling capacitors; and finally, the upper plate voltage of the second-stage sampling capacitor is the amplified output voltage Vout.

[0053] In this embodiment, when the EN enable signal is high, the circuit works, and the first-stage sampling capacitors DAC_P and DAC_N are discharged; when UP is high, DAC2_P is charged and DAC2_N is discharged; when DW is high, DAC2_N is charged and DAC2_P is discharged; when the UP and DW signals are high at the same time, reset; the amplification factor GAIN = (2×M×CDAC) / (N×CDAC2).

[0054] See also Figure 4 , Figure 4 It is a schematic diagram of a threshold detection circuit and a phase detector provided by an embodiment of the present invention. The threshold detection circuit adopts a continuous time comparator, and the upper plate voltage of the first-stage sampling capacitors DAC_P and DAC_N is used as its input signal. Its output signal will be connected to the phase detector after passing through a two-input AND gate with an EN enable signal at the other end; the phase detector includes two rising edge triggered D flip-flops with a reset terminal and a logic AND gate.

[0055] The D terminal of the D flip-flop in the phase detector is always connected to a high level. The output signal of the threshold detection circuit is connected to the input CLK terminal of the D flip-flop after passing through a two-input AND gate with the other end connected to the EN enable signal, and generates high-level UP and DW rectangular pulse signals at the output Q terminal. UP and DW are provided to the reset signal Reset of the D flip-flop through the AND gate. UP and DW are respectively inverted by the inverter to obtain UPN and DWN; the UP, DW, UPN, and DWN signals will be input to the gates of MD2_1~MD2_8 to control their opening and closing, thereby controlling the charging and discharging of DAC2_P and DAC2_N.

[0056] In addition, when the EN enable signal is high, the output result of the two-input AND gate is VOUT, and the threshold detection circuit is in working state; when the EN enable signal is low, the output result is 0, and the threshold detection circuit is in standby state;

[0057] For the D flip-flop, if the VOUT at the input CLK terminal is high, the output at the Q terminal is 1; if the VOUT at the input CLK terminal is low, the output at the Q terminal is 0; when the Q-terminal outputs of the two D flip-flops are both 0, they are maintained; when the Q-terminal outputs of the two D flip-flops are both 1, the signal at the Reset terminal of the input D flip-flop is 1, and they are reset.

[0058] In this embodiment, if VDAC_P>VDAC_N, UP is high level, DW is low level, DAC2_P is charged, and DAC2_N is discharged; if VDAC_P<VDAC_N, UP is low level, DW is high level, DAC2_N is charged, and DAC2_P is discharged.

[0059] like Figure 5 As shown, the continuous time comparator adopts a four-stage cascade self-biased open-loop operational amplifier, combined with a five-tube operational amplifier to perform differential-to-single-ended operation to obtain a single-ended output.

[0060] The self-biased open-loop operational amplifier is composed of 7 transistors M1-M7, M1-M3 are NMOS transistors, and M4-M6 are PMOS transistors. The gates Vin and Vip of M2 and M3 are respectively connected to the reference threshold voltage Vthres and the upper plate voltage VDAC of the sampling capacitor DAC and compared, and the drain voltages Von and Vop of M2 and M3 are differentially output for the comparison results;

[0061] The five-tube operational amplifier is a classic five-tube OTA, Von and Vop are differential inputs of the five-tube operational amplifier, and its single-ended output is output VOUT after passing through two inverters.

[0062] In this embodiment, if the upper plate voltage VDAC of the sampling capacitor DAC is greater than the reference threshold voltage Vthres, the output VOUT is a low level; if the upper plate voltage VDAC of the sampling capacitor DAC is less than the reference threshold voltage Vthres, the output VOUT is a high level.

[0063] In this embodiment, after the above operations of charging and discharging the first-stage sampling capacitor and the second-stage sampling capacitor, the function of amplifying the residual voltage is achieved.

[0064] The present invention provides a time domain residual amplifier for a pipeline analog-to-digital converter, which realizes a voltage gain in the form of a product of a capacitance ratio and a current mirror current ratio, and optimizes linearity and PVT robustness while retaining low power consumption characteristics.

[0065] It should be noted that, in this application, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0066] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features applied for herein.

Claims

1. A time domain residual amplifier for a pipeline analog-to-digital converter, characterized in that: include: Threshold detection circuit, voltage amplifier circuit and phase detector; wherein, The voltage amplifying circuit is connected to the threshold detection circuit and the phase detector respectively; The threshold detection circuit is connected to the phase detector.

2. The time domain residual amplifier for pipeline analog-to-digital converter according to claim 1, characterized in that: The voltage amplification circuit includes first-stage sampling capacitors DAC_P and DAC_N, second-stage sampling capacitors DAC2_P and DAC2_N, and a constant current pull-down charge pump.

3. The time domain residual amplifier for pipeline analog-to-digital converter according to claim 1, characterized in that: The voltage amplification circuit comprises: A constant current source; a first current mirror structure composed of 12 NMOS transistors MM1_1~MM1_12; a second current mirror structure composed of 6 PMOS transistors MM2_1~MM2_6; 2 NMOS transistors MD1_1, MD1_2; first-stage sampling capacitors DAC_P and DAC_N; 8 NMOS transistors MD2_1~MD2_8; second-stage sampling capacitors DAC2_P, DAC2_N; 2 NMOS transistors ME1, ME2.

4. The time domain residual amplifier for pipeline analog-to-digital converter according to claim 1, characterized in that: In the voltage amplifier circuit, the upper plates of the first-stage sampling capacitors DAC_P and DAC_N are respectively connected to the sources of MD1_1 and MD1_2 and input the residual voltage Vres, and the lower plates are grounded; the gates of MD1_1 and MD1_2 are connected to the EN enable signal; In the voltage amplifier circuit, the upper plates of the second-stage sampling capacitors DAC2_P and DAC2_N are respectively connected to the sources of MD2_1 and MD2_5 and output the result Vout, and the lower plates are grounded; the gates of MD2_1 to MD2_8 input UP, UPN, DW, and DWN signals.

5. The time domain residual amplifier for pipeline analog-to-digital converter according to claim 1, characterized in that: The threshold detection circuit adopts a continuous time comparator; The continuous time comparator adopts a four-stage cascade self-biased open-loop operational amplifier, combined with a five-tube operational amplifier to perform a differential-to-single-ended operation to obtain a single-ended output.

6. The time domain residual amplifier for pipeline analog-to-digital converter according to claim 1, characterized in that: The phase detector includes two D flip-flops and a logic AND gate.

7. The time domain residual amplifier for pipeline analog-to-digital converter according to claim 5, characterized in that: The self-biased open-loop operational amplifier is composed of 7 transistors M1-M7, M1-M3 are NMOS transistors, M4-M6 are PMOS transistors; the gates Vin and Vip of M2 and M3 are respectively connected to the reference threshold voltage Vthres and the upper plate voltage of the first-stage sampling capacitor; the drain voltages Von and Vop of M2 and M3 are output Vout.

8. The time domain residual amplifier for pipeline analog-to-digital converter according to claim 5, characterized in that: The five-tube operational amplifier is a classic five-tube OTA, Von and Vop are connected to the differential input terminals of the five-tube operational amplifier, and the output single-ended is output VOUT after passing through two inverters.

9. The time domain residual amplifier for pipeline analog-to-digital converter according to claim 6, characterized in that: The D flip-flops are all rising edge triggered and have a reset terminal Reset.

10. The time domain residual amplifier for pipeline analog-to-digital converter according to claim 6, characterized in that: The D terminal of the D flip-flop in the phase detector is always connected to a high level; the output signal of the threshold detection circuit is connected to the first two-input AND gate; the output of the first two-input AND gate is connected to the CLK input terminal of the D flip-flop; the Q output terminal of the D flip-flop generates UP and DW rectangular pulse signals; UP and DW are input to the second two-input AND gate; the output of the second two-input AND gate is connected to the Reset terminal of the D flip-flop; UP and DW are respectively connected to an inverter; the inverter outputs UPN and DWN.

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