Device for improving switch linearity and bandwidth of sample hold circuit

Abstract

The invention discloses a device for improving switch linearity and bandwidth of a sample hold circuit, which comprises the sample hold circuit and an output buffer, the output buffer comprises a first voltage signal output structure and a second voltage signal output structure, and the first voltage signal output structure comprises a first switch control unit, a second switch control unit and a second switch control unit, the sampling holding circuit is used for disconnecting the first bias load unit from the first signal output unit when the working mode of the sampling holding circuit is a tracking mode, and conducting the first bias load unit from the first signal output unit when the sampling holding circuit is in a holding mode; the first bias load unit is used for accessing externally supplied bias voltage and providing a load; and the first signal output unit is used for disconnecting the output of the first voltage signal in the tracking mode and outputting the first voltage signal in the holding mode. According to the invention, the output buffer is controlled to work only in the hold mode, so that harmonic distortion is reduced, linearity is improved, and the overall bandwidth of the sampling hold circuit is expanded.

Description

Technical Field

[0001] The invention relates to the field of integrated circuit design, and in particular to a device for improving the linearity and bandwidth of a sampling and holding circuit switch. Background Art

[0002] In advanced semiconductor process nodes, such as 28 nm CMOS and FinFET processes, a sample and hold (T / H) circuit generally uses a single NMOS transistor as a sampling switch.

[0003] In order to optimize the output performance of the T / H circuit, traditional designs usually introduce a source follower as an output buffer. The output buffer is working in both tracking mode and holding mode, and its gate-source voltage is relatively constant, so it has a relatively constant transconductance value and exhibits good linear performance. However, when the input frequency reaches tens of gigahertz (GHz), the output of the buffer cannot follow the input signal due to the bandwidth limitation of the sub-channel buffer, thus generating a partially distorted signal proportional to the input frequency. This nonlinear distortion not only reduces the integrity of the signal, but may also have a negative impact on the performance of the entire system, such as increasing the bit error rate and reducing the signal processing capability. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a device for improving the linearity and bandwidth of the switch of the sampling and holding circuit, which can solve the nonlinear problem caused by the switching of the sampling and holding circuit.

[0005] In order to solve the above technical problems, a technical solution adopted by the present invention is: to provide a device for improving the switching linearity and bandwidth of a sampling and holding circuit, comprising a sampling and holding circuit and an output buffer electrically connected to a sampling signal output terminal of the sampling and holding circuit, wherein the output buffer is a differential structure, comprising a first voltage signal output structure and a second voltage signal output structure, wherein the first voltage signal output structure comprises:

[0006] a first switch control unit, used to disconnect the first bias load unit from the first signal output unit when the operation mode of the sample and hold circuit is a tracking mode, and to connect the first bias load unit to the first signal output unit when the operation mode of the sample and hold circuit is a holding mode;

[0007] A first bias load unit, used to access an externally supplied bias voltage and provide a load; and

[0008] A first signal output unit, used to disconnect the output of the first voltage signal when the working mode of the sample and hold circuit is a tracking mode, and output the first voltage signal when the working mode of the sample and hold circuit is a holding mode;

[0009] The second voltage signal output structure comprises:

[0010] a second switch control unit, used to disconnect the second bias unit from the second signal output unit when the operation mode of the sample and hold circuit is the tracking mode, and to connect the second bias load unit to the second signal output unit when the operation mode of the sample and hold circuit is the holding mode;

[0011] A second bias load unit, used to access an externally supplied bias voltage and provide a load; and

[0012] The second signal output unit is used to disconnect the output of the second voltage signal when the working mode of the sampling and holding circuit is the tracking mode, and output the second voltage signal when the working mode of the sampling and holding circuit is the holding mode.

[0013] Further, the first switch control unit is defined as a first MOS tube M1, a gate of the first MOS tube M1 is connected to the clock signal, a source of the first MOS tube M1 is electrically connected to the first bias load unit, and a drain of the first MOS tube M1 is electrically connected to the first signal output unit; when the clock signal is at a high level, the first MOS tube M1 is turned off, and when the clock signal is at a low level, the first MOS tube M1 is turned on.

[0014] Further, the first bias load unit is defined as a second MOS tube M2, a gate of the second MOS tube M2 is connected to an externally supplied bias voltage, a source of the second MOS tube M2 is connected to a power supply voltage, and a drain of the second MOS tube M2 is electrically connected to a source of the first MOS tube M1.

[0015] Further, the first signal output unit includes a third MOSFET M3, a gate of the third MOSFET M3 is connected to the sampling signal, a drain of the third MOSFET M3 is grounded, and a source of the third MOSFET M3 is electrically connected to the drain of the first MOSFET M1; when the first MOSFET M1 is turned on, the third MOSFET M3 is turned on, and the source of the third MOSFET M3 outputs a first voltage signal; when the first MOSFET M1 is turned off, the third MOSFET M3 is turned off, and the source of the third MOSFET M3 disconnects the output of the first voltage signal.

[0016] Furthermore, the first signal output unit also includes a fourth MOSFET M4, a gate of the fourth MOSFET M4 is connected to the clock signal, a source of the fourth MOSFET M4 is grounded, a drain of the fourth MOSFET M4 is electrically connected to the source of the third MOSFET M3, when the clock signal is at a high level, the fourth MOSFET M4 is turned on, and the source of the third MOSFET M3 outputs a first voltage signal, when the clock signal is at a low level, the fourth MOSFET M4 is turned off, and the drain of the fourth MOSFET M4 is short-circuited to GND.

[0017] Furthermore, it also includes a first step-down unit for reducing the common-mode voltage increased when switching to the holding mode; the first step-down unit is defined as a fifth MOS tube M5, the gate of the fifth MOS tube M5 is connected to the clock signal, the source of the fifth MOS tube M5 is electrically connected to the sampling signal output end of the sample-and-hold circuit to connect the sampling signal, the drain of the fifth MOS tube M5 is electrically connected to the gate of the third MOS tube M3, and the source and drain of the fifth MOS tube M5 are electrically connected.

[0018] Further, the second switch control unit is defined as a sixth MOS tube M6, the gate of the sixth MOS tube M6 is connected to the clock signal, the source of the sixth MOS tube M6 is electrically connected to the second bias load unit, and the drain of the sixth MOS tube M6 is electrically connected to the second signal output unit; when the clock signal is at a high level, the sixth MOS tube M6 is turned off, and when the clock signal is at a low level, the sixth MOS tube M6 is turned on;

[0019] The second bias load unit is defined as a seventh MOSFET M7, a gate of the seventh MOSFET M7 is connected to an externally supplied bias voltage, a source of the seventh MOSFET M7 is connected to a power supply voltage, and a drain of the seventh MOSFET M7 is electrically connected to a source of the sixth MOSFET M6.

[0020] Further, the second signal output unit includes an eighth MOSFET M8, a gate of the eighth MOSFET M8 is connected to the sampling signal, a drain of the eighth MOSFET M8 is grounded, and a source of the eighth MOSFET M8 is electrically connected to the drain of the sixth MOSFET M6; when the sixth MOSFET M6 is turned on, the eighth MOSFET M8 is turned on, and the source of the eighth MOSFET M8 outputs a second voltage signal; when the sixth MOSFET M6 is turned off, the eighth MOSFET M8 is turned off, and the source of the eighth MOSFET M8 disconnects the output of the second voltage signal.

[0021] Furthermore, the second signal output unit also includes a ninth MOSFET M9, a gate of the ninth MOSFET M9 is connected to the clock signal, a source of the ninth MOSFET M9 is grounded, and a drain of the ninth MOSFET M9 is electrically connected to the source of the eighth MOSFET M8; when the clock signal is at a high level, the ninth MOSFET M9 is turned on, and the source of the eighth MOSFET M8 outputs a second voltage signal; when the clock signal is at a low level, the ninth MOSFET M9 is turned off, and the drain of the ninth MOSFET M9 is short-circuited to GND.

[0022] Furthermore, it also includes a second step-down unit for reducing the common-mode voltage increased when switching to the holding mode; the second step-down unit is defined as a tenth MOS tube M10, the gate of the tenth MOS tube M10 is connected to the clock signal, the source of the tenth MOS tube M10 is electrically connected to the sampling signal output end of the sample-and-hold circuit to connect the sampling signal, the drain of the tenth MOS tube M10 is electrically connected to the gate of the eighth MOS tube M8, and the source and drain of the tenth MOS tube M10 are electrically connected.

[0023] The device for improving the switching linearity and bandwidth of a sampling and holding circuit of the present invention has at least the following beneficial effects: the present invention uses time-sharing control to make the output buffer not work when the working mode of the sampling circuit is the tracking mode, and to work when the working mode of the sampling circuit is the holding mode, thereby reducing charge injection in the sampling process and improving linearity and bandwidth; by adding a fourth MOS tube and a ninth MOS tube in the output buffer to pull the voltage of the output point close to 0 in the tracking stage, harmonic distortion is reduced, especially when switching from the tracking mode to the holding mode, the introduction of additional harmonic distortion is avoided; by cleverly designing the first buck unit and the second buck unit, effective control of the common mode voltage is achieved, and circuit performance instability or noise increase caused by an increase in the output voltage is avoided; by using device capacitors and parasitic capacitors as sampling capacitors, the use of additional components is reduced, which not only reduces the volume and weight of the circuit, reduces the cost, but also reduces the parasitic effect, and significantly improves the bandwidth of the overall circuit; the present invention is suitable for high-speed signal processing scenarios, such as high-frequency communication, radar signal processing, etc., and can meet the high requirements of high-speed A / D converters for front-end circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0025] Figure 1 The circuit diagram is a circuit diagram of an output buffer in a device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to an embodiment of the present invention.

[0026] Figure 2 for Figure 1 The output curve of the output buffer is shown.

[0027] Figure 3 The figure is a comparison diagram of the bandwidth of the front-end circuit using a traditional source follower buffer and the output buffer of the present invention.

[0028] Figure 4 The figure is a curve comparison diagram of the THD of the output buffer of the present invention and the conventional continuous working buffer as the input signal fi n changes. DETAILED DESCRIPTION

[0029] The present invention will be further described below in conjunction with the accompanying drawings.

[0030] The device for improving the switching linearity and bandwidth of a sampling and holding circuit of the present invention comprises a sampling and holding circuit and an output buffer electrically connected to the sampling signal output terminal of the sampling and holding circuit. In order to reduce the influence of interference on signal transmission and reduce signal distortion and error, in this embodiment, the output buffer is a differential structure. Figure 1 The output buffer includes a first voltage signal output structure and a second voltage signal output structure, wherein the first voltage signal output structure includes a first switch control unit 100, a first bias load unit 200 and a first signal output unit 300. The first switch control unit 100 is used to disconnect the first bias load unit 200 from the first signal output unit 300 when the working mode of the sample and hold circuit is the tracking mode (sampling mode), and is used to connect the first bias load unit 200 to the first signal output unit 300 when the working mode of the sample and hold circuit is the holding mode; the first bias load unit 200 is used to connect the externally supplied bias voltage and provide a load; the first signal output unit 300 is used to disconnect the first voltage signal V buf_outn output, and output a first voltage signal V when the working mode of the sampling and holding circuit is the holding mode buf_outnTo drive the ADC circuit (A / D converter circuit) of the subsequent stage. The second voltage signal output structure includes a second switch control unit 500, a second bias load unit 600 and a second signal output unit 700. The second switch control unit 500 is used to disconnect the second bias unit from the second signal output unit 700 when the working mode of the sample and hold circuit is the tracking mode, and to connect the second bias load unit 600 to the second signal output unit 700 when the working mode of the sample and hold circuit is the holding mode; the second bias load unit 600 is used to connect the externally supplied bias voltage and provide a load; the second signal output unit 700 is used to disconnect the second voltage signal V when the working mode of the sample and hold circuit is the tracking mode. buf_outp output, and output a second voltage signal V when the working mode of the sampling and holding circuit is the holding mode buf_outp The first voltage signal V buf_outn and the second voltage signal V buf_outp They are differential signals with a phase difference of 180 degrees. Their amplitudes are equal but their phases are opposite. When external interference affects one of the differential signals, the interference will be offset at the receiving end of the differential signal because the other signal is 180 degrees out of phase with it.

[0031] When the operating mode is tracking mode, if the output buffer is working, additional charge injection may be introduced, which will affect the voltage of the sampling capacitor and reduce the bandwidth; if the output buffer only works in the hold mode, the charge injection during the sampling process can be reduced, thereby improving linearity and bandwidth. In addition, when the output buffer works in the hold mode, it can effectively isolate the noise and interference between the input signal and the output signal, which helps to maintain the stability and accuracy of the output voltage, thereby further improving the linearity of the circuit. Please refer to Figure 2 In the hold mode, the output buffer switches to the working state and drives the subsequent A / D converter circuit. Figure 2 shows the operation of the output buffer in hold mode.

[0032] The first switch control unit 100 is defined as a first MOS transistor M1, and the gate of the first MOS transistor M1 is connected to the clock signal CLK <2> The source of the first MOS tube M1 is electrically connected to the first bias load unit 200, and the drain of the first MOS tube M1 is electrically connected to the first signal output unit 300. In this embodiment, the first MOS tube M1 is a pmos tube. <2> When the clock signal CLK is low, the first MOS tube M1 is turned on. <2> When the voltage is high, the first MOSFET M1 is turned off. The first bias load unit 200 is defined as the second MOSFET M2. In the present embodiment, the second MOSFET M2 is a pmos transistor. The gate of the second MOSFET M2 is connected to the externally supplied bias voltage, the drain of the second MOSFET M2 is electrically connected to the source of the first MOSFET M1, and the source of the second MOSFET M2 is connected to the power supply voltage. In the present embodiment, the power supply voltage is 850mV. The first signal output unit 300 includes a third MOSFET M3. In the present embodiment, the third MOSFET M3 is a pmos transistor. The gate of the third MOSFET M3 is connected to the sampling signal, the drain of the third MOSFET M3 is grounded, and the source of the third MOSFET M3 is electrically connected to the drain of the first MOSFET M1. When the first MOSFET M1 is turned on, the current of the second MOSFET M2 flows into the third MOSFET M3, the third MOSFET M3 is turned on, and the source of the third MOSFET M3 outputs the first voltage signal V buf_outn When the first MOS tube M1 is turned off, the DC current of the circuit is cut off, and the third MOS tube M3 is turned off. The source of the third MOS tube M3 is disconnected from the first voltage signal V buf_outn Output.

[0033] The second switch control unit 500 is defined as a sixth MOS transistor M6, and the gate of the sixth MOS transistor M6 is connected to the clock signal CLK <2> The source of the sixth MOS tube M6 is electrically connected to the second bias load unit 600, and the drain of the sixth MOS tube M6 is electrically connected to the second signal output unit 700. In this embodiment, the sixth MOS tube M6 is a pmos tube. When the clock signal CLK <2> When the clock signal CLK is low, the sixth MOS tube M6 is turned on. <2> is high level, the sixth MOSFET M6 is turned off. The second bias load unit 600 is defined as the seventh MOSFET M7. In the present embodiment, the seventh MOSFET M7 is a pmos transistor. The gate of the seventh MOSFET M7 is connected to the bias voltage supplied externally, the source of the seventh MOSFET M7 is connected to the power supply voltage, and the drain of the seventh MOSFET M7 is electrically connected to the source of the sixth MOSFET M6. The second signal output unit 700 includes an eighth MOSFET M8. In the present embodiment, the eighth MOSFET M8 is a pmos transistor. The gate of the eighth MOSFET M8 is connected to the sampling signal, the drain of the eighth MOSFET M8 is grounded, and the source of the eighth MOSFET M8 is electrically connected to the drain of the sixth MOSFET M6; when the sixth MOSFET M6 is turned on, the current of the seventh MOSFET M7 flows into the eighth MOSFET M8, the eighth MOSFET M8 is turned on, and the source of the eighth MOSFET M8 outputs the second voltage signal V buf_outp When the sixth MOS tube M6 is turned off, the DC current of the circuit is cut off, the eighth MOS tube M8 is turned off, and the source of the eighth MOS tube M8 is disconnected from the second voltage signal V buf_outp Output.

[0034] In order to reduce harmonic distortion and improve linearity, as a preferred embodiment, the first signal output unit 300 is further provided with a fourth MOS tube M4. In this embodiment, the fourth MOS tube M4 is a nmos tube. The gate of the fourth MOS tube M4 is connected to the clock signal CLK <2> The source of the fourth MOS tube M4 is grounded, the drain of the fourth MOS tube M4 is electrically connected to the source of the third MOS tube M3, and when the clock signal CLK <2> When the voltage is low, the fourth MOS tube M4 is turned off, and the source of the third MOS tube M3 outputs the first voltage signal V buf_outn , when the clock signal CLK <2> When the voltage is high, the fourth MOS tube M4 is turned on, and the drain of the fourth MOS tube M4 is short-circuited to GND. The fourth MOS tube M4 pulls the voltage of the output point close to 0 in the tracking stage, so that in the clock switching process, that is, the transition from the tracking mode to the holding mode, the feedthrough effect caused by the input signal through the source-drain parasitic capacitance (Cgs) is reduced, thereby reducing the harmonic distortion of the overall structure and improving the linearity.

[0035] Similarly, the second signal output unit 700 is further provided with a ninth MOS transistor M9. In this embodiment, the ninth MOS transistor M9 is an NMOS transistor. The gate of the ninth MOS transistor M9 is connected to the clock signal CLK <2> , the source of the ninth MOS tube M9 is grounded, and the drain of the ninth MOS tube M9 is electrically connected to the source of the eighth MOS tube M8; when the clock signal CLK <2> When the voltage is low, the ninth MOS tube M9 is turned off, and the source of the eighth MOS tube M8 outputs the second voltage signal V buf_outp , when the clock signal CLK <2> When it is at a high level, the ninth MOS tube M9 is turned on, and the drain of the ninth MOS tube M9 is short-circuited to GND.

[0036] In order to avoid introducing harmonic distortion when switching from the tracking mode to the holding mode, as a preferred embodiment, a first step-down unit 400 is provided for reducing the common-mode voltage increased when switching to the holding mode; the first step-down unit 400 is defined as a fifth MOS tube M5. In this embodiment, the fifth MOS tube M5 is an NMOS tube. The gate of the fifth MOS tube M5 is connected to the clock signal CLK <2> , the source of the fifth MOS tube M5 is electrically connected to the sampling signal output end of the sampling and holding circuit to access the sampling signal, the drain of the fifth MOS tube M5 is electrically connected to the gate of the third MOS tube M3, and the source and drain of the fifth MOS tube M5 are electrically connected. When switching to the holding mode, the increase in the output voltage will be coupled to the node of the sampling capacitor, thereby increasing the output common-mode voltage. This increase may cause the instability of the circuit performance or the increase of noise, and have an adverse effect on the overall performance of the circuit. This embodiment cleverly designs the fifth MOS tube M5, and can use it to reduce the clock feedthrough effect to offset the increase in common-mode voltage caused by the increase in output voltage, thereby avoiding the introduction of harmonic distortion and ensuring the output quality of the circuit.

[0037] In the tracking mode, the first MOS tube M1 is turned off, cutting off the DC current of the circuit and disconnecting the first voltage signal V buf_outn The output of the buffer is short-circuited to GND by the fourth MOS tube M4. At the sampling point, the total charge Q stored on the sampling node is obtained by the following formula:

[0038] Q=(V TH_in +V0)(C S +C gs )(one)

[0039] In the formula, V0 represents the input sampling voltage V TH_in The DC voltage. C S Represents all parasitic capacitances on the gate of M5 except Cgs.

[0040] In the hold mode, the first MOSFET M1 is turned on, so that the current of the second MOSFET M2 flows into the third MOSFET M3, and the fourth MOSFET M4 is turned off. The source output voltage signal of the third MOSFET M3 drives the A / D converter circuit of the subsequent stage. T / H,infinal and V buf,outfinal After charge redistribution, V TH,in and V buf,out The final value of V T / H,infinal Obtained by the following formula:

[0041]

[0042] V buf,outfinal Obtained by the following formula:

[0043]

[0044] Where V gs0 Indicates V gs When the DC voltage enters the hold mode, the output voltage V buf,out The increase will be coupled to the node of the sampling capacitor, increasing the common-mode voltage of the output, as shown in the last term of formula (II). In order to alleviate this situation, a fifth MOS tube is added to use its falling edge clock feedthrough to offset the increase in common-mode voltage. Compared with the traditional continuously operating output buffer, formulas (II) and (III) show that the output buffer of the present invention does not introduce harmonic distortion.

[0045] Similarly, a second step-down unit 800 is provided for reducing the common mode voltage increased when switching to the hold mode; the second step-down unit 800 is defined as the tenth MOS tube M10. In this embodiment, the tenth MOS tube M10 is an NMOS tube. The gate of the tenth MOS tube M10 is connected to the clock signal CLK <2> The source of the tenth MOS tube M10 is electrically connected to the sampling signal output end of the sample-and-hold circuit to receive the sampling signal, the drain of the tenth MOS tube M10 is electrically connected to the gate of the eighth MOS tube M8, and the source and drain of the tenth MOS tube M10 are electrically connected.

[0046] In addition, in this embodiment, there is no need to set a dedicated sampling capacitor. The device capacitance of the third MOSFET M3 and the fifth MOSFET M5, the line capacitance, and the parasitic capacitance between the lines are used as sampling capacitors, which can not only reduce the volume and weight of the circuit and improve the integration of the circuit, but also reduce additional components, thereby reducing parasitic effects, improving the circuit bandwidth, and getting rid of the circuit's limitation on the bandwidth of the subsequent A / D converter.

[0047] The designed A / D converter front-end circuit is based on the PDK of smic 12nm fi nfet process, with input common mode voltage Vcom_i n of 125mV, swing of 500Vpp, sampling frequency fs=10GS / s, and power supply voltage of 0.85V. Figure 3 , the bandwidth curves of the output buffer and the source follower output buffer of the present invention can be obtained through circuit simulation. Figure 3 The AC / DC simulation shown shows that the bandwidth of the traditional source follower buffer is only 12.2 GHz, which greatly limits the bandwidth of the front-end circuit of the A / D converter and affects the performance of the A / D converter. The output buffer of the present invention expands the bandwidth to 33.5 GHz.

[0048] See also Figure 4 , which is a comparison chart of the total harmonic distortion (THD) changing with the input signal fin. Through joint simulation with the sample-and-hold circuit, the comparison between the output buffer of the present invention and the conventional continuous working buffer is shown in FIG. Figure 4 As shown in FIG. 1 , the input signal swing is 500 mVppd and the input common mode voltage is 125 mV. It can be seen that, benefiting from the output buffer of the present invention, the THD performance is improved by up to 11 dB for higher input frequencies (eg, 7.5 GHz).

[0049] The present invention uses time-sharing control to prevent the output buffer from working when the working mode of the sampling circuit is the tracking mode, and to work when the working mode of the sampling circuit is the holding mode, thereby reducing charge injection in the sampling process and improving linearity; by adding a fourth MOS tube M4 and a ninth MOS tube M9 in the output buffer to pull the voltage of the output point close to 0 in the tracking stage, harmonic distortion is reduced, especially when switching from the tracking mode to the holding mode, the introduction of additional harmonic distortion is avoided; by cleverly designing the first buck unit 400 and the second buck unit 800, effective control of the common mode voltage is achieved, and circuit performance instability or noise increase caused by an increase in the output voltage is avoided; device capacitors and parasitic capacitors are used as sampling capacitors, reducing the use of additional components, not only reducing the volume and weight of the circuit, reducing the cost, but also reducing the parasitic effect, and significantly improving the bandwidth of the overall circuit; the present invention is suitable for high-speed signal processing scenarios, such as high-frequency communication, radar signal processing, etc., and can meet the high requirements of high-speed A / D converters for front-end circuits.

Claims

1. A device for improving the switching linearity and bandwidth of a sample-and-hold circuit, comprising a sample-and-hold circuit and an output buffer electrically connected to a sampling signal output terminal of the sample-and-hold circuit, characterized in that: The output buffer is a differential structure, including a first voltage signal output structure and a second voltage signal output structure, wherein the first voltage signal output structure includes: a first switch control unit, used to disconnect the first bias load unit from the first signal output unit when the operation mode of the sample and hold circuit is a tracking mode, and to connect the first bias load unit to the first signal output unit when the operation mode of the sample and hold circuit is a holding mode; A first bias load unit, used to access an externally supplied bias voltage and provide a load; and A first signal output unit, used to disconnect the output of the first voltage signal when the working mode of the sample and hold circuit is a tracking mode, and output the first voltage signal when the working mode of the sample and hold circuit is a holding mode; The second voltage signal output structure comprises: a second switch control unit, used to disconnect the second bias unit from the second signal output unit when the operation mode of the sample and hold circuit is the tracking mode, and to connect the second bias load unit to the second signal output unit when the operation mode of the sample and hold circuit is the holding mode; A second bias load unit, used to access an externally supplied bias voltage and provide a load; and The second signal output unit is used to disconnect the output of the second voltage signal when the working mode of the sampling and holding circuit is the tracking mode, and output the second voltage signal when the working mode of the sampling and holding circuit is the holding mode.

2. The device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to claim 1, characterized in that: The first switch control unit is defined as a first MOS tube M1, a gate of the first MOS tube M1 is connected to the clock signal, a source of the first MOS tube M1 is electrically connected to the first bias load unit, and a drain of the first MOS tube M1 is electrically connected to the first signal output unit; when the clock signal is at a high level, the first MOS tube M1 is turned off, and when the clock signal is at a low level, the first MOS tube M1 is turned on.

3. The device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to claim 2, characterized in that: The first bias load unit is defined as a second MOS M2, a gate of the second MOS M2 is connected to an externally supplied bias voltage, a source of the second MOS M2 is connected to a power supply voltage, and a drain of the second MOS M2 is electrically connected to a source of the first MOS M1.

4. The device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to claim 2, characterized in that: The first signal output unit includes a third MOSFET M3, a gate of the third MOSFET M3 is connected to a sampling signal, a drain of the third MOSFET M3 is grounded, and a source of the third MOSFET M3 is electrically connected to the drain of the first MOSFET M1; when the first MOSFET M1 is turned on, the third MOSFET M3 is turned on, and the source of the third MOSFET M3 outputs a first voltage signal; when the first MOSFET M1 is turned off, the third MOSFET M3 is turned off, and the source of the third MOSFET M3 disconnects the output of the first voltage signal.

5. The device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to claim 4, characterized in that: The first signal output unit also includes a fourth MOSFET M4, a gate of the fourth MOSFET M4 is connected to the clock signal, a source of the fourth MOSFET M4 is grounded, a drain of the fourth MOSFET M4 is electrically connected to the source of the third MOSFET M3, when the clock signal is at a high level, the fourth MOSFET M4 is turned on, and the source of the third MOSFET M3 outputs a first voltage signal, when the clock signal is at a low level, the fourth MOSFET M4 is turned off, and the drain of the fourth MOSFET M4 is short-circuited to GND.

6. The device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to claim 4, characterized in that: It also includes a first step-down unit for reducing the common-mode voltage increased when switching to the holding mode; the first step-down unit is defined as a fifth MOS tube M5, the gate of the fifth MOS tube M5 is connected to the clock signal, the source of the fifth MOS tube M5 is electrically connected to the sampling signal output end of the sample-and-hold circuit to connect the sampling signal, the drain of the fifth MOS tube M5 is electrically connected to the gate of the third MOS tube M3, and the source and drain of the fifth MOS tube M5 are electrically connected.

7. The device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to claim 1, characterized in that: The second switch control unit is defined as a sixth MOS tube M6, the gate of the sixth MOS tube M6 is connected to the clock signal, the source of the sixth MOS tube M6 is electrically connected to the second bias load unit, and the drain of the sixth MOS tube M6 is electrically connected to the second signal output unit; when the clock signal is at a high level, the sixth MOS tube M6 is turned off, and when the clock signal is at a low level, the sixth MOS tube M6 is turned on; The second bias load unit is defined as a seventh MOSFET M7, a gate of the seventh MOSFET M7 is connected to an externally supplied bias voltage, a source of the seventh MOSFET M7 is connected to a power supply voltage, and a drain of the seventh MOSFET M7 is electrically connected to a source of the sixth MOSFET M6.

8. The device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to claim 7, characterized in that: The second signal output unit includes an eighth MOSFET M8, a gate of the eighth MOSFET M8 is connected to the sampling signal, a drain of the eighth MOSFET M8 is grounded, and a source of the eighth MOSFET M8 is electrically connected to the drain of the sixth MOSFET M6; when the sixth MOSFET M6 is turned on, the eighth MOSFET M8 is turned on, and the source of the eighth MOSFET M8 outputs a second voltage signal; when the sixth MOSFET M6 is turned off, the eighth MOSFET M8 is turned off, and the source of the eighth MOSFET M8 disconnects the output of the second voltage signal.

9. The device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to claim 8, characterized in that: The second signal output unit also includes a ninth MOSFET M9, a gate of the ninth MOSFET M9 is connected to the clock signal, a source of the ninth MOSFET M9 is grounded, and a drain of the ninth MOSFET M9 is electrically connected to the source of the eighth MOSFET M8; when the clock signal is at a high level, the ninth MOSFET M9 is turned on, and the source of the eighth MOSFET M8 outputs a second voltage signal; when the clock signal is at a low level, the ninth MOSFET M9 is turned off, and the drain of the ninth MOSFET M9 is short-circuited to GND.

10. The device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to claim 8, characterized in that: It also includes a second step-down unit for reducing the common-mode voltage increased when switching to the holding mode; the second step-down unit is defined as a tenth MOS tube M10, the gate of the tenth MOS tube M10 is connected to the clock signal, the source of the tenth MOS tube M10 is electrically connected to the sampling signal output end of the sample-and-hold circuit to connect the sampling signal, the drain of the tenth MOS tube M10 is electrically connected to the gate of the eighth MOS tube M8, and the source and drain of the tenth MOS tube M10 are electrically connected.

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