Extensible distributed simultaneous digital multi-beam processing architecture for large-scale digital array

Abstract

The invention discloses an extensible distributed simultaneous digital multi-beam processing architecture for a large-scale digital array, which performs hierarchical processing by taking five processing nodes as a basic unit and comprises two types of processing nodes, namely a multi-channel sampling and sub-array beam forming node and an accumulation switching node. According to the method, the level number of the whole processing architecture is determined according to the array scale, a bidirectional full interconnection structure is adopted for data interaction of five processing nodes in each layer, and data interaction and level crossing are carried out between levels by accumulating exchange nodes. The processing architecture adopts a distributed structure, and the interaction data rate among all processing nodes is only related to the sampling data rate determined by the signal bandwidth and the number of simultaneously formed digital beams, and is not related to the scale of the array antenna unit, so that the expansion of a large-scale array can be flexibly realized. Under the large-scale array application background, node processing load balancing and distributed on-array processing are achieved.

Description

Technical Field

[0001] The present application relates to the field of digital array signal technology, and in particular to a scalable distributed simultaneous digital multi-beam processing architecture for large-scale digital arrays. Background Art

[0002] At present, digital array antennas are widely used in radar, communication, sonar and other fields. With the continuous improvement of application requirements, the requirements for antenna system gain, anti-interference, spatial positioning and resolution are also increasing. With the increase of antenna aperture, the significant increase in the size of digital array elements will lead to an increase in baseband data rate and an increase in the complexity of digital beamforming processing, while ensuring that the spacing between array elements meets the requirements of spatial scanning without grating lobes. Therefore, it is very necessary to study the distributed implementation and scale-expanding processing architecture suitable for large-scale digital receiving array antennas.

[0003] Currently, the commonly used processing architectures include centralized and distributed. In the centralized processing architecture, the aggregation and processing of all channel baseband data are completed on the central processing unit, and the data aggregation data rate and data processing complexity increase linearly with the increase in the number of array elements. In large-scale array application scenarios, the centralized processing architecture will bring bottlenecks in data transmission bandwidth and centralized processing, while the distributed processing architecture distributes the digital beamforming processing of baseband data in each processing node of the digital array. Each node connects some array elements to perform simultaneous digital multi-beamforming at the sub-array level, and only beam data needs to be exchanged between nodes. In the distributed processing architecture, data reception and processing are evenly distributed in each processing node, and data interaction between nodes is only related to the beam data rate and the number of beams, and has nothing to do with the array scale, thereby eliminating the bottleneck of increased data bandwidth and computational complexity caused by the increase in array scale. However, the existing distributed architecture still has the problem that sub-array beamforming data needs to be centralized and processed. Summary of the invention

[0004] The present application provides a scalable distributed simultaneous digital multi-beam processing architecture for large-scale digital arrays, which can be used to solve the technical problem that sub-array beamforming data still needs to be centrally aggregated for processing in a distributed architecture.

[0005] Before specifically introducing the architecture provided by this application, the principle of this application is first explained.

[0006] For a receiving digital array antenna system, the number of array elements is Q, the number of receiving beams is M, and the beam data rate is S. The receiving digital beamforming output signal vector is expressed as:

[0007] y(t)=W H x(t)(1)

[0008] Among them, the digital array multi-beam output y(t)=[y1(t)y2(t)…y m (t)…y M (t)] T , digital array element input x(t)=[x1(t)x2(t)…x q (t)…x Q (t)] T , multi-beam weight coefficient W=[w1 w2 … w m … w M ], where the weight vector of the mth beam is specifically expressed as:

[0009] w m =[w m,1 w m,2 … w m,q … w m,Q ] T .

[0010] First, the matrix is ​​divided into blocks from the array element dimension, and all array elements are divided into K blocks (K is a divisor of Q and M). Each block corresponds to a sub-matrix with N = Q / K array elements. The array data after block division is expressed as:

[0011]

[0012] Among them, the input of the kth (k=1, 2, 3…, K) sub-array element is:

[0013] x k (t) = [x N(k-1)+1 (t) x N(k-1)+2 (t) … x Nk (t))] T (3)

[0014] The weight coefficients of the M beams of the kth subarray are obtained as follows:

[0015] W k =[w 1,k w 2,k … w m,k … w M,k ] (4)

[0016] The block weight vector of the mth beam is expressed as:

[0017]

[0018] The obtained k-th sub-array m-th beam weight coefficient is expressed as:

[0019] w m,k =[wm,N(k-1)+1 w m,N(k-1)+2 … w m,Nk ] T (6)

[0020] Get the kth subarray M beam output y k (t) is:

[0021]

[0022] The beam output y(t) of the entire array is:

[0023]

[0024] From formula (7), we can see that the pressure of baseband data reception and digital beamforming is evenly distributed to K sub-arrays through the block division of the array element dimension. The data rate received by each sub-array processing node and the complexity of digital beamforming are both 1 / K of the original. However, from formula (8), we can see that the beam output of the entire array is the result of the addition of the beams of all sub-array processing nodes. As the number of sub-array processing nodes increases, the converged beam data becomes larger, and the difficulty of hardware implementation will also increase. Through the block division of the beam dimension, each sub-array processing node is responsible for the convergence of part of the beams. The data rate when the beams converge is shared through the data interaction between the sub-array processing nodes, so that the data rate when the beams converge is only related to the number of beams and the beam data rate, and has nothing to do with the number of sub-array processing nodes.

[0025] The kth subarray M beam outputs y k (t) is:

[0026] y k (t) = [y 1,k (t)y 2,k (t)…y m,k (t)…y M,k (t)] T (9)

[0027] The converged output y of the mth beam m (t) is:

[0028] y m (t) = y m,1 (t)+y m,2 (t)+…+y m,k (t)+…+y m,K (t) (10)

[0029] Each subarray processing node outputs M / K beams, and the kth subarray outputs y' k (t) is:

[0030]

[0031] In this way, the number of beams gathered by each subarray processing node is 1 / K of the original number, that is, the total data rate of the beam data is only related to the number of beams M and the beam data rate S, and has nothing to do with the number of subarrays (i.e., array scale). However, as the number of subarrays K increases, the beam interconnection network between subarray processing nodes will become complex, and the hardware implementation will become more difficult. A multi-layer fully interconnected approach is adopted to reduce the number of fully interconnected subarray processing nodes, that is, the subarray processing nodes are further divided into blocks according to the above method until the number of fully interconnected subarray processing nodes at the bottom layer meets the hardware implementation requirements.

[0032] According to the above theoretical analysis, the present application provides a multi-level scalable distributed simultaneous digital multi-beam processing architecture. In order to ensure the functional consistency of the processing nodes and the scalability of the architecture, the number of sub-array blocks in each layer is 4. For the distributed processing architecture of the P layer, the number of sub-array elements N and the total number of array elements Q satisfy Q = N × 4 (P-1) . The first layer of this architecture adopts a hierarchical structure with 5 nodes as basic units; each unit in the first layer includes 4 multi-channel sampling and sub-array beamforming nodes and 1 cumulative exchange node; starting from the second layer, each unit in each layer contains 5 cumulative exchange nodes; among them, the multi-channel sampling and sub-array beamforming node has 1 set of fully interconnected data interaction interfaces, and the cumulative exchange node has two sets of fully interconnected data interaction interfaces; this processing architecture uses 1 of the 5 processing nodes of the basic unit of each layer as the master node, and the other 4 are slave nodes. The slave nodes need to process and exchange data, and the master node only receives slave node data for processing. For the p-layer distributed processing architecture, the p layer has L cumulative exchange nodes, the number of sub-array elements is N, and the number of elements in the entire array is Q = L×N×4 (p -1) .

[0033] Furthermore, in the hierarchical structure of the first layer, the four multi-channel sampling and sub-array beamforming forming nodes and one accumulation switching node of each unit are interconnected by a set of fully interconnected data interaction interfaces for distributed array processing.

[0034] Furthermore, each multi-channel sampling and sub-array beamforming node is a first-layer slave node, samples N-channel analog signals, the sampling data rate is S, and performs digital beamforming of M beams of N array elements; then, the beamformed data of M / 4 beams are sent to the remaining three multi-channel sampling and sub-array beamforming nodes respectively through the fully interconnected data interaction interface, and the interaction data rate between nodes is (M×S) / 4; at the same time, the beamformed data of M / 4 beams from the remaining three multi-channel sampling and sub-array beamforming nodes are received, and the beamformed data of M / 4 beams retained by the node are accumulated to obtain the beamformed data of M / 4 beams of 4N array elements, and output it to the first-layer accumulation exchange node, and the data rate of the sent data is (M×S) / 4.

[0035] The cumulative switching nodes of the first layer participate in the construction of the first and second level fully interconnected networks through two sets of fully interconnected data interaction interfaces. In the first layer, the accumulation switching node is the master node, and receives the beamformed data of M / 4 beams of each 4N array element from the remaining 4 multi-channel sampling and sub-array beamforming nodes of the same unit through the first group of fully interconnected data interaction interfaces, and obtains the beamformed data of M beams of 4N array elements; at the same time, the accumulation switching node is also the second layer slave node, and sends the beamformed data of M / 4 beams to the remaining 3 accumulation switching nodes (slave nodes) of the second level through the second group of fully interconnected data interaction interfaces, and the data rate is (M×S) / 4. At the same time, it receives the beamformed data of each M / 4 beam from the remaining 3 accumulation switching nodes of the second layer, and completes the accumulation with the beamformed data of M / 4 beams retained by this node, to obtain the beamformed data of M / 4 beams of 16N array elements, and outputs it to the fifth accumulation switching node (master node) of the second layer, and the data rate of the sent data is (M×S) / 4.

[0036] Furthermore, starting from the second layer, each unit of each layer of the architecture contains 5 cumulative exchange nodes, and each node interacts with data through two sets of fully interconnected data interaction interfaces. Among them, 4 nodes are slave nodes of the current layer and are also master nodes of the previous layer, and the other node is the master node of the current layer and is also a slave node of the next layer.

[0037] Furthermore, the p-th layer (p = 2, 3, ...) cumulative exchange master nodes participate in the construction of the p-th layer and the p+1-th layer of two-level fully interconnected networks. At the p-th layer, the cumulative exchange node is the master node, and receives 4 packets from the remaining 4 cumulative exchange slave nodes of the current layer through the first set of fully interconnected data interaction interfaces. p After beamforming of N array elements and M / 4 beams, we get 4 pThe node is a slave node at the p+1th layer, and sends the beamformed data of M / 4 beams to the remaining three accumulation exchange nodes at the p+1th layer through the second group of fully interconnected data interaction interfaces, with the data rate being (M×S) / 4. At the same time, it receives the beamformed data of each of the M / 4 beams from the accumulation exchange slave nodes at the remaining three p+1th layers, and completes the accumulation with the beamformed data of the M / 4 beams retained by the node, and obtains 4 p+1 The beamformed data of M / 4 beams of N array elements are output to the p+1 layer accumulation exchange master node, with a data rate of (M×S) / 4.

[0038] Furthermore, in order to ensure stable and distortion-free transmission of bandwidth data between nodes in the distributed processing architecture, the data interaction between the above nodes adopts a customized layered transmission specification, which specifically includes two parts: the data link layer and the physical layer.

[0039] Furthermore, the data link layer receives the parallel data of the transport layer, frames the data according to the customized data link layer frame protocol, and manages the data transmission link through the frame protocol to ensure the stability and accuracy of data transmission. The data link layer frame protocol sets the frame header and frame trailer in the data frame to complete the frame delimitation. The receiving end can identify the beginning and end of the frame according to the frame header and frame trailer. The frame header and frame trailer are the key information for the digital signal processor to identify the valid data frame from the continuous data stream. It is necessary to ensure the specificity of the two to prevent the payload data from being mistakenly identified as the frame header and frame trailer, and to ensure that the length of the frame header and frame trailer is short enough to minimize the consumption of link resources. Combined with the transmission characteristics of the high-speed serial interface, the frame header and frame tail adopt the data format of K code plus D code to ensure that the two are different from the transmitted payload data and the length is also small; the MAC address is set in the data frame to facilitate the positioning of the node and realize the directional transmission of data such as command response between nodes, ensuring that the data can be accurately transmitted to the target node; a timestamp is set in the data frame to mark the logical time when the data in the data frame is generated, which is used for data alignment of beamforming; a check bit is set in the data frame to check whether there is an error in data transmission and realize error control of data transmission.

[0040] Furthermore, the physical layer mainly establishes physical connections between nodes to transmit bit stream data. It is responsible for serial-to-parallel conversion of data and receiving and sending 8B / 10B encoded data at line rate. It includes a serial / deserializer, a driver, a receiver and a clock data recovery (CDR) module. Each module adopts a customized unit design. The serial / deserializer serializes the 8B / 10B encoded parallel data to be sent or parallelizes the received serial data to facilitate bit transmission; the driver is used at the transmitting end, supports pre-emphasis and post-emphasis operations, and increases the energy proportion of the high-frequency part of the signal to compensate for the damage of the channel to the high-frequency part; the receiver is used at the receiving end, supports receive equalization operations, and adjusts the corresponding parameters according to the link eye diagram to determine the current state of the link so that the bit error rate of the link transmission meets the requirements.

[0041] Furthermore, in order to ensure the reliability of data transmission between nodes and the real-time performance of data processing, short frame continuous transmission is adopted for data transmission. Data frames at the data link layer are continuously sent in the form of short frames. When there is user data, the user data is segmented, framed and transmitted according to the established frame protocol. When there is no user data, the user data transmission is replaced by data 0. In this way, since the data frame is short, the receiving end can receive and parse a frame of data in a short time for subsequent processing, thereby realizing real-time data processing. Since the data link layer data frames are continuously transmitted, the data link is in a stable transmission state, thereby improving the stability of data transmission.

[0042] Furthermore, the difficulty in implementing a distributed processing architecture is to ensure data consistency between nodes within the architecture. The present invention uses a data synchronization method of timestamp synchronization and pulse synchronization to ensure alignment of data of all nodes in each layer.

[0043] The processing clocks of all nodes in the distributed processing architecture of the present invention are generated by an external clock source through multi-stage power division, and the working clocks of all nodes are kept synchronous, thereby avoiding the data buffer depth between nodes caused by clock offset.

[0044] Array element-level data synchronization adopts a multi-level pulse synchronization method. The specific implementation steps are as follows:

[0045] Step 1: Establish a system synchronization network, select the cumulative exchange master node of a unit at the top level as the master control node, the master control node generates a synchronization pulse output to all remaining nodes, and uses path loopback, IDELAY delay and other methods to ensure that the synchronization pulse signal reaches all nodes at the same time;

[0046] Step 2: The master control node is triggered by the local module to generate a synchronization pulse signal, synchronize the sampling clocks of the analog-to-digital converters of all multi-channel sampling and sub-array beamforming nodes, and achieve data sampling synchronization;

[0047] Step 3: After the data sampling synchronization is completed, the master control node is triggered by the local module to generate the first-level synchronization pulse signal, confirm that all processing nodes have entered the synchronization state, clear the corresponding cache, and wait for the synchronous sampling data to be loaded;

[0048] Step 4: The master control node generates a second-level synchronization pulse signal to complete the synchronous loading of all node sampling data into the cache to achieve data synchronization.

[0049] Beam-level data synchronization uses timestamp synchronization to package and transmit data obtained by synchronous sampling of all nodes in the same frame format. After synchronous reception of the first-layer baseband data, the data is segmented according to the data frame length. Each segment of data of all nodes in this layer is timestamped according to the logical time. After that, data transmission and data processing at all levels determine the consistency of the data based on the timestamp. The data inconsistency caused by inconsistent delays in different transmission channels between nodes will be solved by aligning the multi-frame data FIFO cache.

[0050] Compared with the prior art, the present invention has the following advantages:

[0051] (1) The present invention provides a distributed simultaneous digital multi-beam processing architecture, which realizes node processing load balancing and distributed array processing. The data rate of interaction between nodes is only related to the number of beams and the beam data rate, and has nothing to do with the number of array elements. In the context of large-scale array applications, it solves the bottlenecks of data transmission bandwidth and centralized processing in the centralized processing architecture. (2) The distributed processing architecture proposed in the present invention is scalable and can flexibly adjust the number of nodes and the number of levels in the architecture to adapt to arrays of different sizes. It is very suitable for establishing a universal simultaneous digital multi-beam processing platform. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 Schematic diagram of a multi-level scalable distributed simultaneous digital multi-beam processing architecture;

[0053] Figure 2 Schematic diagram of a two-level scalable distributed simultaneous digital multi-beam processing architecture;

[0054] Figure 3 Schematic diagram of a two-level scalable distributed simultaneous digital multi-beam processing architecture with 1 unit and 5 nodes fully interconnected at the first level;

[0055] Figure 4 Schematic diagram of a two-level scalable distributed simultaneous digital multi-beam processing architecture with 1 unit and 3 nodes fully interconnected at the second layer;

[0056] Figure 5 Data link layer data frame structure;

[0057] Figure 6Two-stage scalable distributed simultaneous digital multi-beam processing architecture with multi-node synchronized pulse paths. DETAILED DESCRIPTION

[0058] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0059] The following first introduces the embodiments of the present application in conjunction with the accompanying drawings.

[0060] For the actual simultaneous digital multi-beam smart antenna system development requirements, the number of antenna array elements N = 192, the number of receiving beams M = 48, and the receiving baseband signal data rate S = 64MSPS. Based on the above theoretical analysis, a specific example of a two-level scalable distributed simultaneous digital multi-beam processing architecture is given.

[0061] The two-level scalable distributed simultaneous digital multi-beam processing architecture is as follows: Figure 2 As shown, K and J are 3 and 4 respectively, then the number of sub-array elements N=16, that is, the first layer includes 3 processing units (the figure only shows 4 multi-channel sampling and sub-array beamforming nodes of 1 unit), each processing unit includes 4 multi-channel sampling and sub-array beamforming nodes and one accumulation and switching node; the second layer includes 1 processing unit, which includes 3 accumulation and switching nodes, and the 3 accumulation and switching nodes shown in the figure are both the accumulation and switching master nodes of the first layer and the accumulation and switching slave nodes of the second layer, playing the role of connecting the upper and lower layers in series.

[0062] The multi-channel sampling and sub-array beamforming node is responsible for the sampling and reception of array data and the first-level distributed simultaneous digital multi-beamforming. The internal functional modules include data acquisition and reception module, synchronization module, first-level beamforming module, beam data transmission module (data interface module) and second-level beamforming module. The signal sampling and data receiving module uses an integrated signal sampling and data receiving module chip, and other modules are implemented in FPGA; the signal sampling and data receiving module implements down-conversion, sampling, extraction and filtering of the received array data to obtain baseband data; the baseband data and weight data are transmitted in the first-level beamforming module. 48 beams corresponding to 16 array elements (the number of sub-array elements) are obtained in the block. Each unit has 4 multi-channel sampling and sub-array beamforming nodes. For node 1, beams 1 to 12 are retained locally and the data of the same beams 1 to 12 of the other three nodes are received. The beam data corresponding to the four groups of array elements are obtained by the secondary beamforming module to obtain 64-element beams 1 to 12. Similarly, nodes 2, 3, and 4 output 64-element beams 13 to 24, beams 25 to 36, and beams 37 to 48, respectively. The beams of the four nodes are all converged to the cumulative exchange node of the current unit. When converged, the total beam data rate is 3.072GSPS.

[0063] The accumulative switching node is used to connect the first layer and the second layer in series. The internal functional modules mainly include beam data transmission module, three-level beam forming module and synchronization module. In the first layer, one accumulative switching node acts as the master node of one unit, receiving beam data gathered from four multi-channel sampling and sub-array beam forming nodes. Each accumulative switching node obtains 64 array elements and 48 beams. In the second layer, the accumulative switching node acts as a slave node, such as Figure 2 As shown, in this example, the second layer has only one unit, and the unit contains only three cumulative exchange slave nodes. For node 1, it retains beams 1 to 16 locally and receives beams 1 to 16 from the other two nodes. The beam data corresponding to the four groups of array elements are obtained by the three-level beamforming module to obtain beams 1 to 16 of 192 array elements. Similarly, nodes 2 and 3 obtain beams 17 to 32 and beams 33 to 48 of 192 array elements respectively. The beam data after the three-level beamforming of the slave nodes are directly gathered and output to the back-end communication processor.

[0064] The two-level scalable distributed simultaneous digital multi-beam processing architecture ensures stable and distortion-free transmission of data between all nodes through a customized layered transmission specification, which specifically includes two parts: the data link layer and the physical layer.

[0065] The data link layer receives the parallel data from the transport layer, frames the data according to the custom data link layer frame protocol, and manages the data transmission link through the frame protocol to ensure the stability and accuracy of data transmission. The data link layer frame protocol sets the frame header and frame trailer in the data frame to complete the frame delimitation. The receiving end can identify the beginning and end of the frame based on the frame header and frame trailer. The frame header and frame trailer are the key information for the digital signal processor to identify valid data frames from the continuous data stream. It is necessary to ensure the specificity of the two to prevent the payload data from being mistakenly identified as the frame header and frame trailer, and to ensure that the length of the frame header and frame trailer is short enough to minimize the consumption of link resources. Combined with the transmission characteristics of the high-speed serial interface, the frame header and frame tail adopt the data format of K code plus D code to ensure that the two are different from the transmitted payload data and the length is also small; the MAC address is set in the data frame to facilitate the positioning of the node and realize the directional transmission of data such as command response between nodes, ensuring that the data can be accurately transmitted to the target node; a timestamp is set in the data frame to mark the logical time when the data in the data frame is generated, which is used for data alignment of beamforming; a check bit is set in the data frame to check whether there is an error in data transmission and realize error control of data transmission.

[0066] The physical layer is implemented based on high-speed serial transceivers and the VPX 6U hardware interconnect bus that complies with the VITA48 standard. Each processing node forms a multi-level mesh interconnect architecture based on this.

[0067] High-speed serial transceivers include 8B / 10B codec modules, serializers / deserializers, drivers, receivers, and clock data recovery modules.

[0068] The 8B / 10B codec module performs 8B / 10B codec on the received and transmitted data to achieve DC balance, preventing signal transmission errors caused by voltage levels due to multiple bits of logic 1 or logic 0 in the high-speed serial stream not changing, and also facilitating the recovery of the data clock of the CDR module.

[0069] The serializer / deserializer serializes the 8B / 10B encoded parallel data to be sent or parallelizes the received serial data to facilitate bit transmission. The implementation of the serializer / deserializer adopts the double-edge sampling (Double Data Rate, DDR) working mode, and adopts the strategy of area for speed to reduce the proportion of high-frequency circuits in the circuit and reduce circuit noise. In addition to parallelizing the serial data, the deserializer also has a logic alignment function, which is to use the characteristic codeword K code to complete the boundary determination of the parallel data to form the correct parallel data.

[0070] The driver acts on the transmitting end, that is, the forward feedback equalizer, which is used to compensate for the damage of the channel to the signal. The data transmission channel is simplified into a low-pass filter in the frequency domain. The high-frequency part of the transmission signal will be damaged if it is higher than the cutoff frequency. The forward feedback equalizer is understood as a high-pass filter in the frequency domain, which compensates for the high-frequency part of the transmission signal and makes up for the damage of the high-frequency signal; in the time domain, it is reflected as pre-emphasis and de-emphasis. Pre-emphasis keeps the low-frequency part of the signal unchanged and improves the high-frequency part of the signal, and de-emphasis attenuates the low-frequency part of the signal and keeps the high-frequency part of the signal. Both are aimed at increasing the energy proportion of the high-frequency part of the signal to compensate for the damage of the channel to the high-frequency part.

[0071] The receiver is used at the receiving end. Its goal is the same as that of the forward feedback equalizer. It is usually implemented using a linear equalizer. Its gain for high-frequency components is greater than that for low-frequency components. It is used to increase the energy proportion of the high-frequency part of the signal.

[0072] The clock data recovery module, as the name implies, recovers the clock from high-speed serial data. Based on a digital phase-locked loop and a phase interpolator, the CDR captures the frequency of the data edge jumps to recover the clock, and then aligns the recovered clock with the data edge to recover the transmitted data. Thanks to the previous 8B / 10B encoding, the serial data will maintain a high-frequency jump, improving the accuracy of the recovered clock.

[0073] The mesh interconnection architecture is based on the VPX backplane component to complete the point-to-point communication between each node. The backplane adopts a stacked design, which can effectively improve the signal transmission quality and reduce crosstalk and electromagnetic interference. The high-speed serial single-channel data rate of this design can reach 6.25Gbps, meeting the interactive needs of large-bandwidth beam data between each node. The high-speed fully interconnected network design of each unit and the fully interconnected network design between cumulative switching nodes are as follows: Figure 3 and Figure 4 As shown in the figure, each node is connected to the backplane through the P0-P6 ports to complete the interconnection between the nodes. The distributed system completes the point-to-point star-shaped full mesh (Full Mesh) between one master node and four slave nodes in the layer through the P1 and P3 ports. The data throughput of the interconnection within a single processing unit can reach 100Gbps; similarly, the point-to-point star-shaped full mesh between the nodes between layers is completed through P5 and P6. The multi-level star-shaped full-interconnection hardware interconnection structure meets the requirements of the two-level distributed simultaneous digital multi-beam processing architecture.

[0074] In order to ensure the stability and real-time performance of data transmission, the data link layer adopts a short frame continuous transmission mode, that is, the data frame of the data link layer is continuously sent in the form of short frames. When there is user data, the user data is segmented, framed and transmitted according to the established frame protocol; when there is no user data, the user data transmission is replaced by data 0. In this way, since the data frame is short, the receiving end can receive and parse a frame of data in a short time for subsequent processing, thereby realizing real-time data processing; since the data link layer data frame is continuously transmitted, the data link is in a stable transmission state, thereby improving the stability of data transmission. In the embodiment of the present application, the data transmission rate of the high-speed serial data interface is 5.12GB / s, the data link layer data frame length is 2048 points, the data bit width is 32bit, and the single-frame data transmission time is only 4us, which meets the real-time requirements of the system.

[0075] The two-level scalable distributed simultaneous digital multi-beam processing architecture ensures the consistency of data of all nodes in each layer by adopting a data synchronization scheme of timestamp synchronization and pulse synchronization.

[0076] The processing clocks of all nodes in the distributed processing architecture are generated by an external clock source through multi-level power division. In this way, after completing one clock synchronization, the working clocks of all nodes will always remain synchronized, avoiding the need for frequent clock synchronization between nodes due to clock offset.

[0077] Pulse synchronization technology, the specific implementation steps are as follows:

[0078] Step 1: Establish a system synchronization network, as follows Figure 6 As shown, the top-level cumulative exchange master node 1 is selected as the master node. The master node generates synchronization pulses and outputs them to the multi-channel sampling and sub-array beamforming nodes of this unit. Figure 5 As shown in path 1, on the other hand, it is output to the remaining two accumulation switching nodes and then forwarded to the multi-channel sampling and sub-array beamforming nodes of their respective units, that is, Figure 6 Path 2 and Path 3 shown in the figure use path loopback, IDELAY delay and other methods to achieve synchronous pulse signals reaching all nodes at the same time;

[0079] Step 2: The master control node is triggered by the local module to generate the first-level synchronization pulse signal, confirm that all processing nodes have entered the synchronization state, clear the corresponding cache, and wait for the synchronization data to be loaded;

[0080] Step 3: After the cache is cleared, the master control node generates a second-level synchronization pulse signal to complete the synchronous loading of all node data into the cache, thereby realizing synchronous input of sampled data.

[0081] Timestamp synchronization packages the data of all nodes in the same frame format for transmission. After synchronous reception of the first-layer baseband data, the data is segmented according to the data frame length. Each segment of data of all nodes in this layer is timestamped according to the logical time. After that, data transmission and data processing at all levels determine the consistency of data based on the timestamp. The data inconsistency caused by transmission delay between nodes is resolved by aligning the multi-frame data FIFO cache.

[0082] The present invention provides a distributed simultaneous digital multi-beam processing architecture, which realizes node processing load balancing and distributed array processing. The data rate of interaction between nodes is only related to the number of beams and the beam data rate, and has nothing to do with the array scale. In the context of large-scale array applications, the bottlenecks of data transmission bandwidth and centralized processing in the centralized processing architecture are solved. In addition, the present invention has the characteristic of scalability, and can adapt to arrays of different scales by flexibly adjusting the number of nodes and the number of levels in the architecture. It is very suitable for establishing a universal simultaneous digital multi-beam processing platform.

[0083] In the context of large-scale array applications, the present invention realizes node processing load balancing and distributed array processing, solving the problem of the existing centralized processing architecture that the amount of baseband data aggregation and data processing complexity are concentrated, and the array scale expansion flexibility is poor due to the proportionality with the array scale. The processing architecture of the present invention is particularly suitable for the realization and scale expansion of large-scale digital receiving array antennas.

[0084] The above-described embodiments of the present application do not constitute a limitation on the protection scope of the present application.

Claims

1. A scalable distributed simultaneous digital multi-beam processing architecture for large-scale digital arrays, characterized by: The architecture includes a hierarchical structure of digital multi-beam forming using five processing nodes as basic units; Among them, each unit in the first layer includes 4 multi-channel sampling and sub-array beamforming nodes and 1 accumulation exchange node; starting from the second layer, each unit in each layer contains 5 accumulation exchange nodes; The multi-channel sampling and sub-array beamforming nodes have a set of fully interconnected data interaction interfaces, while the accumulation exchange node has two sets of fully interconnected data interaction interfaces; Among the five processing nodes of each layer's basic unit, one is the master node and the other four are slave nodes. The slave nodes process and exchange data with each other, and the master node only receives and processes the data from the slave nodes. The master node of the current layer is also the slave node of the next layer; Data interaction between nodes uses a custom layered transmission specification, including the data link layer and the physical layer.

2. The architecture according to claim 1, characterized in that The data interaction form of each node in the first layer is as follows: Each multi-channel sampling and sub-array beamforming node is a first-layer slave node, samples N-channel analog signals, has a sampling data rate of S, and performs digital beamforming of M beams of N array elements; Then, the beamforming data of M / 4 beams are sent to the remaining three multi-channel sampling and sub-array beamforming nodes through the fully interconnected data interaction interface, and the data rate of the interaction between the nodes is (M×S) / 4; at the same time, the beamforming data of M / 4 beams from the remaining three multi-channel sampling and sub-array beamforming nodes are received, and the beamforming data of M / 4 beams retained by the node are accumulated to obtain the beamforming data of M / 4 beams of 4N array elements, and output to the first-layer accumulation exchange node, and the data rate of the sent data is (M×S) / 4; The cumulative switching nodes at the first layer participate in the construction of the first and second level fully interconnected networks through two sets of fully interconnected data interaction interfaces; At the first layer, the accumulation exchange node is the main node, which receives the beamformed data of each of 4N array elements M / 4 beams from the other four multi-channel sampling and sub-array beamforming nodes of the same unit through the first group of fully interconnected data interaction interfaces, and obtains the beamformed data of 4N array elements M beams; At the same time, the accumulation switching node of the first layer is also the slave node of the second layer. It sends the beamformed data of M / 4 beams to the remaining three accumulation switching nodes, i.e., the slave nodes, of the second layer through the second group of fully interconnected data interaction interfaces. The data rate is (M×S) / 4. At the same time, it receives the beamformed data of M / 4 beams from the remaining three accumulation switching nodes of the second layer, and completes the accumulation with the beamformed data of M / 4 beams retained by this node to obtain the beamformed data of M / 4 beams of 16N array elements, and outputs it to the fifth accumulation switching node of the second layer, i.e., the master node of the second layer. The data rate of the sent data is (M×S) / 4.

3. The architecture according to claim 1, characterized in that The data interaction form of each node starting from the second layer is as follows: At the pth layer, p=2,3,…the cumulative exchange master nodes participate in the construction of the pth layer and the p+1th layer of two-level fully interconnected networks respectively; at the pth layer, the cumulative exchange node is the master node, and receives 4 packets from the remaining 4 cumulative exchange slave nodes of the current layer through the first group of fully interconnected data interaction interfaces. p After beamforming of N array elements and M / 4 beams, we get 4 p The beamformed data of M beams with N array elements; The current node in the p+1th layer is a slave node. Through the second group of fully interconnected data interaction interfaces, it sends the beamformed data of M / 4 beams to the remaining three p+1-layer accumulation exchange nodes respectively, with a data rate of (M×S) / 4. At the same time, it receives the beamformed data of each M / 4 beam from the remaining three p+1-layer accumulation exchange slave nodes, and completes the accumulation with the beamformed data of the M / 4 beams retained by the node, and obtains 4 p+1 The beamformed data of M / 4 beams of N array elements are output to the p+1 layer accumulation exchange master node, and the data rate is (M×S) / 4.

4. The architecture according to claim 1, characterized in that The data link layer is used to receive parallel data from the transport layer, frame the data according to the custom data link layer frame protocol, manage the data transmission link through the frame protocol, and ensure the stability and accuracy of data transmission; the data link layer frame protocol sets the frame header and frame trailer in the data frame to complete the frame delimitation, and the receiving end can identify the start and end of the frame according to the frame header and frame trailer; The frame header and frame tail adopt the data format of K code plus D code; Set the MAC address in the data frame; Set a timestamp in the data frame to mark the logical time when the data in the data frame is generated, which is used for data alignment of beamforming; A check bit is set in the data frame to check whether errors occur in data transmission and to implement error control of data transmission.

5. The architecture according to claim 1, characterized in that The physical layer is used to establish physical connections between nodes to transmit bit stream data. It is responsible for serial-to-parallel conversion of data, receiving and sending 8B / 10B encoded data at line rate, including serial / deserializer, driver, receiver and clock data recovery CDR module. Each module uses customized units. The serializer / deserializer serializes the 8B / 10B encoded parallel data to be sent or parallelizes the received serial data; the driver is used at the transmitting end and supports pre-emphasis and post-emphasis operations; the receiver is used at the receiving end and supports receive equalization operations, and adjusts the corresponding parameters based on the link eye diagram to determine the current state of the link.

6. The architecture according to claim 1, characterized in that: The layered data transmission specification adopts a short frame continuous transmission mode. Data frames at the data link layer are sent continuously in the form of short frames. When there is user data, the user data is segmented, framed, and transmitted according to the established frame protocol. When there is no user data, the user data transmission is replaced by data 0.

7. The architecture according to claim 1, characterized in that The architecture uses a data synchronization method of timestamp synchronization and pulse synchronization to keep the data of all nodes in each layer aligned: The processing clocks of all nodes in the distributed processing architecture are generated by an external clock source through multi-level power division, and the working clocks of all nodes are kept synchronized; The pulse synchronization technology method is as follows: Step 1: Establish a system synchronization network, select the cumulative exchange master node of a certain unit at the top level as the master control node, the master control node generates a synchronization pulse and outputs it to all the remaining nodes, calculates the round-trip time of the synchronization pulse between the master control node and the remaining nodes through a counter, obtains the time delay from the master control node to the remaining nodes, and makes corresponding delay compensation to ensure that the synchronization pulse reaches all nodes at the same time; Step 2: Establish a system synchronization network, select the cumulative exchange master node of a unit at the top level as the master control node, the master control node generates synchronization pulses and outputs them to all remaining nodes, and through path loopback and IDELAY delay, the synchronization pulse signal reaches all nodes at the same time; Step 3: After the data sampling synchronization is completed, the master control node is triggered by the local module to generate the first-level synchronization pulse signal, confirm that all processing nodes have entered the synchronization state, clear the corresponding cache, and wait for the synchronous sampling data to be loaded; Step 4: The master control node generates a second-level synchronization pulse signal to complete the synchronous loading of all node sampling data into the cache to achieve data synchronization; The timestamp synchronization packages and transmits the data obtained by synchronous sampling of all nodes in the same frame format. After synchronous reception of the first-layer baseband data, the data is segmented according to the data frame length. Each segment of data of all nodes in the corresponding layer is timestamped according to the logical time. After that, data transmission and data processing at all levels determine the consistency of the data based on the timestamp. The data inconsistency caused by inconsistent delays in different transmission channels between nodes will be solved by aligning the multi-frame data FIFO cache.

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