Digital beam forming single chip function test method

Abstract

The invention discloses a digital beam forming single chip function testing method, and particularly relates to the field of chip testing. A test system is adopted for testing, the test system comprises a signal generation board and a beam detection board, and the method comprises the following steps: simulating input data of a chip in various critical actual use scenes through the signal generation board, generating data of various rates and various types, and issuing the data to a chip to be tested; determining the processing delay of each channel of the to-be-tested chip by combining the maximum transmission rate and the correctness of a transmission protocol which can be adapted to the chip by the beam detection board, and traversing the delay inequality of each channel of the input signal within a certain range to verify the accuracy and reliability of the function of the to-be-tested chip; the combined overall test of a plurality of key performances of the digital beam forming single chip can be realized; the method is suitable for testing digital beam forming chips with different input channel numbers and different input data rates in wide and narrow bands.

Description

Technical Field

[0001] The present application relates to the field of chip testing, and in particular to a digital beamforming single-chip functional testing method. Background Art

[0002] With the development of integrated circuit technology, the emergence of chips has greatly simplified development. As the core of modern science and technology, they are widely used in a wide range of fields, including aerospace, communications, the internet, and the automotive industry. To address bottlenecks in digital beamforming technology used in phased array radars and electronic countermeasures, such as large equipment volumes, high power consumption, poor versatility, and reliance on imported core components, a general-purpose digital beamforming chip based on broadband digital beamforming technology has been developed. It has a wide range of applications, meets the requirements of a programmable and scalable architecture, and features a variable number of input and output channels. The performance, reliability, and safety of these chips determine the performance of phased array radars and other electronic equipment. Existing testing methods can only measure a single performance characteristic. Summary of the Invention

[0003] The main purpose of this application is to provide a digital beamforming single-chip functional testing method, which aims to solve the problem that existing testing methods can only measure a single performance of the chip.

[0004] To achieve the above-mentioned purpose, the present application provides a method for testing the function of a digital beamforming single chip, which is tested using a test system. The test system includes a signal generating board and a beam detection board. The method includes: generating a first test code through the signal generating board, sending the first test code to the chip to be tested, and determining the accuracy of the transmission protocol of the receiving channel of the chip to be tested; generating a second test code through the chip to be tested, sending the second test code to the beam detection board, and determining the accuracy of the transmission protocol of the sending channel of the chip to be tested; after the accuracy of the transmission protocol of the receiving channel and the sending channel of the chip to be tested both meet the first preset condition, The board generates first test data, sends the first test data to the beam detection board through the chip to be tested, and obtains the transmission delay of the first test data from the signal generating board to the beam detection board; after the transmission delay of the chip to be tested reaches a second preset condition, sets the actual delay difference of each receiving channel of the chip to be tested; generates second test data through the signal generating board, sends the second test data to the chip to be tested, obtains the receiving data of the chip to be tested, and determines the theoretical delay difference of the corresponding receiving channel of the chip to be tested according to the receiving data; determines the difference between the actual delay difference and the theoretical delay difference, and determines the test result of the time accuracy of the chip to be tested according to the difference.

[0005] Optionally, a first test code is sent to the chip to be tested to determine the accuracy of the transmission protocol of the receiving channel of the chip to be tested, including: sending the first test code to the chip to be tested at a first preset rate to determine the number of bit errors of the corresponding received test code of the receiving channel of the chip to be tested; based on the number of bit errors, determining the adaptability of the receiving channel of the chip to be tested to the first preset rate, and the accuracy of the transmission protocol of the receiving channel.

[0006] Optionally, the number of bit errors of the first test code is 0; the method for determining the adaptability of the receiving channel of the chip to be tested to the first preset rate includes: sending the first test code to the chip to be tested at the first preset rate, obtaining the number of bit errors of the corresponding receiving test code output by the chip to be tested, and when the number of bit errors output by the chip to be tested is equal to 0, determining that the chip to be tested is adapted to the first preset rate of the receiving channel; when the number of bit errors output by the chip to be tested is greater than 0, determining that the chip to be tested is not adapted to the first preset rate of the receiving channel.

[0007] Optionally, a method for determining the accuracy of the transmission protocol of the receiving channel of the chip to be tested includes: injecting bit errors into a first test code, sending the first test code with injected bit errors to the chip to be tested at a first preset rate, obtaining the number of bit errors of the corresponding received test code output by the chip to be tested, comparing the number of bit errors of the corresponding received data with the number of injected bit errors, and when it is determined that the two bit error numbers are equal, the transmission protocol of the receiving channel of the chip to be tested is accurate.

[0008] Optionally, a second test code is sent to the beam detection board to determine the accuracy of the transmission protocol of the transmission channel of the chip to be tested, including: sending the second test code to the beam detection board to test the data rate of the beam detection board, and determining the adaptability of the transmission channel of the chip to be tested to the second preset rate based on the data rate; and determining the number of bit errors of the corresponding received test code of the beam detection board, and determining the test result of the transmission protocol of the transmission channel of the chip to be tested based on the number of bit errors.

[0009] Optionally, first test data is generated by a signal generating board, the first test data is sent to the beam detection board through the chip to be tested, and the transmission delay of the first test data from the signal generating board to the beam detection board is obtained, including: generating the first test data by the signal generating board, sending the first test data to the beam detection board through the logic circuit of the chip to be tested, and obtaining the time difference of the first test data being transmitted from the signal generating board to the beam detection board as the first time difference; and sending the first test data to the beam detection board through the outer loop path of the chip to be tested, and obtaining the time difference of the first test data being transmitted from the signal generating board to the beam detection board as the second time difference; and determining the transmission delay of the chip to be tested based on the first time difference and the second time difference.

[0010] Optionally, the test system also includes an interface board, and the method for determining the first time difference includes: performing message header detection on the first test data through the signal generating board and the beam detection board respectively, and generating two pulse signals respectively when the message header appears, and obtaining the time difference of the two pulse signals through the interface board test.

[0011] Optionally, the first time difference and the second time difference are determined in the same way.

[0012] Optionally, the difference between the actual delay difference and the theoretical delay difference is determined, and the test result of the time accuracy of the chip to be tested is determined based on the difference, including: determining the difference between the actual delay difference and the theoretical delay difference, and when the difference reaches a preset difference, correcting the receiving channel of the chip to be tested, and obtaining the delay difference of the corrected receiving channel, and determining the test result of the time accuracy of the chip to be tested based on the delay difference of the corrected receiving channel.

[0013] Optionally, the test system also includes a main control board, which is respectively connected to the chip to be tested, the signal generating board, and the beam detection board. The main control board is used to send control instructions to the chip to be tested, the signal generating board, and the beam detection board, and to process the data output by the chip to be tested, the signal generating board, and the beam detection board.

[0014] Compared with the prior art, the present invention has the following advantages:

[0015] The present invention discloses a method for testing the function of a digital beamforming single chip. A signal generating board can be quickly configured through software to generate data of various rates and types and send them to the chip under test, simulating the input data of the chip under various critical actual usage scenarios. In combination with a beam detection board, the maximum transmission rate that the chip can adapt to and the correctness of the transmission protocol are tested, the processing delay of each channel of the chip under test is determined, and the time delay difference of each channel of the input signal is traversed within a certain range to verify the accuracy and reliability of the function of the chip under test. The method can realize a joint overall test of multiple key performances of the digital beamforming single chip. Compared with the existing individual tests in multiple test scenarios using multiple test equipment, which have large errors and cannot unify input and output, the test results are combined and the standards are unified, which improves the test efficiency and can ensure the accuracy and precision of the test. The method is suitable for testing digital beamforming chips with different numbers of input channels and different input data rates for wide and narrow bands. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a structural diagram of a test system in a digital beamforming single-chip functional test method of the present application;

[0017] Figure 2 This is a flow chart of testing the maximum data rate and transmission protocol in a digital beamforming single-chip functional testing method of the present application;

[0018] Figure 3 This is a flow chart of testing transmission delay in a digital beamforming single-chip functional testing method of the present application;

[0019] Figure 4 This is a flow chart of testing the delay difference in a digital beamforming single-chip functional testing method of the present application;

[0020] Figure 5 This is an experimental verification diagram of the delay difference test in a digital beamforming single-chip functional test method applied in this application.

[0021] The realization of the objectives, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0022] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0023] The first embodiment of the present invention provides a digital beamforming single chip functional testing method, such as Figure 1 As shown, a test system is used for testing. The test system includes a signal generator board, a beam detection board, and a main control board. The signal generator board is used to generate and send digital signals to the chip to be tested. The beam detection board is used to receive the digital signals output by the chip to be tested. The main control board is used to control the signal generator board, the chip to be tested, and the beam detection board, and process the generated data to obtain the corresponding test results. Specifically, the following steps are included:

[0024] Step S1: Generate a first test code using a signal generator board, send the first test code to a chip under test at a first preset rate, and determine the number of bit errors in corresponding received data of a receiving channel of the chip under test; based on the number of bit errors, determine the adaptability of the receiving channel of the chip under test to the first preset rate and the test result of the transmission protocol of the receiving channel;

[0025] In this embodiment, the signal generating board is loaded with the IBERT program of FPGA, and the first test code can be a PRBS7 code. It is worth noting that the chip to be tested is a digital beamforming single chip, which has the functions of code detection and code generation. The first preset rate is the maximum transmission rate of the receiving channel of the chip to be tested, which can be selected according to the specific chip to be tested. Send the correct test code to the chip to be tested, and determine whether the current first preset rate is the maximum transmission rate of the receiving channel that the chip to be tested can adapt to based on the number of bit errors of the corresponding received data in the receiving channel, so as to adjust the transmission rate later. At the same time, send a test code containing bit errors to the chip to be tested, and based on the comparison of the number of bit errors, the correctness of the transmission protocol of the receiving channel can be determined. The specific steps are as follows, see Figure 2 .

[0026] Step S11, determining whether the first preset rate is the maximum transmission rate of the receiving channel that the chip to be tested can adapt to, specifically includes: generating a first test code through a signal generating board, and the number of bit errors of the first test code is 0; sending the first test code to the chip to be tested at F1 (Gbps), obtaining a receiving test code corresponding to the first test code in the receiving channel of the chip to be tested, and reading the receiving test code through the code type detection function of the chip to be tested and counting the number of bit errors E1 and displaying it; when the number of bit errors E1 output by the chip to be tested is equal to 0, determining that the chip to be tested is adapted to the first preset rate of the receiving channel; when the number of bit errors E1 output by the chip to be tested is greater than 0, determining that the chip to be tested is not adapted to the first preset rate of the receiving channel.

[0027] Step S12, determine the correctness of the transmission protocol of the receiving channel; specifically, inject N1 bit errors into the first test code generated by the signal generating board through software, send the first test code with injected errors to the chip to be tested at a first preset rate, obtain the bit error number E2 of the corresponding receiving test code output by the chip to be tested, compare the bit error number E2 of the test code output by the chip to be tested with the bit error number N1 of the first test code, if E2 is equal to N1, then the test result of the transmission protocol of the receiving channel of the chip to be tested is correct; if E2 is not equal to N1, it is determined that the test result of the transmission protocol of the receiving channel is incorrect.

[0028] Step S2: Generate a second test code using the chip under test, and send the second test code to the beam detection board at a second preset rate to test the data rate of the beam detection board. Based on the data rate, determine the adaptability of the transmission channel of the chip under test to the second preset rate. Also, determine the number of bit errors in the corresponding received data of the beam detection board. Based on the number of bit errors, determine the test result of the transmission protocol of the transmission channel of the chip under test.

[0029] In this embodiment, the beam detection board loads the IBERT program of the FPGA, resets the IBERT error counter at the receiving end, and the second test code can be a PRBS7 code. It is worth noting that the second preset rate is determined in the same manner as the first preset rate.

[0030] Specifically, in step S21, a second test code is generated by the code generation function of the chip to be tested, and the second test code is sent as a normal PRBS7 code test code at a rate of F2 (Gbps) to the beam detection board through a high-speed serial transceiver, and the data rate F3 and the number of bit errors E3 at the current FPGA receiving end are recorded at the beam detection board end. If F2=F3 and E3=0, it is determined that the chip to be tested adapts to the rate F2 of the transmitting channel; if F2 is not equal to F3, or E3 is not equal to 0, it is determined that the chip to be tested is not adapted to the rate F2 of the receiving channel.

[0031] Step S22: At the chip transmitting end, E4 bit errors are injected into the second test code, and the number of bit errors E5 of the receiving channel of the beam detection board is recorded. If E4 is equal to E5, it is determined that the transmission protocol of the transmitting channel of the chip to be tested is correct, otherwise it is incorrect.

[0032] Step S3: When it is determined that the test results of the receiving channel and the sending channel meet the first preset condition, the signal generating board generates first test data, sends the first test data to the beam detection board through the chip to be tested, and obtains the transmission delay of the first test data from the signal generating board to the beam detection board. Figure 3 ;

[0033] In step S31, the test system further includes an interface board, which generates first test data via the signal generation board, sends the first test data to the beam detection board via the chip under test, and obtains a time difference between the transmission of the first test data from the signal generation board to the beam detection board as a first time difference, i.e., a time difference in a normal working mode.

[0034] Specifically, the first test data is generated by the signal generating board. After the first test data is synthesized and calculated by the chip to be tested, it is sent to the beam detection board. The signal generating board and the beam detection board respectively perform message header detection on the first test data, and two pulse signals are generated when the message header appears. The two pulse signals are transmitted to the oscilloscope for display through the interface board, and the first time difference T1 is measured.

[0035] Step S32: The first test data is sent to the beam detection board through the outer loop path of the chip to be tested, and the time difference between the first test data transmitted from the signal generating board to the beam detection board is obtained as the second time difference, i.e., the time difference of the loopback working mode;

[0036] It is understandable that in the loopback working mode, data enters the transceiver pin (external loopback path) of the chip under test and is directly forwarded from the pin without passing through the logic module, that is, the chip under test does not perform any operation on the data.

[0037] Specifically, the first test data is transmitted directly to the beam detection board via the external loopback function of the transceiver pins of the chip under test, bypassing the logic of the chip under test. The signal generation board and the beam detection board each perform header detection on the first test data and generate two pulse signals when the header appears. The two pulse signals are transmitted to the oscilloscope for display via the interface board, and the second time difference T2 is measured, and the PMA layer delay of the chip under test is obtained as T3.

[0038] Step S33: Determine the transmission delay of the chip under test based on the first and second time differences; the delay of the chip under test is T4 = T1 - T2 + T3. Measure several times. If the maximum value of T4 is less than 500ns, the transmission delay of the test chip is determined to meet the standard.

[0039] Step S4 : when it is determined that the transmission delay of the chip under test reaches the second preset condition, determining the relative delay difference of each receiving channel of the chip under test.

[0040] The signal delay difference of each channel of the chip is mainly caused by the sampling time error of each sampling channel and the time difference of the transmission process after data quantization. Among them, the sampling time error is generally less than one sampling period and is a decimal; while the error of data transmission is an integer sampling period and is an integer. By synchronizing and correcting the amplitude and phase of each channel of the chip, the integer sampling period can be completely corrected, but the fractional sampling period will still have a residual delay difference after rounding, which theoretically cannot exceed 1 / 2 sampling period. The specific test includes the following steps, such as Figure 4 As shown:

[0041] Step S41, setting the actual delay difference of each receiving channel of the chip to be tested; wherein the delay difference of each receiving channel is the delay difference of each receiving channel relative to channel 0;

[0042] In step S42, the signal generator board generates second test data for each channel. Specifically, the signal generator board outputs test data at different frequencies as the second test data for the corresponding channel. The second test data is sent to the chip under test, and the received data of each receiving channel of the chip under test is obtained. Combined with the frequency change, the phase difference Δβ of the signal of each receiving channel of the chip under test is calculated, thereby determining the delay difference Δt of the corresponding receiving channel of the chip under test as the theoretical delay difference. The formula is as follows:

[0043] Δt=Δβ / 2πΔf.

[0044] Step S43: Compare the theoretical delay difference with the actual delay difference. If the difference between the two reaches a preset difference, they are consistent and the next step is performed. Otherwise, the timing accuracy test result of the chip to be tested is unqualified.

[0045] Step S44, calibrate the corresponding receiving channel of the chip to be tested, wherein the calibration process includes channel synchronization and amplitude and phase calibration, and test the delay difference of the receiving channel after calibration to obtain the test result of the time accuracy of the chip to be tested. Further, if the delay difference of the receiving channel after calibration is less than 1 / (2f s ), that is, 1 / 2 sampling period, then the time accuracy index of the test chip is qualified.

[0046] The specific synchronization method is: make the signal generator board generate test data of different frequencies, send it to the chip to be tested, and obtain the phase difference θ between each channel. n ', will t n Corrected to consistency.

[0047] The amplitude and phase correction method is: read the a of each channel at each frequency n and θ n , and then normalize the amplitude to get a n ', [a n '*cos(θ n ),-a n '*sin(θ n )] is sent to the registers in the chip to be tested to calibrate the a of each channel n and θ n To ensure consistency, the sampling time error of each sampling channel and the time difference of the transmission process after data quantization are corrected at the same time.

[0048] To further ensure test accuracy, this embodiment repeats steps S41-S44 after testing the relative delay difference of the corrected receiving channel until the standard range is exhausted. If the delay difference of each test is within the standard range, it proves that the timing accuracy of the chip under test is accurate. The delay difference of each receiving channel of the chip under test is set in step S41 in a fixed increment of Δτ. The standard range of the delay difference is the theoretical maximum value, i.e., |Δt| max <π / (2π·Δf), Δf is the minimum frequency difference selected for phase difference measurement.

[0049] The method of testing the time delay difference in step S4 is verified below with a specific example.

[0050] The signal generator board generates four-channel digital signals. The signal of each channel can be expressed as:

[0051] x n (t) = an exp{j[2πf(t-τ n -t n )+θ n ]},

[0052] Where, t n is the system delay difference of each channel, τ n is the incident delay difference of each channel, a n is the amplitude of each channel signal, θ n is the initial phase difference of each channel. The sampling rate is f s , the delay (τ n +t n ) is divided into integer sampling points and decimal sampling points, that is, τ n +t n =I n T s +F n T s , where T s =1 / f s is the sampling period, I n = | (τ n +t n )f s is an integer sampling point, is the fractional sampling point, Indicates rounding down.

[0053] Assuming the sampling rate f s =10.24GS / s, set the delay of each receiving channel to τ0=0ps, τ1=50ps, τ2=100ps, τ3=150ps, the system delay is t0=0ps, t1=3105ps, t2=3275ps, t3=3285ps, and set the frequency change within 10us to Δf=50MHz, then the calculated integer sampling points of the delay of each channel are I0=0, I1=32, I2=34, I3 =35, the fractional delay is F0T0=0, F1T1=30ps, F2T2=54.6875ps, F3T3=17.03125ps, the phase difference caused by the delay (theoretical) is 2πΔf(τ1+t1)≈0.99rad, 2πΔf(τ2+t2)≈1.06rad, 2πΔf(τ3+t3)≈1.08rad, where the phase difference caused by the fractional delay is 2πΔfF1T s ≈0.009rad, 2πΔfF2T s ≈0.017rad, 2πΔfF3T s ≈0.005rad, and the theoretical phase difference obtained in this embodiment is compared with the measured phase difference, and the two are basically consistent, such as Figure 5As shown in ab, it is proved that the method of testing the phase difference caused by the delay in this embodiment has high accuracy. The delay difference is determined by using the phase difference, which ensures the accuracy of the delay difference test.

[0054] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A digital beamforming single-chip functional testing method, characterized in that: A test system is used for testing, the test system includes a signal generating board and a beam detection board, and the method includes: Generate a first test code through the signal generating board, send the first test code to the chip to be tested, and determine the accuracy of the transmission protocol of the receiving channel of the chip to be tested; Generate a second test code through the chip to be tested, send the second test code to the beam detection board, and determine the accuracy of the transmission protocol of the transmission channel of the chip to be tested; After the accuracy of the transmission protocol of the receiving channel and the sending channel of the chip to be tested both meet the first preset condition, the signal generating board generates first test data, the first test data is sent to the beam detection board through the chip to be tested, and the transmission delay of the first test data from the signal generating board to the beam detection board is obtained; After the transmission delay of the chip to be tested reaches a second preset condition, setting an actual delay difference of each receiving channel of the chip to be tested; Generate second test data through the signal generating board, send the second test data to the chip to be tested, obtain receiving data of the chip to be tested, and determine the theoretical delay difference of the corresponding receiving channel of the chip to be tested according to the receiving data; The difference between the actual delay difference and the theoretical delay difference is determined, and the test result of the time accuracy of the chip to be tested is determined according to the difference.

2. The digital beamforming single-chip functional testing method according to claim 1, characterized in that: Sending the first test code to the chip to be tested to determine the accuracy of the transmission protocol of the receiving channel of the chip to be tested includes: Sending the first test code to the chip to be tested at a first preset rate, and determining the number of bit errors of the corresponding received test code of the receiving channel of the chip to be tested; According to the number of bit errors, the adaptability of the receiving channel of the chip to be tested to a first preset rate and the accuracy of the transmission protocol of the receiving channel are determined.

3. The digital beamforming single-chip functional testing method according to claim 2, characterized in that: The bit error number of the first test code is 0; The method for determining the adaptability of the receiving channel of the chip to be tested to a first preset rate includes: Sending the first test code to the chip under test at a first preset rate, obtaining the number of bit errors of the corresponding received test code output by the chip under test, and determining that the chip under test is adapted to the first preset rate of the receiving channel when the number of bit errors output by the chip under test is equal to 0; When the number of bit errors output by the chip to be tested is greater than 0, it is determined that the chip to be tested is not adapted to the first preset rate of the receiving channel.

4. The digital beamforming single-chip functional testing method according to claim 3, characterized in that: The method for determining the accuracy of the transmission protocol of the receiving channel of the chip to be tested comprises: Inject bit errors into the first test code, send the first test code with injected bit errors to the chip to be tested at a first preset rate, obtain the bit error number of the corresponding received test code output by the chip to be tested, compare the bit error number of the corresponding received data with the injected bit error number, and when it is determined that the two bit error numbers are equal, the transmission protocol of the receiving channel of the chip to be tested is accurate.

5. The digital beamforming single chip functional testing method according to claim 1, characterized in that: The sending of the second test code to the beam detection board to determine the accuracy of the transmission protocol of the transmission channel of the chip to be tested includes: Sending the second test code to the beam detection board to test the data rate of the beam detection board, and determining the adaptability of the transmission channel of the chip to be tested to the second preset rate according to the data rate; The number of bit errors of the corresponding received test code of the beam detection board is determined, and the test result of the transmission protocol of the sending channel of the chip to be tested is determined according to the number of bit errors.

6. The digital beamforming single chip functional testing method according to claim 1, characterized in that: The step of generating first test data by the signal generating board, sending the first test data to the beam detection board through the chip to be tested, and obtaining a transmission delay of the first test data from the signal generating board to the beam detection board includes: Generate first test data through the signal generating board, send the first test data to the beam detection board through the logic circuit of the chip to be tested, and obtain the time difference of the first test data being transmitted from the signal generating board to the beam detection board as the first time difference; and sending the first test data to the beam detection board through the outer loop path of the chip to be tested, and obtaining the time difference of the first test data being transmitted from the signal generating board to the beam detection board as the second time difference; The transmission delay of the chip to be tested is determined according to the first time difference and the second time difference.

7. The digital beamforming single-chip functional testing method according to claim 1, characterized in that: The test system further includes an interface board, and the method for determining the first time difference includes: The signal generating board and the beam detecting board respectively perform message header detection on the first test data, and respectively generate two pulse signals when the message header appears, and the time difference between the two pulse signals is obtained through the interface board test.

8. The digital beamforming single-chip functional testing method according to claim 5, characterized in that: The first time difference and the second time difference are determined in the same way.

9. The digital beamforming single chip functional testing method according to claim 1, characterized in that: The step of determining the difference between the actual delay difference and the theoretical delay difference, and determining the test result of the time accuracy of the chip to be tested according to the difference, includes: Determine the difference between the actual delay difference and the theoretical delay difference. When the difference reaches a preset difference, calibrate the receiving channel of the chip to be tested, and obtain the delay difference of the corrected receiving channel. According to the delay difference of the corrected receiving channel, determine the test result of the time accuracy of the chip to be tested.

10. The digital beamforming single chip functional testing method according to claim 1, characterized in that: The test system also includes a main control board, which is respectively connected to the chip to be tested, the signal generating board, and the beam detection board. The main control board is used to send control instructions to the chip to be tested, the signal generating board, and the beam detection board, and to process data output by the chip to be tested, the signal generating board, and the beam detection board.

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