Message DMA method and device based on pointer and electronic equipment

Abstract

The invention discloses a message DMA method and device based on a pointer and electronic equipment, and belongs to the technical field of communication. The method comprises the following steps: setting a first count value and a tail count value for an annular queue formed by a plurality of descriptors; the first count value is used for indicating the use condition of the descriptor; the tail count value is used for indicating the newly-added condition of the descriptor; under the condition that the number of descriptors in a descriptor cache of the DMA controller is smaller than a threshold value, the available condition of the descriptors in the annular queue is determined according to the first count value and the tail count value; and under the condition of determining that the annular queue comprises the unused descriptors, reading the descriptors from the annular queue and storing the descriptors into a descriptor cache of the DMA controller. According to the method, read-write requests do not need to be frequently initiated to the host, the frequency of read-write operation of the DMA on the host is reduced, and the DMA transmission efficiency is improved.

Description

Technical Field

[0001] The present application belongs to the field of communications, and in particular, relates to a pointer-based message DMA method, device and electronic equipment. Background Art

[0002] In modern communication networks, the direct memory access (DMA) technology of Ethernet network cards usually uses a circular queue to manage data transmission. Its characteristic is that a set of descriptors is used to build a receiving and sending circular queue. These descriptors reside in the system's memory, and each descriptor points to a continuous memory space, which is used to store complete or partial network messages.

[0003] In the related art, when a message is sent or received, the descriptor needs to be written back separately to pass its status information. When sending a message, the DMA controller needs to initiate a read operation to the host to obtain the descriptor, and after each message transmission is completed, the DMA controller needs to initiate a write operation when writing back the descriptor. Although the amount of data transferred each time is small, due to their frequent occurrence, they will have a significant impact on the bus transmission efficiency connecting the DMA and the host. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a pointer-based message DMA method, device and electronic device to reduce the frequency of DMA read and write operations on the host and improve DMA transmission efficiency.

[0005] In a first aspect, the present application provides a pointer-based message DMA method, comprising:

[0006] A first count value and a tail count value are set for a circular queue composed of a plurality of descriptors; the first count value is used to indicate the usage of the descriptor; and the tail count value is used to indicate the addition of a descriptor;

[0007] When the number of descriptors in the descriptor cache of the DMA controller is less than a threshold, determining the availability of descriptors in the circular queue according to the first count value and the last count value;

[0008] When it is determined that the circular queue includes unused descriptors, the descriptors are read from the circular queue and stored in a descriptor buffer of the DMA controller.

[0009] According to the pointer-based message DMA method of the present application, a first count value and a tail count value are set for a circular queue composed of multiple descriptors; the first count value is used to indicate the usage of the descriptor; the tail count value is used to indicate the addition of a descriptor; when the number of descriptors in the descriptor cache of a DMA controller is less than a threshold, the availability of the descriptors in the circular queue is determined based on the first count value and the tail count value; when it is determined that the circular queue includes unused descriptors, the descriptors are read from the circular queue and stored in the descriptor cache of the DMA controller. In the embodiment of the present application, the usage of descriptors is recorded by the first count value, and the addition of descriptors is recorded by the tail count value. The DMA controller can promptly understand whether there are available descriptors in the circular queue based on the first count value and the tail count value. If there are unused descriptors and the number of available descriptors in the descriptor cache of the DMA controller is lower than a threshold (configurable), the DMA controller will read these descriptors in batches from the circular queue at one time and store them in its own cache. When sending and receiving messages, if the descriptors exist in the cache of the DMA controller, they can be used directly without frequently initiating read and write requests to the host, thereby reducing the frequency of DMA read and write operations on the host and improving DMA transmission efficiency.

[0010] According to an embodiment of the present application, determining the availability of descriptors in the ring queue according to the first count value and the last count value includes:

[0011] Determine whether the first count value and the last count value are equal;

[0012] When the head count value and the tail count value are not equal, it is determined that the ring queue includes unused descriptors.

[0013] In this embodiment, by comparing the first count value and the last count value, the availability of descriptors in the circular queue can be accurately determined. In this way, the availability of descriptors in the circular queue can be quickly determined without initiating a request to the host, thereby reducing the frequency of DMA read and write operations on the host and improving DMA transmission efficiency.

[0014] According to one embodiment of the present application, when it is determined that the circular queue includes unused descriptors, reading descriptors from the circular queue and storing them in a descriptor cache of the DMA controller includes:

[0015] Determine the number of requested descriptors according to at least one of the size of the available space of the descriptor cache, the first count value, the tail count value, and the size of the descriptor buffer storing the circular queue;

[0016] Descriptors are read from the descriptor buffer of the circular queue according to the number of requested descriptors and stored in the descriptor cache of the DMA controller.

[0017] In this embodiment, by determining the number of descriptors to be requested based on at least one of the four parameters of the available space of the DMA controller descriptor cache, the first count value, the tail count value, and the size of the ring queue descriptor buffer, the DMA controller can be prevented from causing cache overflow due to requesting too many descriptors, and frequent read operations due to too few requests are reduced, thereby optimizing the DMA data transmission process, reducing the demand for host resources, and improving the system's data processing capabilities and overall efficiency.

[0018] According to one embodiment of the present application, determining the number of requested descriptors according to at least one of the size of the available space of the descriptor cache, the first count value, the tail count value, and the size of the descriptor buffer storing the circular queue includes:

[0019] Calculating a first difference between the first count value and the last count value, and calculating a second difference between the first count value and the size of the descriptor buffer;

[0020] The minimum value among the size of the descriptor cache available space, the first difference and the second difference is determined as the number of requested descriptors.

[0021] In this embodiment, by calculating the first difference between the first count value and the last count value, the number of descriptors currently unused in the circular queue can be understood, and by calculating the second difference between the first count value and the descriptor buffer size, the number of descriptors remaining in the circular queue can be determined, and the minimum value of the size of the descriptor cache available space, the first difference, and the second difference is determined as the requested number of descriptors, so that the DMA controller will not request descriptors exceeding the cache capacity, and will not cause cache overflow or resource waste due to excessive requests, thereby reducing unnecessary memory access, reducing dependence on host memory, and improving data processing speed.

[0022] According to one embodiment of the present application, the circular queue includes a receiving queue and a sending queue, and the receiving queue and the sending queue are respectively allocated independent descriptor buffers, in which descriptors are stored in sequence according to adjacent addresses; the first count value and the tail count value of the receiving queue and the sending queue are stored in the count value buffer of the memory.

[0023] In this embodiment, independent descriptor buffers are set for the receiving queue and the transmitting queue respectively, and the head and tail count values ​​are stored independently in the memory, so that the receiving and transmitting operations can be performed in parallel without interfering with each other. The continuous storage of descriptors optimizes the memory access mode of the DMA controller, making data transmission more efficient.

[0024] According to one embodiment of the present application, reading the descriptor from the ring queue and storing it in the descriptor cache of the DMA controller includes:

[0025] Determine the starting position of reading according to the tail count value, the size of the descriptor buffer storing the circular queue, and the physical address where the first descriptor in the descriptor buffer storing the circular queue is stored;

[0026] The descriptor is read from the starting position and stored in the descriptor buffer of the DMA controller.

[0027] In this embodiment, the starting position of reading is determined by the tail count value, the size of the descriptor buffer and the physical address of the first descriptor, so that the DMA controller can accurately locate the descriptor that needs to be read in the circular queue, and directly read the descriptor from the starting position and store it in the cache of the DMA controller. There is no need to initiate additional descriptor read position requests to the host, which reduces the number of accesses to the host memory and further improves the DMA transmission efficiency.

[0028] According to one embodiment of the present application, the method further includes:

[0029] When receiving a message, adding the message receiving information to a preset field in the message header;

[0030] Obtaining a receive descriptor from a descriptor buffer of the DMA controller;

[0031] Writing the message to which the reception information is added into the memory buffer indicated by the reception descriptor;

[0032] When the message in the memory buffer indicated by the receiving descriptor is read, the first count value of the receiving queue is updated.

[0033] In this embodiment, by preprocessing the message when receiving the message, adding the receiving information in the preset field of the received message header, the host can understand the message according to this information, and the DMA controller does not need to upload the received message information by writing back the descriptor, which reduces the number of accesses to the host memory and further improves the DMA transmission efficiency. In addition, when the message in the memory buffer is read, the first count value of the receiving queue is updated, thereby synchronizing the use status of the descriptor in the ring queue, so that the host can recycle the used descriptors according to the first count value, thereby improving the management efficiency of the descriptors.

[0034] According to one embodiment of the present application, the method further includes:

[0035] In the case of sending a message, obtaining a send descriptor from a descriptor buffer of the DMA controller;

[0036] Reading a message from the memory buffer indicated by the send descriptor and sending it;

[0037] When the transmission is successful, the first count value of the transmission queue is updated.

[0038] In this embodiment, when sending a message, a send descriptor is obtained from the descriptor cache of the DMA controller, the message is read from the memory buffer indicated by the send descriptor and sent, and after the sending is successful, the first count value of the send queue is updated to synchronize the usage status of the descriptors in the circular queue. There is no need to upload the usage information of the descriptor by writing back the descriptor, which reduces the number of accesses to the host memory and further improves the DMA transmission efficiency.

[0039] According to one embodiment of the present application, the method further includes:

[0040] When a new descriptor is added to the descriptor buffer storing the circular queue, a tail count value of the circular queue is updated.

[0041] In this embodiment, the tail count value is updated in time after a new descriptor is added to the descriptor buffer of the circular queue, so that the status of the descriptors in the circular queue can be timely understood based on the first count value and the tail count value. The DMA controller does not need to frequently initiate read and write requests to the host, thereby reducing the frequency of DMA read and write operations on the host and improving DMA transmission efficiency.

[0042] In a second aspect, the present application provides a pointer-based message DMA device, characterized in that it includes:

[0043] A setting module, used to set a first count value and a tail count value for a circular queue composed of multiple descriptors; the first count value is used to indicate the usage of the descriptor; the tail count value is used to indicate the addition of a descriptor;

[0044] A determination module, configured to determine the availability of descriptors in the circular queue according to the first count value and the last count value when the number of descriptors in the descriptor cache of the DMA controller is less than a threshold value;

[0045] The reading module is used for reading the descriptors from the circular queue and storing the descriptors in the descriptor cache of the DMA controller when it is determined that the circular queue includes unused descriptors.

[0046] According to the pointer-based message DMA device of the present application, a first count value and a tail count value are set for a circular queue composed of multiple descriptors; the first count value is used to indicate the usage of the descriptors; the tail count value is used to indicate the addition of new descriptors; when the number of descriptors in the descriptor cache of the DMA controller is less than a threshold, the availability of the descriptors in the circular queue is determined according to the first count value and the tail count value; when it is determined that the circular queue includes unused descriptors, the descriptors are read from the circular queue and stored in the descriptor cache of the DMA controller. In the embodiment of the present application, the usage of descriptors is recorded by the first count value, and the addition of descriptors is recorded by the tail count value. The DMA controller can promptly understand whether there are available descriptors in the circular queue based on the first count value and the tail count value. If there are unused descriptors and the number of available descriptors in the descriptor cache of the DMA controller is lower than a threshold (configurable), the DMA controller will read these descriptors in batches from the circular queue at one time and store them in its own cache. When sending and receiving messages, if the descriptors exist in the cache of the DMA controller, they can be used directly without frequently initiating read and write requests to the host, thereby reducing the frequency of DMA read and write operations on the host and improving DMA transmission efficiency.

[0047] In a third aspect, the present application provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the pointer-based message DMA method as described in the first aspect above is implemented.

[0048] In a fourth aspect, the present application provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the pointer-based message DMA method as described in the first aspect above is implemented.

[0049] In a fifth aspect, the present application provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the pointer-based message DMA method as described in the first aspect above.

[0050] In a sixth aspect, the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the pointer-based message DMA method as described in the first aspect above.

[0051] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0052] According to the pointer-based message DMA method of the present application, a first count value and a tail count value are set for a circular queue composed of multiple descriptors; the first count value is used to indicate the usage of the descriptor; the tail count value is used to indicate the addition of a descriptor; when the number of descriptors in the descriptor cache of a DMA controller is less than a threshold, the availability of the descriptors in the circular queue is determined based on the first count value and the tail count value; when it is determined that the circular queue includes unused descriptors, the descriptors are read from the circular queue and stored in the descriptor cache of the DMA controller. In the embodiment of the present application, the usage of descriptors is recorded by the first count value, and the addition of descriptors is recorded by the tail count value. The DMA controller can promptly understand whether there are available descriptors in the circular queue based on the first count value and the tail count value. If there are unused descriptors and the number of available descriptors in the descriptor cache of the DMA controller is lower than a threshold (configurable), the DMA controller will read these descriptors in batches from the circular queue at one time and store them in its own cache. When sending and receiving messages, if the descriptors exist in the cache of the DMA controller, they can be used directly without frequently initiating read and write requests to the host, thereby reducing the frequency of DMA read and write operations on the host and improving DMA transmission efficiency.

[0053] Furthermore, in some embodiments, by comparing the first count value and the last count value, the availability of descriptors in the circular queue can be accurately determined. In this way, the availability of descriptors in the circular queue can be quickly determined without initiating a request to the host, thereby reducing the frequency of DMA read and write operations on the host and improving DMA transmission efficiency.

[0054] Furthermore, in some embodiments, by determining the number of descriptors to be requested based on at least one of the four parameters of the available space in the DMA controller descriptor cache, the first count value, the last count value, and the size of the ring queue descriptor buffer, the DMA controller can avoid cache overflow due to requesting too many descriptors, reduce frequent read operations due to too few requests, optimize the DMA data transmission process, reduce the demand for host resources, and improve the system's data processing capabilities and overall efficiency.

[0055] Furthermore, in some embodiments, by calculating the first difference between the first count value and the last count value, the number of descriptors currently unused in the circular queue can be understood, and by calculating the second difference between the first count value and the descriptor buffer size, the number of descriptors remaining in the circular queue can be determined, and the minimum value of the size of the descriptor cache available space, the first difference, and the second difference is determined as the requested number of descriptors, so that the DMA controller will not request descriptors that exceed the cache capacity, and will not cause cache overflow or resource waste due to excessive requests, thereby reducing unnecessary memory accesses, reducing dependence on host memory, and improving data processing speed.

[0056] Furthermore, in some embodiments, by setting independent descriptor buffers for the receive queue and the transmit queue respectively, and independently storing the head and tail count values ​​in the memory, the receive and transmit operations can be performed in parallel without interfering with each other. The continuous storage of descriptors optimizes the memory access mode of the DMA controller, making data transmission more efficient.

[0057] Furthermore, in some embodiments, the starting position of reading is determined by the tail count value, the size of the descriptor buffer and the physical address of the first descriptor, so that the DMA controller can accurately locate the descriptor that needs to be read in the circular queue, and directly read the descriptor from the starting position and store it in the cache of the DMA controller. There is no need to initiate additional descriptor read position requests to the host, thereby reducing the number of accesses to the host memory and further improving the DMA transmission efficiency.

[0058] Furthermore, in some embodiments, by preprocessing the message when receiving the message, adding the receiving information in the preset field of the received message header, the host can understand the message according to this information, and the DMA controller does not need to upload the received message information by writing back the descriptor, which reduces the number of accesses to the host memory and further improves the DMA transmission efficiency. In addition, when the message in the memory buffer is read, the first count value of the receiving queue is updated, thereby synchronizing the use status of the descriptor in the circular queue, so that the host can recycle the used descriptors according to the first count value, thereby improving the management efficiency of the descriptors.

[0059] Furthermore, in some embodiments, when sending a message, a send descriptor is obtained from the descriptor cache of the DMA controller, the message is read from the memory buffer indicated by the send descriptor and sent, and after the sending is successful, the first count value of the send queue is updated, thereby synchronizing the usage status of the descriptors in the circular queue. There is no need to upload the usage information of the descriptor by writing back the descriptor, which reduces the number of accesses to the host memory and further improves the DMA transmission efficiency.

[0060] Furthermore, in some embodiments, by timely updating the tail count value after a new descriptor is added to the descriptor buffer of the circular queue, the status of the descriptors in the circular queue can be timely understood based on the first count value and the tail count value. The DMA controller does not need to frequently initiate read and write requests to the host, thereby reducing the frequency of DMA read and write operations on the host and improving DMA transmission efficiency.

[0061] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0063] Figure 1 It is a flowchart of a pointer-based message DMA method provided in an embodiment of the present application;

[0064] Figure 2 It is a schematic diagram of the structure of the ring queue provided in the embodiment of the present application;

[0065] Figure 3 It is a code logic diagram of the management of descriptors provided in the embodiment of the present application;

[0066] Figure 4 It is a structural schematic diagram of a pointer-based message DMA device provided in an embodiment of the present application;

[0067] Figure 5 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0068] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0069] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0070] The pointer-based message DMA method, device and electronic device provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings through specific embodiments and their application scenarios.

[0071] The pointer-based message DMA method may be applied to a terminal, and may be specifically executed by hardware or software in the terminal.

[0072] The terminal includes, but is not limited to, a portable communication device such as a mobile phone or tablet computer with a touch-sensitive surface (e.g., a touch screen display and / or a touch pad). It should also be understood that in some embodiments, the terminal may not be a portable communication device, but a desktop computer with a touch-sensitive surface (e.g., a touch screen display and / or a touch pad).

[0073] In the following various embodiments, a terminal including a display and a touch-sensitive surface is described. However, it should be understood that the terminal may include one or more other physical user interface devices such as a physical keyboard, a mouse and a joystick.

[0074] The pointer-based message DMA method provided in the embodiment of the present application, the execution subject of the pointer-based message DMA method can be an electronic device or a functional module or functional entity in the electronic device that can implement the pointer-based message DMA method. The electronic devices mentioned in the embodiment of the present application include but are not limited to mobile phones, tablet computers, computers, cameras and wearable devices, etc. The pointer-based message DMA method provided in the embodiment of the present application is explained below using the electronic device as an execution subject as an example.

[0075] like Figure 1As shown, the pointer-based message DMA method includes: step 110, step 120 and step 130.

[0076] Step 110: Set a first count value and a last count value for a circular queue composed of multiple descriptors; the first count value is used to indicate the usage of the descriptor; and the last count value is used to indicate the addition of a descriptor.

[0077] In computer science, DMA is a hardware feature that allows certain hardware subsystems to directly access system memory without going through the central processing unit (CPU). This mechanism can significantly improve the efficiency of data transfer, especially when processing large amounts of data.

[0078] A descriptor is a data structure used to describe a DMA transfer task, including various parameters required for DMA transfer. For example, these parameters may include control bits used to indicate the descriptor status, data packet addresses, that is, pointers to the source or destination memory area during DMA transfer, data length, next descriptor address, etc.

[0079] A circular queue is a special data structure that can be viewed as a queue connected end to end. The descriptors of a circular queue can be stored in a descriptor buffer in memory. In a circular queue, descriptors are arranged in sequence, and the next descriptor after the last descriptor is the first descriptor, so that descriptors can be recycled.

[0080] In the embodiments of the present application, Figure 2 As shown, the first count value and the tail count value can be used to manage the descriptors in the circular queue. Specifically, the first count value can be used to indicate the usage of the descriptor. For example, the first count value will be updated after the descriptor is used. The first count value can be used to understand how many descriptors are used in the circular queue. The tail count value can be used to indicate the addition of descriptors. For example, when the host adds a descriptor to the circular queue, the tail count value can be updated according to the number of newly added descriptors. The tail count value can be used to understand how many descriptors are included in the circular queue.

[0081] In some embodiments, when a new descriptor is added to the descriptor buffer storing the circular queue, the tail count value of the circular queue is updated.

[0082] In this embodiment, if a new descriptor is added to the descriptor buffer, the tail count value of the ring queue can be updated according to the number of the new descriptors. For example, if one new descriptor is added, the tail count value can be increased by 1, and if two new descriptors are added, the tail count value can be increased by 2.

[0083] In this embodiment, the tail count value is updated in time after a new descriptor is added to the descriptor buffer of the circular queue, so that the status of the descriptors in the circular queue can be timely understood based on the first count value and the tail count value. The DMA controller does not need to frequently initiate read and write requests to the host, thereby reducing the frequency of DMA read and write operations on the host and improving DMA transmission efficiency.

[0084] In some embodiments, the circular queue includes a receiving queue and a sending queue, and the receiving queue and the sending queue are respectively allocated independent descriptor buffers, in which descriptors are stored in sequence according to adjacent addresses; the first count value and the tail count value of the receiving queue and the sending queue are stored in the count value buffer of the memory.

[0085] In this embodiment, the circular queue may include a receiving queue and a sending queue. The descriptor of the receiving queue is a receiving descriptor, which is used for the DMA receiving task of the message. The DMA controller may store the received message in the memory buffer indicated by the receiving descriptor. The descriptor of the sending queue is a sending descriptor, which is used for the DMA sending task of the message. The DMA controller may read the message from the memory buffer indicated by the sending descriptor and send the message out.

[0086] In this embodiment, in the memory, each queue can be allocated with an independent descriptor buffer. In the descriptor buffer, the descriptors are stored in sequence according to adjacent addresses, so that the location information of each descriptor is not required. When adding a new descriptor, the location information of other descriptors can be determined based on the storage address of the first descriptor. Among them, the size of the descriptor buffer indicates the number of descriptors that the buffer can accommodate, and the value is a power of 2, such as 128, 256, 512, etc., which can be configured through a register.

[0087] In this embodiment, the receiving queue and the sending queue each correspond to a first count value and a tail count value. The first count value and the tail count value are not directly stored in the queue, but are stored in a separate count value buffer in the memory, and the count value buffer can be used to continuously store the first count value and the tail count value of each queue. Storing the first count value and the tail count value in the memory buffer can be more conveniently shared and accessed by the CPU and the DMA controller. For example, the DMA controller can periodically initiate a read request to read the tail count value to keep synchronization with the host, and periodically initiate a write request to update the first count value to keep synchronization with the host.

[0088] In an example, each count value has a bit width of 32 bits. If the number of queues is N, the total number of bytes of the count value that needs to be read or written each time is 2×N×4, and the starting address is the physical address of the count value in the count value buffer.

[0089] In this embodiment, independent descriptor buffers are set for the receiving queue and the transmitting queue respectively, and the head and tail count values ​​are stored independently in the memory, so that the receiving and transmitting operations can be performed in parallel without interfering with each other. The continuous storage of descriptors optimizes the memory access mode of the DMA controller, making data transmission more efficient.

[0090] Step 120 : When the number of descriptors in the descriptor cache of the DMA controller is less than a threshold, determine the availability of descriptors in the circular queue according to the first count value and the last count value.

[0091] In the embodiment of the present application, the DMA controller is a hardware module responsible for direct memory access transmission between the memory and the peripherals. The DMA controller can independently complete the data transmission task without the participation of the CPU, thereby improving the overall performance of the system.

[0092] The descriptor cache is a memory area inside the DMA controller that is used to store DMA transfer task descriptors. During message transmission, the DMA controller needs to read descriptors from the descriptor cache to obtain the relevant parameters required for data transmission. If the number of descriptors in the descriptor cache is insufficient, the DMA controller cannot obtain new transfer tasks in a timely manner, resulting in performance degradation.

[0093] When the number of descriptors in the descriptor cache of the DMA controller is less than a threshold, new descriptors need to be added from the ring queue. The availability of descriptors in the ring queue can be determined based on the first count value and the last count value. For example, the number of unused available descriptors in the ring queue can be determined by comparing the first count value and the last count value.

[0094] In some embodiments, determining availability of descriptors in the ring queue according to the first count value and the last count value includes:

[0095] Determine whether the first count value and the last count value are equal;

[0096] In the case where the head count value and the tail count value are not equal, it is determined that unused descriptors are included in the ring queue.

[0097] In this embodiment, it can be determined whether the first count value and the last count value are equal. If the last count value is greater than the first count value, it means that there are newly available descriptors in the circular queue. It can be determined that the circular queue includes unused descriptors based on the difference between the last count value and the first count value, so that new descriptors can be taken out of the circular queue and filled into its own descriptor cache, so that subsequent DMA transfer tasks can be smoothly executed.

[0098] In this embodiment, by comparing the first count value and the last count value, the availability of descriptors in the circular queue can be accurately determined. In this way, the availability of descriptors in the circular queue can be quickly determined without initiating a request to the host, thereby reducing the frequency of DMA read and write operations on the host and improving DMA transmission efficiency.

[0099] Step 140: When it is determined that the circular queue includes unused descriptors, read the descriptors from the circular queue and store them in the descriptor cache of the DMA controller.

[0100] In an embodiment of the present application, by comparing the first count value and the last count value, it is determined that there are unused descriptors in the circular queue, and then new descriptors can be taken from the circular queue and filled into the descriptor cache of the DMA controller to enable the smooth execution of subsequent DMA transfer tasks.

[0101] According to the pointer-based message DMA method of the present application, a first count value and a tail count value are set for a circular queue composed of multiple descriptors; the first count value is used to indicate the usage of the descriptor; the tail count value is used to indicate the addition of a descriptor; when the number of descriptors in the descriptor cache of a DMA controller is less than a threshold, the availability of the descriptors in the circular queue is determined according to the first count value and the tail count value; when it is determined that the circular queue includes unused descriptors, the descriptors are read from the circular queue and stored in the descriptor cache of the DMA controller. In the embodiment of the present application, the usage of descriptors is recorded by the first count value, and the addition of descriptors is recorded by the tail count value. The DMA controller can promptly understand whether there are available descriptors in the circular queue based on the first count value and the tail count value. If there are unused descriptors and the number of available descriptors in the descriptor cache of the DMA controller is lower than a threshold (configurable), the DMA controller will read these descriptors in batches from the circular queue at one time and store them in its own cache. When sending and receiving messages, if the descriptors exist in the cache of the DMA controller, they can be used directly without frequently initiating read and write requests to the host, thereby reducing the frequency of DMA read and write operations on the host and improving DMA transmission efficiency.

[0102] In some embodiments, when it is determined that the circular queue includes unused descriptors, reading the descriptors from the circular queue and storing them in a descriptor cache of the DMA controller includes:

[0103] Determine the number of requested descriptors according to at least one of the size of available space in the descriptor cache, the first count value, the last count value, and the size of the descriptor buffer storing the circular queue;

[0104] Descriptors are read from the descriptor buffer of the ring queue according to the number of requested descriptors and stored in the descriptor cache of the DMA controller.

[0105] In this embodiment, the number of descriptors to be read from the circular queue may be determined based on a variety of factors, including at least one of the size of the available space in the descriptor cache, the first count value, the last count value, and the size of the descriptor buffer storing the circular queue.

[0106] The size of the available space in the descriptor cache indicates how much space is left in the DMA controller's descriptor cache to store new descriptors. If the cache is close to full, the number of descriptors requested can be reduced to avoid overflow.

[0107] The first count value and the last count value indicate the usage and addition of descriptors in the ring queue. By comparing the first count value and the last count value, it can be determined how many descriptors are available in the ring queue.

[0108] The size of the descriptor buffer storing the circular queue indicates the number of descriptors that can be accommodated in the descriptor buffer. According to the size of the descriptor buffer, the number of requested descriptors can be made not to exceed the capacity of the circular queue.

[0109] In this embodiment, after determining the number of requested descriptors, the descriptors may be read from the descriptor buffer of the ring queue and stored in the descriptor cache of the DMA controller.

[0110] In this embodiment, by determining the number of descriptors to be requested based on at least one of the four parameters of the available space of the DMA controller descriptor cache, the first count value, the tail count value, and the size of the ring queue descriptor buffer, the DMA controller can be prevented from causing cache overflow due to requesting too many descriptors, and frequent read operations due to too few requests are reduced, thereby optimizing the DMA data transmission process, reducing the demand for host resources, and improving the system's data processing capabilities and overall efficiency.

[0111] In some embodiments, determining the number of requested descriptors according to at least one of the size of the available space of the descriptor cache, the first count value, the tail count value, and the size of the descriptor buffer storing the circular queue includes:

[0112] Calculating a first difference between the first count value and the last count value, and calculating a second difference between the first count value and the size of the descriptor buffer;

[0113] The minimum value among the size of the available space of the descriptor cache, the first difference value, and the second difference value is determined as the number of requested descriptors.

[0114] In this embodiment, a first difference between the head count value and the tail count value of the ring queue may be calculated, and the first difference represents how many unused descriptors are available in the ring queue.

[0115] A second difference between the first count value of the ring queue and the total size of the descriptor buffer may also be calculated, wherein the second difference represents the maximum number of unused descriptors in the ring queue.

[0116] The size of the available space in the descriptor cache indicates how much space is left in the descriptor cache of the DMA controller to store new descriptors, and the minimum value is taken among the first difference value, the second difference value, and the available space size of the descriptor cache of the DMA controller. The minimum value is the number of descriptors that the DMA controller should request to read from the ring queue at this time.

[0117] In this embodiment, by calculating the first difference between the first count value and the last count value, the number of descriptors currently unused in the circular queue can be understood, and by calculating the second difference between the first count value and the descriptor buffer size, the number of descriptors remaining in the circular queue can be determined, and the minimum value of the size of the descriptor cache available space, the first difference, and the second difference is determined as the requested number of descriptors, so that the DMA controller will not request descriptors exceeding the cache capacity, and will not cause cache overflow or resource waste due to excessive requests, thereby reducing unnecessary memory access, reducing dependence on host memory, and improving data processing speed.

[0118] In some embodiments, reading the descriptor from the circular queue and storing it in the descriptor buffer of the DMA controller includes:

[0119] Determine the starting position of the read according to the tail count value, the size of the descriptor buffer storing the circular queue, and the physical address where the first descriptor in the descriptor buffer storing the circular queue is stored;

[0120] The descriptor is read from the starting location and stored in the descriptor buffer of the DMA controller.

[0121] In this embodiment, since the descriptors are stored in the descriptor buffer storing the circular queue in sequence according to adjacent addresses, the positions of other descriptors can be determined according to the physical address where the first descriptor is stored. First, the position of the first available descriptor in the descriptor buffer must be determined, and the position is determined as the starting position for reading.

[0122] Specifically, the remainder obtained by dividing the tail count value by the descriptor buffer size indicates which descriptor in the descriptor buffer is the first available descriptor. The remainder is then multiplied by the size of a single descriptor (in bytes) and added to the physical address of the first descriptor in the descriptor buffer to obtain the position of the first available descriptor, that is, the starting position for reading.

[0123] In this embodiment, after determining the starting position for reading, reading can be performed from the starting position according to the number of descriptors requested. For example, descriptors can be read one by one from the starting position for reading until the number of descriptors read is equal to the number of descriptors requested.

[0124] In this embodiment, the starting position of reading is determined by the tail count value, the size of the descriptor buffer and the physical address of the first descriptor, so that the DMA controller can accurately locate the descriptor that needs to be read in the circular queue, and directly read the descriptor from the starting position and store it in the cache of the DMA controller. There is no need to initiate additional descriptor read position requests to the host, which reduces the number of accesses to the host memory and further improves the DMA transmission efficiency.

[0125] In some embodiments, the method further comprises:

[0126] When receiving a message, adding the message receiving information to a preset field in the message header;

[0127] Get the receive descriptor from the descriptor buffer of the DMA controller;

[0128] Write the message with the added receiving information into the memory buffer indicated by the receiving descriptor;

[0129] When the message in the memory buffer indicated by the receive descriptor is read, the first count value of the receive queue is updated.

[0130] In this embodiment, when a message is received, some receiving information, such as a timestamp, a source address, a length, etc., may be added to a preset field in the message header to identify the source and nature of the message.

[0131] In an example, as shown in the following table, a 4-byte custom field can be added to the message header to indicate the message reception information, without the need to transmit the message reception information in the form of a write-back descriptor, wherein the flag bit is used to determine whether there is a message in the message buffer in the memory (1 indicates there is a message, and it is cleared after the host reads it).

[0132]

[0133] In this embodiment, the receive descriptor is stored in the descriptor cache of the DMA controller, and the receive descriptor can be obtained from the descriptor cache, and the number of descriptors in the descriptor cache will be reduced by one. The receive descriptor includes a pointer to a memory buffer, including information such as the address and length of the memory buffer. According to the address of the memory buffer, the message with the received information added can be written into the memory buffer indicated by the receive descriptor.

[0134] In this embodiment, after the message in the receiving buffer is read by the upper layer application, the first count value of the receiving queue can be updated, for example, the first count value can be increased by 1, indicating that a descriptor has been used.

[0135] In this embodiment, by preprocessing the message when receiving the message, adding the receiving information in the preset field of the received message header, the host can understand the message according to this information, and the DMA controller does not need to upload the received message information by writing back the descriptor, which reduces the number of accesses to the host memory and further improves the DMA transmission efficiency. In addition, when the message in the memory buffer is read, the first count value of the receiving queue is updated, thereby synchronizing the use status of the descriptor in the ring queue, so that the host can recycle the used descriptors according to the first count value, thereby improving the management efficiency of the descriptors.

[0136] In some embodiments, the method further comprises:

[0137] In the case of sending a message, the send descriptor is obtained from the descriptor buffer of the DMA controller;

[0138] Read the message from the memory buffer indicated by the send descriptor and send it;

[0139] If the transmission is successful, the first count value of the transmission queue is updated.

[0140] In this embodiment, the descriptor cache of the DMA controller stores the send descriptor, and the send descriptor can be obtained from the descriptor cache, and the number of descriptors in the descriptor cache will be reduced by one. The send descriptor includes a pointer to a memory buffer, including information such as the address and length of the memory buffer. According to the address of the memory buffer, a message can be read from the memory buffer, and then the read message can be sent out through DMA transmission.

[0141] In this embodiment, after the message is successfully sent, the first count value of the sending queue may be updated, for example, the first count value may be increased by 1, indicating that a descriptor has been used.

[0142] In this embodiment, when sending a message, a send descriptor is obtained from the descriptor cache of the DMA controller, the message is read from the memory buffer indicated by the send descriptor and sent, and after the sending is successful, the first count value of the send queue is updated to synchronize the usage status of the descriptors in the circular queue. There is no need to upload the usage information of the descriptor by writing back the descriptor, which reduces the number of accesses to the host memory and further improves the DMA transmission efficiency.

[0143] The following example illustrates the descriptor management process. The code logic of descriptor management is as follows: Figure 3 As shown in the figure, init means initialization, bd_num means the number of descriptors in the circular queue, bd_start_addr means the starting address of the circular queue, and enable means the enable flag, which is set to 1 during initialization.

[0144] In this scenario example, first, we can check whether the head count value head and the tail count value tail are equal. If they are not equal, we proceed to the next step to determine whether the number of descriptors in the descriptor cache bd cache is lower than the threshold. If so, we proceed to the next step to determine whether the request counter req_cntr is equal to the confirmation counter ack_cntr. If they are equal, we proceed to the next step to determine whether the descriptor is about to wrap around to the beginning of the circular queue based on the tail count value tail. If so, we update the number of request descriptors req_num to the size of the descriptor buffer boundry minus the head count value. Otherwise, we update the number of request descriptors req_num to the tail count value tail minus the head count value. We proceed to the next step to increase the request counter req_cntr according to the number of request descriptors req_num, and perform the final confirmation step. If it is confirmed that all the requested descriptors are used, we update the confirmation counter ack_cntr and update the head count value head according to the number of request descriptors req_num.

[0145] The pointer-based message DMA method provided in the embodiment of the present application can be executed by a pointer-based message DMA device. In the embodiment of the present application, a pointer-based message DMA device executing the pointer-based message DMA method is taken as an example to illustrate the pointer-based message DMA device provided in the embodiment of the present application.

[0146] The embodiment of the present application also provides a pointer-based message DMA device.

[0147] like Figure 4 As shown, the pointer-based message DMA device includes:

[0148] The setting module 410 is used to set a first count value and a tail count value for a circular queue composed of multiple descriptors; the first count value is used to indicate the usage of the descriptor; the tail count value is used to indicate the addition of a descriptor;

[0149] A determination module 420, configured to determine availability of descriptors in the circular queue according to a first count value and a last count value when the number of descriptors in the descriptor cache of the DMA controller is less than a threshold value;

[0150] The reading module 430 is used to read the descriptor from the circular queue and store it in the descriptor cache of the DMA controller when it is determined that the circular queue includes unused descriptors.

[0151] According to the pointer-based message DMA device of the present application, a first count value and a tail count value are set for a circular queue composed of multiple descriptors; the first count value is used to indicate the usage of the descriptors; the tail count value is used to indicate the addition of new descriptors; when the number of descriptors in the descriptor cache of the DMA controller is less than a threshold, the availability of descriptors in the circular queue is determined according to the first count value and the tail count value; when it is determined that the circular queue includes unused descriptors, the descriptors are read from the circular queue and stored in the descriptor cache of the DMA controller. In the embodiment of the present application, the usage of descriptors is recorded by the first count value, and the addition of descriptors is recorded by the tail count value. The DMA controller can promptly understand whether there are available descriptors in the circular queue based on the first count value and the tail count value. If there are unused descriptors and the number of available descriptors in the descriptor cache of the DMA controller is lower than a threshold (configurable), the DMA controller will read these descriptors in batches from the circular queue at one time and store them in its own cache. When sending and receiving messages, if the descriptors exist in the cache of the DMA controller, they can be used directly without frequently initiating read and write requests to the host, thereby reducing the frequency of DMA read and write operations on the host and improving DMA transmission efficiency.

[0152] In some embodiments, the determination module 420 is further configured to:

[0153] Determine whether the first count value and the last count value are equal;

[0154] In the case where the head count value and the tail count value are not equal, it is determined that unused descriptors are included in the ring queue.

[0155] In some embodiments, the reading module 430 is further configured to:

[0156] Determine the number of requested descriptors according to at least one of the size of available space in the descriptor cache, the first count value, the last count value, and the size of the descriptor buffer storing the circular queue;

[0157] Descriptors are read from the descriptor buffer of the ring queue according to the number of requested descriptors and stored in the descriptor cache of the DMA controller.

[0158] In some embodiments, the reading module 430 is further configured to:

[0159] Calculating a first difference between the first count value and the last count value, and calculating a second difference between the first count value and the size of the descriptor buffer;

[0160] The minimum value among the size of the available space of the descriptor cache, the first difference value, and the second difference value is determined as the number of requested descriptors.

[0161] In some embodiments, the reading module 430 is further configured to:

[0162] Determine the starting position of the read according to the tail count value, the size of the descriptor buffer storing the circular queue, and the physical address where the first descriptor in the descriptor buffer storing the circular queue is stored;

[0163] The descriptor is read from the starting location and stored in the descriptor buffer of the DMA controller.

[0164] In some embodiments, the reading module 430 is further configured to:

[0165] When receiving a message, adding the message receiving information to a preset field in the message header;

[0166] Get the receive descriptor from the descriptor buffer of the DMA controller;

[0167] Write the message with the added receiving information into the memory buffer indicated by the receiving descriptor;

[0168] When the message in the memory buffer indicated by the receive descriptor is read, the first count value of the receive queue is updated.

[0169] In some embodiments, the reading module 430 is further configured to:

[0170] In the case of sending a message, the send descriptor is obtained from the descriptor buffer of the DMA controller;

[0171] Read the message from the memory buffer indicated by the send descriptor and send it;

[0172] If the transmission is successful, the first count value of the transmission queue is updated.

[0173] In some embodiments, the reading module 430 is further configured to:

[0174] When a new descriptor is added to the descriptor buffer storing the circular queue, the tail count value of the circular queue is updated.

[0175] The pointer-based message DMA device in the embodiment of the present application can be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or other devices other than a terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a palmtop computer, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc., and can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0176] The pointer-based message DMA device in the embodiment of the present application may be a device having an operating system. The operating system may be a Microsoft (Windows) operating system, an Android (Android) operating system, an IOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0177] In some embodiments, Figure 5 As shown, an embodiment of the present application also provides an electronic device 500, including a processor 501, a memory 502, and a computer program stored in the memory 502 and executable on the processor 501. When the program is executed by the processor 501, each process of the above-mentioned pointer-based message DMA method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0178] It should be noted that the electronic devices in the embodiments of the present application include the above-mentioned mobile electronic devices and non-mobile electronic devices.

[0179] An embodiment of the present application also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various processes of the above-mentioned pointer-based message DMA method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0180] The processor is the processor in the electronic device in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0181] An embodiment of the present application also provides a computer program product, including a computer program, which implements the above-mentioned pointer-based message DMA method when executed by a processor.

[0182] The processor is the processor in the electronic device in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0183] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned pointer-based message DMA method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0184] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0185] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0186] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0187] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

[0188] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0189] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A pointer-based message DMA method, characterized in that: include: Set the first count value and the last count value for a circular queue consisting of multiple descriptors; The first count value is used to indicate the usage of the descriptor; The tail count value is used to indicate the addition of a descriptor; When the number of descriptors in the descriptor cache of the DMA controller is less than a threshold, determining the availability of descriptors in the circular queue according to the first count value and the last count value; When it is determined that the circular queue includes unused descriptors, the descriptors are read from the circular queue and stored in a descriptor buffer of the DMA controller.

2. The method according to claim 1, characterized in that The determining, according to the first count value and the last count value, the availability of the descriptors in the ring queue comprises: Determine whether the first count value and the last count value are equal; When the head count value and the tail count value are not equal, it is determined that the ring queue includes unused descriptors.

3. The method according to claim 1, characterized in that The method of reading descriptors from the circular queue and storing them in a descriptor cache of the DMA controller when it is determined that the circular queue includes unused descriptors comprises: Determine the number of requested descriptors according to at least one of the size of the available space of the descriptor cache, the first count value, the tail count value, and the size of the descriptor buffer storing the circular queue; Descriptors are read from the descriptor buffer of the circular queue according to the number of requested descriptors and stored in the descriptor cache of the DMA controller.

4. The method according to claim 3, characterized in that The determining the number of requested descriptors according to at least one of the size of the available space of the descriptor cache, the first count value, the tail count value, and the size of the descriptor buffer storing the circular queue comprises: Calculating a first difference between the first count value and the last count value, and calculating a second difference between the first count value and the size of the descriptor buffer; The minimum value among the size of the descriptor cache available space, the first difference and the second difference is determined as the number of requested descriptors.

5. The method according to claim 1, characterized in that The circular queue includes a receiving queue and a sending queue, each of which is allocated with an independent descriptor buffer, in which descriptors are stored in sequence according to adjacent addresses; the first count value and the last count value of the receiving queue and the sending queue are stored in the count value buffer of the memory.

6. The method according to claim 5, characterized in that The step of reading the descriptor from the circular queue and storing the descriptor in the descriptor cache of the DMA controller comprises: Determine the starting position of reading according to the tail count value, the size of the descriptor buffer storing the circular queue, and the physical address where the first descriptor in the descriptor buffer storing the circular queue is stored; The descriptor is read from the starting position and stored in the descriptor buffer of the DMA controller.

7. The method according to claim 5, characterized in that The method further comprises: When receiving a message, adding the message receiving information to a preset field in the message header; Obtaining a receive descriptor from a descriptor buffer of the DMA controller; Writing the message to which the reception information is added into the memory buffer indicated by the reception descriptor; When the message in the memory buffer indicated by the receiving descriptor is read, the first count value of the receiving queue is updated.

8. The method according to claim 5, characterized in that The method further comprises: In the case of sending a message, obtaining a send descriptor from a descriptor buffer of the DMA controller; Reading a message from the memory buffer indicated by the send descriptor and sending it; When the transmission is successful, the first count value of the transmission queue is updated.

9. The method according to claim 1, characterized in that: The method further comprises: When a new descriptor is added to the descriptor buffer storing the circular queue, a tail count value of the circular queue is updated.

10. A pointer-based message DMA device, characterized in that: include: A setting module, used for setting a head count value and a tail count value for a ring queue composed of a plurality of descriptors; The first count value is used to indicate the usage of the descriptor; The tail count value is used to indicate the addition of a descriptor; A determination module, configured to determine the availability of descriptors in the circular queue according to the first count value and the last count value when the number of descriptors in the descriptor cache of the DMA controller is less than a threshold value; The reading module is used for reading the descriptors from the circular queue and storing the descriptors in the descriptor cache of the DMA controller when it is determined that the circular queue includes unused descriptors.

11. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the method according to any one of claims 1 to 9 is implemented.

12. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 9 is implemented.

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