Scheduler, integrated circuit, and image sensing device

Abstract

The invention provides a scheduler, an integrated circuit and image sensing equipment, and relates to the technical field of image processing. The scheduler is used for an integrated circuit, the integrated circuit is configured to process a sequence of image frames, the sequence of image frames comprises a first image frame, and the integrated circuit comprises a plurality of image processing modules; the scheduler is configured to activate the first image processing module to enable the first image processing module to perform first processing on the first image frame, and the plurality of image processing modules comprise the first image processing module; the scheduler is further configured to set the first image processing module to be in a standby state based on the state of the target signal, and the first image processing module modifies the state of the target signal after completing the first processing; wherein when the first image processing module is in the activated state, the scheduler sets the image processing modules, except the first image processing module, in the integrated circuit to be in a standby state. The scheduler can reduce the power consumption of the integrated circuit where the scheduler is located in the using process.

Description

Technical Field

[0001] The present application relates to the field of image processing technology, and in particular to a scheduler, an integrated circuit, and an image sensing device. Background Art

[0002] In existing application scenarios, there are media processing pathways consisting of multiple modules, such as image processing, video encoding and decoding, signal transmission, etc. Each module has its specific function in the entire pathway. These modules will remain in operation until all services are completed, and they will still consume a certain amount of power even when there are no processing tasks or the load is very low. When the power consumption of each module is added together, it will form the overall power consumption of the entire integrated circuit, such as the system on chip (SOC). Therefore, if each module remains in operation, the total power consumption of the integrated circuit will be high.

[0003] Therefore, how to reduce the power consumption of integrated circuits during use is an urgent problem to be solved. Summary of the invention

[0004] In view of this, the present application discloses a scheduler, an integrated circuit and an image sensing device to reduce the power consumption of the integrated circuit during use.

[0005] In a first aspect, the present application discloses a scheduler for an integrated circuit, wherein the integrated circuit is configured to process an image frame sequence, the image frame sequence includes a first image frame, and the integrated circuit includes several image processing modules; the scheduler is configured to activate the first image processing module so that the first image processing module performs a first processing on the first image frame, and the several image processing modules include the first image processing module; the scheduler is also configured to set the first image processing module to a standby state based on the state of a target signal, and the first image processing module modifies the state of the target signal after completing the first processing; wherein, when the first image processing module is in an activated state, the scheduler sets the image processing modules other than the first image processing module in the integrated circuit to a standby state.

[0006] Optionally, the plurality of image processing modules further include a second image processing module; when the scheduler sets the second image processing module to standby state, at least one of the following operations is performed: cutting off the power supply of the second image processing module or shutting down the clock source of the second image processing module.

[0007] Optionally, after the first image processing module is switched from the active state to the standby state, the scheduler is configured to set the second image processing module to the active state based on the state of the target signal.

[0008] Optionally, the scheduler is configured to set a processing order for several image processing modules to process the first image frame, and the first image frame passes through the first image processing module and the second image processing module successively; the second image processing module performs a second process on the first image frame when in an activated state.

[0009] Optionally, when the scheduler sets the second image processing module to standby mode, it reads the properties of the power supply and clock source of the first image processing module and the second image processing module, determines whether the power supply of the first image processing module and the second image processing module is a shared power supply and whether the clock source of the first image processing module and the second image processing module is a shared clock source, and performs at least one of the following operations based on the result of the judgment: cutting off the power supply of the second image processing module or turning off the clock source of the second image processing module.

[0010] Optionally, when the power supply of the first image processing module and the second image processing module is a shared power supply, the scheduler turns off the clock source of the second image processing module; when the clock source of the first image processing module and the second image processing module is a shared clock source, the scheduler cuts off the power supply of the second image processing module; when the power supply of the first image processing module and the second image processing module is not a shared power supply and the clock source of the first image processing module and the second image processing module is not a shared clock source, the scheduler performs at least one of the following operations: cuts off the power supply of the second image processing module or turns off the clock source of the second image processing module.

[0011] Optionally, the image frame sequence includes a second image frame; after the first image frame passes through a plurality of image processing modules in sequence, the scheduler activates the first image processing module so that the first image processing module performs the first processing on the second image frame.

[0012] Optionally, the integrated circuit also includes a counting module, which is configured to start counting after the first image frame passes through several image processing modules in sequence; the scheduler reads the counting result of the counting module, and activates the first image processing module when the counting result exceeds a preset time so that the first image processing module performs the first processing on the second image frame.

[0013] In a second aspect, the present application discloses an integrated circuit, comprising the scheduler disclosed in the first aspect above.

[0014] In a third aspect, the present application discloses an image sensing device, comprising the integrated circuit disclosed in the second aspect above.

[0015] To summarize, the scheduler, integrated circuit, and image sensing device disclosed in the present application have at least the following beneficial effects: only the scheduled image processing modules perform business processing, and the unscheduled image processing modules are powered off or clock-off by default to save power consumption of the integrated circuit; when performance requirements are not high, the use of the scheduler of the present application can improve the on-machine time of the system equipment and save the cost of battery equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following is a brief introduction to the drawings used in describing the embodiments of the present application:

[0017] Figure 1 The diagram is a schematic diagram of an image processing chip in the prior art processing an image frame.

[0018] Figure 2 This is a structural example diagram of an integrated circuit provided in an embodiment of the present application.

[0019] Figure 3 This is a structural example diagram of another integrated circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the specific implementation methods of the present application will be described below with reference to the accompanying drawings. The accompanying drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other accompanying drawings and other implementation methods can be obtained based on these drawings without creative work. Adjustments and improvements made without departing from the concept of the present application are all within the scope of protection of the present application.

[0021] In order to simplify the drawings, only the parts related to the corresponding embodiments are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, only part of the components with the same structure or function in some figures are schematically drawn, and there may be more or fewer components with the same structure or function in reality.

[0022] In this application, unless otherwise clearly specified and limited, ordinal numbers, such as "first", "second", etc., are only used to distinguish and describe associated objects, and cannot be understood as indicating or implying the relative importance or order between associated objects; in addition, they do not represent the number of associated objects. "Multiple" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between associated objects, which indicates the "or" relationship between associated objects. "And / or" is used to describe the relationship between associated objects, which includes any combination relationship between associated objects, such as "a and / or b" includes: "alone a", "alone b", or "a and b". "One or more" or "at least one" in multiple objects refers to any object or any combination of multiple objects, such as "one or more of a1, a2, a3" or "at least one of a1, a2, a3" includes: "alone a1", "alone a2", "alone a3", "a1 and a2", "a1 and a3", "a2 and a3", or "a1, a2 and a3".

[0023] In today's multimedia application scenarios, multiple functional modules are usually involved in jointly building a complex media processing path. This path includes modules such as image processing, video encoding and decoding, audio processing, and signal transmission. Each module plays a specific role in it, and works together to complete a series of processing processes such as acquisition, conversion, encoding, and transmission of media data. In some practical applications, in order to improve the system's ability to respond to user operations and task requests, these modules can be set to remain in working state before all services are completed. In this way, even in idle periods when there are no processing tasks, or when the system load is very low, they will not completely enter a dormant or closed state, which will inevitably consume a certain amount of power. This normal power consumption is accumulated together, which may be small for a single module, but at the system level, especially for the entire integrated circuit, the superposition of the power consumption of each module will gradually become significant, resulting in a high total power consumption of the entire integrated circuit. For an image processing chip, its essence may be an integrated circuit, and several image processing modules are integrated on the integrated circuit. In this application, the meanings expressed by the integrated circuit and the image processing chip are consistent. The following is described in conjunction with the accompanying drawings.

[0024] Figure 1 This is a schematic diagram of an image processing chip in the prior art processing an image frame. Figure 1 ,In the integrated circuit, several image processing modules are included, e.g. Figure 1The image signal processor (ISP), video post-processor (VPP), digital signal processor (DSP), neural processing unit (NPU), application central processing unit (ACPU) and video encoder (VENC) are shown. The above image processing modules process the image frame sequence in sequence, where the image frame sequence is used to represent an ordered sequence composed of several image frames; Figure 1 In the example, the image frame sequence includes a first image frame Frame1, a second image frame Frame2, a third image frame Frame3, a fourth image frame Frame4, a fifth image frame Frame5, a sixth image frame Frame6 and a seventh image frame Frame7, and these image frames have the following characteristics: Figure 1The order shown. In the above image processing modules, ISP is mainly responsible for processing the raw image data collected by the image sensor (such as CMOS or CCD), including denoising, white balance adjustment, color correction, gamma correction, sharpening, automatic exposure adjustment and other operations. Its function is to convert the raw image data (such as RAW format) output by the sensor into a clear and color-accurate image for use by subsequent processing modules. VPP is responsible for performing various optimization tasks in the post-processing stage of video data, such as resolution scaling, frame rate conversion, color space conversion, sharpening, brightness adjustment, etc. It is mainly used to improve the quality of video display and ensure that the video output is suitable for the needs of the target display device (such as adjusting to the resolution and color format of a specific screen). DSP is a dedicated processor designed to perform efficient mathematical calculations and is suitable for image and video processing needs. It can accelerate complex signal processing tasks such as filtering, convolution, Fourier transform, etc., and can be used in image and video decoding, encoding and enhancement processing, especially suitable for real-time audio and video processing scenarios. NPU is designed to accelerate the inference of neural network models and is a hardware acceleration unit for machine learning, image recognition, target detection and other AI-related processing tasks. It can be used in image processing systems for artificial intelligence functions such as face recognition, object classification, and motion detection, giving the device more intelligent image processing capabilities. ACPU is a processing unit used to run high-level applications, which can be a multi-core general-purpose processor (such as the ARM Cortex-A series). In the image processing process, ACPU is mainly responsible for non-real-time and non-urgent processing tasks, including high-level application logic control, algorithm scheduling, etc. It can also collaborate with other processing units to perform image enhancement and post-effect processing. VENC is responsible for compressing and encoding raw video data into standard video formats (such as H.264, H.265) for easy storage or transmission. The encoder compresses video data to reduce the size of video files while ensuring image quality as much as possible. It is suitable for scenarios such as video recording and video streaming transmission. Its function is to convert processed video frames into a coded format to make it easy for network transmission or storage.

[0025] When performing image processing, the integrated circuit uses ISP to process Frame1 in the first time period (i.e., the time period represented by 0-T1 in the figure). The integrated circuit uses VPP to process Frame1 in the second time period (i.e., the time period represented by T1-T2 in the figure), and uses ISP to process Frame2. The integrated circuit uses DSP to process Frame1, uses VPP to process Frame2, and uses ISP to process Frame3 in the third time period (i.e., the time period represented by T2-T3 in the figure). The integrated circuit uses NPU to process Frame1, uses DSP to process Frame2, uses VPP to process Frame3, and uses ISP to process Frame4 in the fourth time period (i.e., the time period represented by T3-T4 in the figure). The integrated circuit uses ACPU to process Frame1, uses NPU to process Frame2, uses DSP to process Frame3, uses VPP to process Frame4, and uses ISP to process Frame5 in the fifth time period (i.e., the time period represented by T4-T5 in the figure). In the sixth time period (i.e., the time period represented by T5-T6 in the figure), the integrated circuit uses VENC to process Frame1, uses ACPU to process Frame2, uses NPU to process Frame3, uses DSP to process Frame4, uses VPP to process Frame5, and uses ISP to process Frame6. After T6, the integrated circuit completes all processing operations on Frame1, and Frame1 is transmitted to the subsequent memory or processor, and the memory stores Frame1 or the processor further processes Frame1. In the seventh time period (i.e., the time period represented by T6 after the figure), the integrated circuit uses VENC to process Frame2, uses ACPU to process Frame3, uses NPU to process Frame4, uses DSP to process Frame5, uses VPP to process Frame6, and uses ISP to process Frame7. In other words, Frame7 and subsequent image frames will also be processed in sequence by the various image processing modules in the integrated circuit.

[0026] Figure 1The integrated circuit shown includes 6 types of image processing modules, which are only used as examples; in actual applications, the types and corresponding quantities of image processing modules can be set according to needs. In the above image processing process, all image processing modules are in an activated state, such as VPP, DSP, NPU, ACPU and VENC in the first time period. Although these modules are not directly in working state in the above first time period, they are also in an activated state and generate certain power consumption. The activated state means that the module is powered on, or the clock corresponding to the module is running.

[0027] The above disclosed image processing chip processes image frames in a way that will result in a large overall power consumption in the integrated circuit, and reducing power consumption is one of the important links in integrated circuit design. If the integrated circuit is in a high power consumption state for a long time, it is not conducive to application scenarios that are sensitive to power consumption (such as mobile devices, battery-powered systems). In this case, optimizing the working state of each module, reasonably managing its power consumption, or allowing modules with no tasks or low loads to enter low power consumption or sleep mode through dynamic power management strategies, becomes a key measure to reduce the overall power consumption of the integrated circuit. In other words, for low-power scenarios, such as when there are fewer image frames to be processed, or when the processing speed requirement is low, the power consumption of the integrated circuit during use can be reduced by setting the state of each image management module in the integrated circuit and setting the processing method of the image frame. In this way, the service life of the integrated circuit can be extended and the user experience can be improved; and heat can be reduced to improve the reliability of the image sensing device in which the integrated circuit is located.

[0028] Figure 2 This is a structural example diagram of an integrated circuit provided in an embodiment of the present application. Please refer to Figure 2 The present application discloses a scheduler 201 for an integrated circuit 200, wherein the integrated circuit 200 is configured to process an image frame sequence, wherein the image frame sequence includes a first image frame (in Figure 2 The integrated circuit 200 includes an image processing module group 210, which includes a plurality of image processing modules (the plurality of image processing modules are shown in FIG. Figure 2 In the figure, the first image processing module 211, the second image processing module 212, the third image processing module 213, the fourth image processing module 214 and the fifth image processing module 215 are represented. It should be noted that the number of image processing modules in the image processing module group 210 is not limited to Figure 2As shown, there are 5, and this number can be set according to actual needs, and this application does not impose any restrictions on this); the scheduler 201 is configured to activate the first image processing module 211, so that the first image processing module 211 performs a first processing on the first image frame, and the several image processing modules include the first image processing module 211; the scheduler 201 is also configured to set the first image processing module 211 to a standby state based on the state of the target signal, and the first image processing module 211 modifies the state of the target signal after completing the first processing; wherein, when the first image processing module 211 is in an activated state, the scheduler 201 sets the image processing modules other than the first image processing module 211 in the integrated circuit 200 to a standby state.

[0029] Exemplarily, the first image processing module 211 may be the image signal processor ISP mentioned above, the second image processing module 212 may be the video post-processor VPP mentioned above, the third image processing module 213 may be the digital signal processor DSP mentioned above, the fourth image processing module 214 may be the neural network processor NPU mentioned above, and the fifth image processing module 215 may be the video encoder VENC mentioned above. The image frame sequence may include, for example, N image frames, namely, the first image frame, the second image frame (in Figure 2 In the figure, it is represented as a square grid, and the inside of the grid is marked as 2)... The Nth image frame (in Figure 2 In the figure, it is represented as a square grid, and the inside of the grid is marked with N). An image frame refers to a single static image in a video or a continuous image sequence. In video processing, a frame is a static image presented continuously at a certain frequency, and each frame records the complete scene information at a certain moment. Multiple image frames are played continuously to form a dynamic visual effect. One form of image frame sequence is video. The essence of video is a series of image frames played in sequence quickly and continuously, so that the human eye produces a continuous dynamic effect.

[0030] When the integrated circuit 200 starts working, the scheduler 201 first activates the first image processing module 211 so that the first image processing module 211 performs the first processing on the first image frame. For example, if the first image processing module 211 is an ISP, the first processing may be one or more of operations such as denoising, white balance adjustment, color correction, gamma correction, sharpening, and automatic exposure adjustment. After the first image processing module 211 completes the first processing of the first image frame, the first image processing module 211 modifies the state of the target signal in the scheduler 201. For example, the target signal may be a flag bit dedicated to the first image processing module 211. When the first image processing module 211 is in an activated state, the value of the flag bit is 1; when the first image processing module 211 completes the first processing, the value of the flag bit is modified to 0. When the scheduler 201 detects that the value of the flag bit is 0, the first image processing module 211 is set to a standby state to save the power consumption of the first image processing module 211, thereby reducing the power consumption of the integrated circuit 200. The image processing module in the standby state may consume almost no power. For another example, the target signal can be a count value stored in a register. When the first image processing module 211 is in an activated state, the count value is 1; after the first image processing module 211 completes the first processing, the count value is modified to 2. When the scheduler 201 detects that the value of the flag is 2, the first image processing module 211 is set to a standby state, and the second image processing module 212 can be immediately activated to process the first image frame, or the second image processing module 212 can be activated to process the first image frame after a certain delay. By setting a certain delay between adjacent image processing modules, such as a millisecond delay, the flexibility of scheduling in the integrated circuit 200 can be improved, and the purpose of power saving can be further achieved. In the above examples, the specific values ​​of the flags and the count values ​​in the registers are only used as examples, and the present application does not limit this.

[0031] In some embodiments of the present application, the scheduler 201 can be implemented by software or by hardware, and the number of schedulers 201 is greater than or equal to one. For example, the scheduler 201 can be implemented by an ACPU. In this case, the ACPU can run a scheduling algorithm to control the activation and standby of each image processing module. When the scheduler 201 is implemented by software, it can be determined whether the corresponding image processing module has completed the corresponding processing by judging whether the value of the flag bit has changed. When the scheduler 201 is implemented by hardware, it can be determined whether the corresponding image processing module has completed the corresponding processing by the level state of a detection signal. For example, when the detection signal is in a high level state, the scheduler 201 determines that the image processing module has completed the corresponding processing. The number of schedulers 201 can be set according to user needs. For example, a scheduler can be assigned to each image processing module, or a plurality of image processing modules can be controlled by one scheduler.

[0032] In addition, when the first image processing module 211 is in the active state, the scheduler 201 sets the image processing modules in the integrated circuit 200 other than the first image processing module 211 to the standby state. That is, when the first image processing module 211 is in the active state, the second image processing module 212, the third image processing module 213, the fourth image processing module 214 and the fifth image processing module 215 are all in the standby state, thus achieving the purpose of saving power consumption.

[0033] Through the above technical means, only the scheduled image processing modules perform business processing, while the unscheduled image processing modules are powered off or clock-off by default to save the power consumption of the integrated circuit; when the performance requirements are not high, the use of the scheduler of this application can increase the on-machine time of the system equipment and save the cost of battery equipment.

[0034] In some embodiments of the present application, when the first image frame is processed by any image processing module in the integrated circuit 200, all image frames except the first image frame are in a waiting state; that is, at any moment, only one image frame is processed by the image processing module, thereby achieving the purpose of saving power consumption.

[0035] In some embodiments of the present application, the plurality of image processing modules further include a second image processing module 212; when the scheduler 201 sets the second image processing module 212 to the standby state, at least one of the following operations is performed: cutting off the power supply of the second image processing module 212 or turning off the clock source of the second image processing module 212. That is, the method by which the scheduler 201 sets any image processing module to the standby state is to control the power supply and clock source corresponding to the image processing module, and by turning off its power signal or clock signal, the image processing module enters the standby state to reduce power consumption.

[0036] Figure 3 This is a structural example diagram of another integrated circuit provided in an embodiment of the present application. Please refer to Figure 3 When the scheduler 301 sets the second image processing module 312 to the standby state, it reads the properties of the power supply and clock source of the first image processing module 311 and the second image processing module 312, determines whether the power supply of the first image processing module 311 and the second image processing module 312 is a shared power supply and whether the clock source of the first image processing module 311 and the second image processing module 312 is a shared clock source, and performs at least one of the following operations based on the result of the judgment: cutting off the power supply of the second image processing module 312 or turning off the clock source of the second image processing module 312.

[0037] In some embodiments of the present application, when the power sources of the first image processing module 311 and the second image processing module 312 are a shared power source, the scheduler 301 turns off the clock source of the second image processing module 312; when the clock sources of the first image processing module 311 and the second image processing module 312 are a shared clock source, the scheduler 301 cuts off the power supply of the second image processing module 312; when the power sources of the first image processing module 311 and the second image processing module 312 are not a shared power source and the clock sources of the first image processing module 311 and the second image processing module 312 are not a shared clock source, the scheduler 301 performs at least one of the following operations: cuts off the power supply of the second image processing module 312 or turns off the clock source of the second image processing module 312.

[0038] exist Figure 3In the embodiment, the first image processing module 311 and the second image processing module 312 share the power supply 330, that is, the two are in the same power domain. However, the two are not in the same clock domain. The clock source 300 divides the clock signal c into a first clock signal c1 and a second clock signal c2 through a first frequency divider 310 and a second frequency divider 320. When the first image processing module 311 performs the first processing on the first image frame, the scheduler sets the second image processing module 312 to the standby state by turning off the second frequency divider 320. Since the first image processing module 311 and the second image processing module 312 share the power supply 330, if it is turned off, the normal operation of the first image processing module 311 may be affected. The scheduler 301 can determine whether to turn off the power supply or the clock source according to the properties of the power supply and clock source of the first image processing module 311 and the second image processing module 312. When the first image frame is processed by the first image processing module 311, the scheduler 301 can turn off the first frequency divider 310 and set the first image processing module 311 to a standby state by eliminating the first clock signal c1; and the scheduler 301 can turn on the second frequency divider 320 so that the second frequency divider 320 transmits the second clock signal c2 to the second image processing module 312, thereby activating the second image processing module 312. After the second image processing module 312 processes the first image frame, the scheduler 301 turns off the second frequency divider 320 and determines the next third image processing module ( Figure 3 The scheduler 301 determines whether the first image processing module 311 and the second image processing module 312 use the power supply 330 together (not shown). If the power supply 330 is not used to supply power to the third image processing module, the scheduler 301 turns off the power supply 330 to save power consumption. Considering that each image processing module consumes power even when it is not performing image processing operations, turning off the power supplies corresponding to these image processing modules can effectively solve this problem. The leakage power consumption of the module still consumes a small amount of power when the module is not working, which is mainly due to the leakage current inside the semiconductor device. In low-power design, it is particularly important to reduce the leakage power consumption of the non-working module. For businesses with low performance requirements, the use of the above design can not only maintain work efficiency, but also reduce the power consumption of the integrated circuit.

[0039] In some embodiments of the present application, after the first image processing module is switched from an active state to a standby state, the scheduler is configured to set the second image processing module to an active state based on the state of the target signal. Exemplarily, when the first image processing module completes processing of the first image frame, it modifies a flag in the scheduler, and the scheduler detects the modification of the flag, then sets the first image processing module to a standby state and sets the second image processing module to an active state, so that the second image processing module further processes the first image frame.

[0040] In some embodiments of the present application, the scheduler is configured to set a processing order of a first image frame by a plurality of image processing modules, and the first image frame passes through the first image processing module and the second image processing module in sequence; the second image processing module performs a second process on the first image frame when activated. Each image processing module has a certain order of processing of the image frame. For example, the first image frame can be processed by the first image processing module, the second image processing module, the third image processing module, the fourth image processing module, and the fifth image processing module in sequence, and each image processing module processes the image frame in a different manner.

[0041] In some embodiments of this application, please continue to refer to Figure 2 , the image frame sequence includes a second image frame; after the first image frame passes through a plurality of image processing modules in sequence, the scheduler 201 activates the first image processing module 211 so that the first image processing module 211 performs the first processing on the second image frame. That is to say, after the first image frame is processed by each image processing module in the image processing module group 210, the scheduler 201 sets the fifth image processing module 215 to the standby state, and reactivates the first image processing module 211 so that the first image processing module 211 performs the first processing on the second image frame, and starts a new round of circulation. This cycle is repeated until all image frames in the image frame sequence are processed by the integrated circuit 200, indicating that this service is terminated.

[0042] In some embodiments of this application, please continue to refer to Figure 2 The integrated circuit 200 further includes a counting module 220, which is configured to start counting after the first image frame passes through a plurality of image processing modules in sequence; the scheduler 201 reads the counting result of the counting module 220, and activates the first image processing module 211 when the counting result exceeds a preset time so that the first image processing module 211 performs the first processing on the second image frame. Exemplarily, the preset time may be 10ms, and after the first image frame is processed by the integrated circuit 200, the counting module 220 starts counting, and when the counting result exceeds 10ms, the scheduler 201 activates the first image processing module 211 so that it starts processing the second image frame.

[0043] Based on similar technical concepts, the present application discloses an integrated circuit, including the scheduler disclosed in the above embodiments.

[0044] Based on similar technical concepts, the present application discloses an image sensing device, including the integrated circuit disclosed in the above embodiments. The image sensing device can be, for example, various cameras (CCD camera, CMOS camera, infrared thermal imaging camera, etc.) or a laser radar.

[0045] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. A scheduler, characterized in that: for an integrated circuit, the integrated circuit being configured to process a sequence of image frames, the sequence of image frames including a first image frame, the integrated circuit comprising a plurality of image processing modules; The scheduler is configured to activate a first image processing module so that the first image processing module performs a first process on the first image frame, and the plurality of image processing modules include the first image processing module; The scheduler is further configured to set the first image processing module to a standby state based on a state of a target signal, the first image processing module modifying the state of the target signal after completing the first processing; Wherein, when the first image processing module is in the activated state, the scheduler sets the image processing modules other than the first image processing module in the integrated circuit to the standby state.

2. The scheduler according to claim 1, characterized in that The plurality of image processing modules further include a second image processing module; When the scheduler sets the second image processing module to the standby state, the scheduler performs at least one of the following operations: cutting off the power supply of the second image processing module or shutting down the clock source of the second image processing module.

3. The scheduler according to claim 2, characterized in that After the first image processing module is switched from the active state to the standby state, the scheduler is configured to set the second image processing module to the active state based on a state of the target signal.

4. The scheduler according to claim 3, characterized in that: The scheduler is configured to set a processing order of the plurality of image processing modules on the first image frame, and the first image frame passes through the first image processing module and the second image processing module in sequence; The second image processing module performs a second process on the first image frame in the activated state.

5. The scheduler according to claim 2, characterized in that: When the scheduler sets the second image processing module to the standby state, it reads the properties of the power supply and clock source of the first image processing module and the second image processing module, determines whether the power supply of the first image processing module and the second image processing module is a shared power supply and whether the clock source of the first image processing module and the second image processing module is a shared clock source, and performs at least one of the following operations based on the result of the determination: cutting off the power supply of the second image processing module or turning off the clock source of the second image processing module.

6. The scheduler according to claim 5, characterized in that When the power supplies of the first image processing module and the second image processing module are a shared power supply, the scheduler turns off the clock source of the second image processing module; When the clock sources of the first image processing module and the second image processing module are a shared clock source, the scheduler cuts off the power supply of the second image processing module; When the power supplies of the first image processing module and the second image processing module are not a shared power supply and the clock sources of the first image processing module and the second image processing module are not a shared clock source, the scheduler performs at least one of the following operations: cutting off the power supply of the second image processing module or shutting down the clock source of the second image processing module.

7. The scheduler according to claim 1, characterized in that: The sequence of image frames includes a second image frame; After the first image frame passes through the plurality of image processing modules in sequence, the scheduler activates the first image processing module to enable the first image processing module to perform the first processing on the second image frame.

8. The scheduler according to claim 7, characterized in that: The integrated circuit further comprises a counting module, wherein the counting module is configured to start counting after the first image frame passes through the plurality of image processing modules in sequence; The scheduler reads a counting result of the counting module, and activates the first image processing module when the counting result exceeds a preset time so that the first image processing module performs the first processing on the second image frame.

9. An integrated circuit, characterized in that: Comprising a scheduler as described in any one of claims 1-8.

10. An image sensing device, characterized in that: Comprising the integrated circuit of claim 9.

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