Slave device, communication system, imaging apparatus, master device, and data communication method

Abstract

The invention provides a slave device, a communication system, an imaging apparatus, a master device, and a data communication method. The slave device is provided with: an ID storage unit that stores IDs in which a predetermined order is uniquely assigned to each of the plurality of slave devices; the communication unit receives a control signal transmitted from the master device, the control signal including address information indicating an address shared by the plurality of slave devices, designation information designating a slave device to be a subject of data communication, and data length information indicating a length of data received or transmitted by the slave device designated by the designation information in a predetermined order. And a control unit that determines that communication with the master device is not performed when the control unit is not selected in accordance with the designation information, and that, when the control unit is selected in accordance with the designation information, determines the order in the selected slave device so as to read or write data of the data length indicated by the data length information from or to the register of the slave device in accordance with the ID and the designation information. And performs data communication with the master device at a timing corresponding to the sequence.

Description

Technical Field

[0001] The present invention relates to a slave device, a communication system, a camera apparatus, a master device and a data communication method. Background Art

[0002] Patent document 1 discloses an I2C communication device capable of changing an address. Patent document 2 discloses a communication device for managing a slave device in which a plug-in module is added to a platform. Patent document 3 discloses a method for providing registers for storing inherent slave addresses, global addresses, and serial numbers for multiple integrated circuits communicating with a host. Patent document 4 discloses a method for communicating by attaching a virtual device address as a global device to multiple devices.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application No. 2004-510228

[0006] Patent Document 2: International Publication No. 2014 / 083707 Pamphlet

[0007] Patent Document 3: Chinese Patent Application Publication No. 112148656

[0008] Patent Document 4: U.S. Patent Application Publication No. 2016 / 0314087 Summary of the invention

[0009] Problem that the invention aims to solve

[0010] A system is desired in which a master device and some of a plurality of slave devices having the same common address can perform data communication while suppressing the pressure on the communication band.

[0011] Solutions for solving problems

[0012] In a first aspect of the present invention, a slave device that performs data communication with a master device via a bus is provided. The slave device includes a communication unit that performs data communication with the master device based on a control signal including address information indicating an address shared by a plurality of slave devices, designation information that specifies at least one slave device among the plurality of slave devices that is the object of data communication, and data length information indicating the length of data received or sent by the slave device specified by the designation information in a predetermined order, so as to read data of a data length indicated by the data length information from a register of the slave device or write data of a data length indicated by the data length information to the register in accordance with the predetermined order and the designation information.

[0013] In the slave device, each of the plurality of slave devices may have an ID uniquely assigned in a predetermined order. The communication unit may determine the order of reading or writing the data based on the ID and the designation information.

[0014] In any of the slave devices, each of the plurality of slave devices may be uniquely assigned a predetermined order. The designated information may have a first bit string, and at least one of the plurality of slave devices that is the object of data communication is assigned to each bit of the first bit string. In the case where the slave device is assigned to a bit with a first value in the first bit string, the communication unit may receive or send data of a data length indicated by the data length information in accordance with the predetermined order and the designated information. In the case where the slave device is assigned to a bit with a second value in the first bit string, the communication unit may determine that the slave device is not the object of data communication.

[0015] In any of the slave devices, the address information may include a first bit indicating whether the slave device should read data or write data. The communication unit may determine whether the slave device should read data or write data based on the first bit.

[0016] In any of the slave devices, the data length information may have a second bit string corresponding to the register address and data length of the slave device from which the slave device should read or write data. The communication unit may determine the register address and data length of the slave device from which the slave device should read or write data, corresponding to the second bit string contained in the data length information, by referring to a mapping representing the relationship between the second bit string and the register address and data length of the slave device from which the slave device should read or write data. In the case where the slave device is the object of data communication, the communication unit may receive or send data of the data length indicated by the data length information in accordance with the predetermined order and the designated information by accessing the register address of the slave device from which the slave device should read or write data.

[0017] In any of the slave devices, each of the plurality of slave devices may be uniquely assigned a predetermined order. The address information may include a first bit indicating whether the slave device should read data or write data. The designated information may have a first bit string, and at least one slave device that is the object of data communication among the plurality of slave devices is assigned to each bit of the first bit string. The data length information may have a second bit string corresponding to the register address and data length of the slave device to which the slave device should read or write data. The communication unit may determine whether the slave device should read data from the register or write data to the register based on the first bit. In the case where the address information indicates the common address and the slave device is assigned to a bit with a first value in the first bit string, the communication unit may determine that the slave device is the object of data communication. In the case where the address information indicates the common address and the slave device is assigned to a bit with a second value in the first bit string, the communication unit may determine that the slave device is not the object of data communication. In the case where the slave device is the object of data communication, the communication unit can determine the register address and data length of the slave device to which the slave device should read or write data corresponding to the second bit string included in the data length information by referring to a mapping indicating the relationship between the second bit string and the register address and data length of the slave device to which the slave device should read or write data. In the case where the slave device is the object of data communication, the communication unit can receive or send data of the data length indicated by the data length information in accordance with the predetermined order and the designated information by accessing the register address of the slave device to which the slave device should read or write data.

[0018] In any of the slave devices, the address information may represent the common address or an independent address that uniquely identifies each of the multiple slave devices. In the case where the address information represents the independent address, the control signal may include register information representing the register address of the slave device corresponding to the independent address, where the slave device as the object of data communication should read or write data, instead of the designated information and the data length information. In the case where the address information represents the independent address of the slave device, the communication unit may perform data communication with the master device to read or write data by accessing the register address of the slave device shown in the register information.

[0019] In any of the slave devices, the slave device may perform data communication with the master device via I2C communication.

[0020] In any of the slave devices, the slave device may be an IC (Integrated Circuit) chip.

[0021] In a second aspect of the present invention, there is provided a communication system including: any one of the slave devices; and the master device that transmits the control signal to the plurality of slave devices via the bus.

[0022] In a third aspect of the present invention, a camera device is provided, comprising: the communication system; and a plurality of camera units, each of which has an optical system, an image pickup element, and a driving unit, the image pickup element photographing an image formed by the optical system, the driving unit driving at least one of the optical system and the image pickup element, and each of the plurality of slave devices drives at least one of each of the optical systems and the image pickup element by controlling each of the driving units according to each of the data.

[0023] In a fourth aspect of the present invention, a camera device is provided, comprising: the communication system; and a camera unit, which has an optical system, a camera element and a driving unit, the camera element captures an image formed by the optical system, the driving unit drives at least one of the optical system and the camera element, and each of the multiple slave devices drives at least one of the optical system and the camera element by controlling the driving unit according to each of the data.

[0024] In a fifth aspect of the present invention, a master device is provided for performing data communication with a plurality of slave devices via a bus. The master device includes a communication unit, and the communication unit performs data communication with at least one slave device that is a target of data communication among the plurality of slave devices by sending a control signal to the plurality of slave devices via the bus, wherein the control signal includes address information indicating an address shared by the plurality of slave devices, designation information specifying at least one slave device that is a target of data communication among the plurality of slave devices, and data length information indicating the length of data received or sent in a predetermined order by the slave device specified by the designation information.

[0025] In a sixth aspect of the present invention, a data communication method is provided, in which data communication is performed between a master device and a plurality of slave devices via a bus. The data communication method includes the following stages: a slave device among the plurality of slave devices receives a control signal from the master device, the control signal including address information indicating an address shared by the plurality of slave devices, designation information specifying at least one slave device among the plurality of slave devices that is the object of data communication, and data length information indicating the length of data received or sent by the slave device specified by the designation information in a predetermined order; and when the slave device is designated as the object of data communication according to the designation information, the slave device performs data communication with the master device based on the control signal, so as to read data of the data length indicated by the data length information from a register of the slave device or write data to a register of the slave device in accordance with the predetermined order and the designation information.

[0026] In addition, the above summary of the invention does not list all the features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 1 is a diagram showing an example of a schematic diagram of a user terminal 100 including an imaging device 10 including a plurality of cameras 12 a to 12 c.

[0028] Figure 2 This is a diagram showing an example of the configuration of the cameras 12a to 12c.

[0029] Figure 3 It is a diagram showing an example of the structure of the substrates 16 and 26.

[0030] Figure 4 This is a diagram showing an example of a conventional master-slave structure for controlling IC chips.

[0031] Figure 5 1 is a diagram showing an example of a control signal transmitted by the master device 20 to control six slave devices 22a to 22f.

[0032] Figure 6 22 is a diagram showing another example of a control signal transmitted by the master device 20 to control six slave devices 22a to 22f.

[0033] Figure 7 This is a diagram showing an example of the configuration of a communication system according to the present embodiment.

[0034] Figure 8 It is a diagram showing an example of the structure of the slave device 32.

[0035] Fig. 9It is a diagram showing an example of the control signal 90 according to the embodiment.

[0036] Fig.10 2 is a diagram showing an example of the structure of the ADRS bit 94.

[0037] Fig.11 This is a diagram showing an example of a reference table indicating combinations of control targets of the slave device 32 (IC chip) according to the embodiment.

[0038] Fig.12 This is a diagram showing an example of a control map according to the embodiment.

[0039] Fig.13 1 is a diagram showing an example of the control signal 130 when one byte is written according to the embodiment.

[0040] Fig.14 1 is a diagram showing an example of the control signal 140 when 2-byte writing is performed according to the embodiment.

[0041] Fig.15 1 is a diagram showing an example of a control signal 150 when two bytes are written according to the embodiment.

[0042] Fig.16 1 is a diagram showing an example of the control signal 160 when one byte is read according to the embodiment.

[0043] Fig.17 1 is a diagram showing an example of the control signal 170 when 2-byte reading is performed according to the embodiment.

[0044] Fig.18 This is a diagram showing an example of a flowchart of the operation of the IC recognition unit 64 according to the embodiment. DETAILED DESCRIPTION

[0045] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, the combination of features described in the embodiments is not necessarily all essential to the solution of the invention.

[0046] Figure 1 1 is a diagram showing an example of a schematic diagram of a user terminal 100 having an imaging device 10 including a plurality of cameras 12a to 12c. In this specification, the plurality of cameras 12a to 12c and the like may be collectively referred to as a plurality of cameras 12 or cameras 12 and the like.

[0047] As an example, the user terminal 100 is a device including a camera 10 built into a smartphone, a tablet terminal, a notebook computer, a small computer, etc. As another example, the user terminal 100 may be a device including a camera 10 for capturing moving images, such as a digital camera, a web camera, or a video camera.

[0048] The plurality of cameras 12 have optical systems with different focal lengths and viewing angles. The respective imaging ranges of the plurality of cameras 12 overlap. Here, the camera 12a is, for example, an ultra-wide-angle camera having an optical system with a focal length of 13 mm or more and less than 16 mm, an f-number of 2.2 or more and less than 2.6, and a viewing angle of 110 degrees or more and less than 130 degrees. The camera 12b is, for example, a wide-angle camera (main camera) having an optical system with a focal length of 22 mm or more and less than 30 mm, and an f-number of 1.5 or more and less than 2.0. The camera 12c is, for example, a telephoto camera having an optical system with a focal length of 50 mm or more and less than 150 mm, and an f-number of 2.2 or more and less than 4.0.

[0049] The camera device 10 may output one image by synthesizing images captured by at least two cameras 12 among the plurality of cameras 12 .

[0050] The camera 12 has an image shake correction function. The camera 12 may have an optical image shake correction (OIS) function. Figure 2 The control of the optical system of the camera 12 in the OIS function will be described in detail.

[0051] Figure 1 The number of cameras 12 shown is an example, and the number of cameras 12 is not limited to three, and may be less than three, or may be four or more. In this case, for example, the imaging ranges of two or more cameras 12 overlap, or the imaging ranges of three or more cameras 12 overlap, or the imaging ranges of four or more cameras 12 overlap. The imaging device 10 only needs to include one or more cameras 12.

[0052] Here, the X-axis may be a direction extending in one direction of the end side of the user terminal 100 along a plane perpendicular to the optical axis (Z-axis) of each optical system of the plurality of cameras 12. The Y-axis may be a direction perpendicular to the X-axis and forming a right-handed system with respect to the positive direction of the X-axis along a plane perpendicular to the optical axis in the front and back of the user terminal 100. The Z-axis may be a direction intersecting the XY plane and forming a right-handed system with the XYZ axes.

[0053] Figure 21 is a diagram showing an example of the structure of cameras 12a to 12c. Camera 12a includes an optical system 120a, voice coil motors 121a and 123a, and IC chips 127a and 128a. Camera 12b includes an optical system 120b, voice coil motors 121b and 123b, and IC chips 127b and 128b. Camera 12c includes an optical system 120c, voice coil motors 121c and 123c, and IC chips 127c and 128c. Optical systems 120a to 120c include a plurality of lenses. The plurality of lenses can function as at least one of a zoom lens, a variable focal length lens, and a focus lens.

[0054] The voice coil motors 121a to 121c, 123a to 123c are driving mechanisms for driving the optical systems 120a to 120c along two axes, namely, the X-axis and the Y-axis, which are orthogonal to each other on a plane perpendicular to the optical axis, for realizing OIS. The voice coil motors 121a to 121c, 123a to 123c include air-core coils 122a to 122c and air-core coils 124a to 124c, and magnets that form pairs with each air-core coil. The IC chips 127a to 127c and the IC chips 128a to 128c can be respectively arranged in the air-core parts of the air-core coils 122a to 122c and the air-core coils 124a to 124c. In addition, in this specification, the voice coil motors 121a to 121c, 123a to 123c are sometimes collectively referred to as a plurality of voice coil motors 121, 123 or voice coil motors 121, 123, etc. The air-core coils 122a to 122c and the air-core coils 124a to 124c are sometimes collectively referred to as a plurality of air-core coils 122, 124 or air-core coils 122, 124, etc. The IC chips 127a to 127c and the IC chips 128a to 128c are sometimes collectively referred to as a plurality of IC chips 127, 128 or IC chips 127, 128, etc.

[0055] For example, a magnet is provided on a holding frame for holding the optical systems 120a to 120c, and hollow coils 122a to 122c and 124a to 124c are provided on bases 14a to 14c (sometimes collectively referred to as base 14) that support the holding frame in a manner that allows it to move on the XY plane. When the IC chips 127 and 128 allow current to flow through the hollow coils 122 and 124, a force is generated in the hollow coils 122 and 124 in a direction perpendicular to the magnetic field, and the holding frame moves relative to the base 14. Thus, OIS is achieved.

[0056] The cameras 12 a to 12 c drive at least one of the voice coil motors 121 and 123 to move the optical systems 120 a to 120 c in a direction to eliminate image blur.

[0057] As described above, the plurality of cameras 12 include the IC chips 127 and 128 for controlling the voice coil motors 121 and 123, respectively. Therefore, as the number of cameras 12 included in the imaging device 10 increases, the number of IC chips 127 and 128 increases.

[0058] Here, the imaging device 10 simulates and generates an image with a depth of field by synthesizing two images captured by two cameras with different focus positions (for example, a combination of camera 12a and camera 12b, a combination of camera 12b and camera 12c, or a combination of camera 12c and camera 12a). In this case, the two cameras 12 drive the optical system 120 by controlling the voice coil motors 121 and 123 via IC chips 127 and 128, thereby performing OIS.

[0059] Specifically, within the control range under the first imaging condition, the ultra-wide-angle camera 12a and the wide-angle camera 12b pass current to the voice coil motors 121 and 123 via the IC chips 127 and 129 to drive the optical systems 120a and 120b, thereby performing OIS. In addition, within the control range under the second imaging condition, the wide-angle camera 12b and the telephoto camera 12c pass current to the voice coil motors 121 and 123 via the IC chips 127 and 128 to drive the optical systems 120b and 120c, thereby performing OIS. That is, for one camera 12, two IC chips 127 and 128 control two voice coil motors 121 and 123, so in this example, four IC chips 127 and 128 may be controlled at once.

[0060] Figure 3 1 is a diagram showing an example of the structure of the substrates 16 and 26. The substrate 16 can be supported on the substrate 26 by means of an elastic body such as a spring or by means of a ball and a rail so as to be movable or rotatable relative to the substrate 26 along the XY plane. On the other hand, the substrate 26 can be fixed to the housing of the camera device 10 or the like. The substrate 16 has an image pickup element 18 and air-core coils 122d, 124d, and 126d, and the air-core coils 122d, 124d, and 126d constitute voice coil motors 121d, 123d, and 125d for realizing in-body image shake correction (BIS), in other words, for realizing sensor-shift optical image shake correction. In addition, the substrate 16 also includes a position sensor for detecting the position of the substrate 16. The camera device 10 includes an image pickup element 18 that forms an image via an optical system 120.

[0061] The substrate 26 is a substrate arranged along the Z-axis direction (depth direction) in the XYZ space relative to the substrate 16. A magnet 260d, a magnet 263d, and a magnet 266d are arranged on the substrate 26. The voice coil motors 121d, 123d, and 125d are composed of the hollow coils 122d, 124d, and 126d and the magnets 260d, 263d, and 266d. The substrate 26 includes magnets 260d, 263d, and 266d at positions facing the hollow coils 122d, 124d, and 126d. In the present embodiment, the substrate 16 has the hollow coils 122d, 124d, and 126d, and the substrate 26 has magnets 260d, 263d, and 266d. However, this is an example, and the substrate 16 may include the magnets 260d, 263d, and 266d, and the substrate 26 may include the air-core coils 122d, 124d, and 126d.

[0062] The substrate 16 includes an air-core coil 122d, an air-core coil 124d, an air-core coil 126d, and an IC chip 127d, an IC chip 128d, and an IC chip 129d on one side (the side on the negative side in the Z-axis direction in the example in the figure). The IC chips 127d, 128d, and 129d can be respectively arranged in the air-core parts of the air-core coils 122d, 124d, and 126d.

[0063] The voice coil motors 123d and 125d are driving mechanisms that apply a force along the Y-axis direction to the substrate 16. The voice coil motor 121d is a driving mechanism that applies a force along the X-axis direction to the substrate 16. When the voice coil motors 123d and 125d are driven so as to apply a force in the opposite direction (a combination of hollow arrows or a combination of black arrows in the figure) to the substrate 16 along the Y-axis direction, the substrate 16 is rotated.

[0064] Therefore, BIS is realized by driving the voice coil motors 123d, 125d, and 121d to rotate or translate the substrate 16 relative to the optical system 120. That is, the three IC chips 127d, 128d, and 129d are controlled to control BIS based on the substrate 16.

[0065] At least one of the cameras 12a to 12c may include such substrates 16 and 26. Thus, at least one camera can have both the OIS and BIS functions.

[0066] Alternatively, at least one of the cameras 12a to 12c may not include the voice coil motors 121 and 123 (corresponding to any one of the voice coil motors 121a to 121c and 123a to 123c) for driving the optical system 120, but may include the substrates 16 and 26. Therefore, the voice coil motors 123d, 125d, and 121d for driving the substrate 16 on which the imaging element 18 is mounted may be included. That is, at least one of the cameras may not include the OIS function but may include only the BIS function.

[0067] In addition, OIS or BIS can be realized by further moving the optical system 120a to 120c or the imaging element 18 disposed on the substrate 16 in the Z-axis direction. In this case, a further driving mechanism such as a voice coil motor is provided, but in this specification, a detailed description of the control in the Z-axis direction is omitted for simplicity.

[0068] Figure 4 An example of a communication system 200 for controlling a conventional IC chip configured in a master-slave configuration is shown. The communication system 200 is configured to include a master device 20 and a plurality of slave devices 22a to 22c. The master device 20 and the plurality of slave devices 22a to 22c are each an IC chip.

[0069] The master device 20 sends a control signal for controlling each slave device 22a to 22c. For example, the master device 20 and each slave device 22a to 22c communicate in an I2C communication mode. 2 C protocol) to carry out data communication of control signals. 2 In the C protocol, the master device 20 controls the slave devices 22a to 22c by sending a serial clock (SCL) signal and a serial data (SDA) signal.

[0070] The slave devices 22a to 22c are IC chips respectively provided in the voice coil motors 121, 123, and 125 to control the operation of the voice coil motors 121, 123, and 125. The slave devices 22a to 22c have different independent addresses so that the master device 20 can control each IC chip separately. In the example shown in the figure, the slave device 22a has an independent address AAh, the slave device 22b has an independent address BBh, and the slave device 22c has an independent address CCh.

[0071] The master device 20 specifies one of the slave devices 22a to 22c to be processed using the independent addresses AAh to CCh in the control signal, and then specifies the register address to be written to. The master device 20 also specifies the data to be written to the specified register address in the control signal. For details of the control signal sent by the master device 20, refer to Figure 5 and Figure 6 To describe in detail.

[0072] In the figure, three slave devices 22a to 22c are shown as the slave devices 22 included in the communication system 200, but the number of the slave devices 22a to 22c is not limited to three, and may be less than three or more than four. Figure 2 In the example of FIG. 1 , two IC chips are provided for each of the cameras 12a to 12c, so the communication system 200 has six slave devices 22, namely, slave devices 22a to 22f. Figure 2 A camera 12 and Figure 3 When the substrate 16 in FIG. 1 is used in combination, the communication system 200 includes five slave devices 22 , namely, slave devices 22 a to 22 e.

[0073] Figure 5 FIG. 2 shows an example of a control signal sent by the master device 20 to control six slave devices 22a to 22f. Figure 2 In the example shown in FIG. 1 , the master device 20 sends a control signal for controlling six slave devices 22a to 22f. The control signal shown in the figure is composed of bit strings 24a to 24f. The control signal in the example shown in the figure is a control signal for commanding the slave devices 22a to 22f to write data of 1 byte (8 bits) in length.

[0074] The bit string 24a is the part of the control signal for the first slave device 22a. In the bit string 24a, the first 8 bits specify the independent address of which slave device is to be controlled. The bit string 24a contains 1-bit data for the master device 20 to receive an acknowledgment response (ACK) from the slave device 22 assigned the specified independent address.

[0075] Next, the bit string 24a includes a register address specifying bit that specifies the write position of a bit in the register of the slave device 22a. After the register address specifying bit, the bit string 24a again includes 1-bit data for sending an acknowledgment response (ACK) from the slave device 22 to the master device 20.

[0076] Next, the bit string 24a includes an 8-bit data string that specifies the content of data to be written to the 1-byte (8-bit) register of the slave device 22a. The bit string 24a includes 1-bit data for an acknowledgment response (ACK) after the 8-bit data string.

[0077] As a result, the bit string 24a contains data with a total data length of 27 bits. In the case of controlling six slave devices 22, the bit strings 24b to 24f are followed by the bit string 24b for controlling the second slave device 22, the bit string 24c for controlling the third slave device 22, ..., etc. The bit strings 24b to 24f have the same length as the bit string 24a. Thus, the control signal for the command to write data of 1 byte (8 bits) length to the slave devices 22a to 22f has a data length of 27×6=162 bits.

[0078] When the slave devices 22a to 22f process such control signals, each of the slave devices 22a to 22f sometimes starts processing in the order in which the communication with itself from the master device 20 is terminated. Therefore, for example, when the control is performed to move the optical system 120 or the imaging element 18 from the current position to the target position in the XY plane, the control is sometimes performed in a manner in which the drive timings of the actuators controlled by the slave devices 22a to 22f are staggered. In such a case, the control of driving the actuator of the optical system 120 or the imaging element 18 in the X direction and the control of driving the actuator of the optical system 120 or the imaging element 18 in the Y direction are performed at different timings. As a result, the movement of the optical system 120 or the imaging element 18 from the current position to the target position is not a straight line movement connecting the current position and the target position, but a broken line movement, and the movement is sometimes not smooth.

[0079] Figure 6 FIG. 2 shows another example of a control signal sent by the master device 20 to control six slave devices 22a to 22f. Figure 2 In the example shown in FIG. 1 , the master device 20 sends a control signal for controlling six slave devices 22a to 22f. The control signal shown in the figure is composed of bit strings 28a to 28f. The control signal in the example shown in the figure is a control signal for commanding the slave devices 22a to 22f to write data of 2 bytes (16 bits) in length.

[0080] The bit string 28a is a portion of the control signal for the first slave device 22a. In the bit string 28a of the control signal, the first 8 bits specify an independent address representing an object of controlling the slave device. The bit string 28a contains 1-bit data for the master device 20 to receive an acknowledgment response (ACK) from the slave device 22 assigned the specified independent address.

[0081] Next, bit string 28a includes a register address specifying bit that specifies the write position for the bit in the register possessed by slave device 22a. Bit string 24a again includes 1-bit data for sending an acknowledgement response (ACK) from slave device 22 to master device 20 after the register address specifying bit.

[0082] Next, the bit string 28a includes an 8-bit data string that specifies the content of data to be written to the register of the slave device 22a. The bit string 28a includes 1-bit data for an acknowledgment response (ACK) again after the 8-bit data string.

[0083] exist Figure 6 In the example of , the bit string 28a also includes an 8-bit data string to be written to the register of the slave device 22a. The bit string 28a then includes 1-bit data for an acknowledgement response (ACK).

[0084] As a result, the bit string 28a contains data having a total data length of 36 bits. The bit strings 28b to 28f have the same length as the bit string 28a. Thus, the control signal for commanding the slave devices 22a to 22f to write data having a length of 2 bytes (16 bits) has a data length of 36×6=216 bits.

[0085] Thus, in the conventional communication system 200, when 1-byte data is communicated using the I2C protocol, a 162-bit control signal is communicated, and when 2-byte data is communicated, a 216-bit control signal is communicated. Such communication will oppress the communication bandwidth of the I2C communication line.

[0086] and Figure 5 Similarly, in the control signal of this example, the slave device 32 specified by the independent address independently performs the read / write operation of the bit specified by the register address specified bit. In the control signal, each bit string of the bit string 24a to 24f or the bit string 28a to 28f is continuously sent, and the individual slave device 22 sometimes starts the operation independently in the order in which the communication from the master device to itself is completed. Therefore, sometimes there is a time difference in the driving timing of the actuator, so that the operation of the optical system 120 or the imaging element 18 controlled by the slave devices 22a to 22c and the slave devices 22a to 22c becomes not smooth.

[0087] Figure 7 1 is a diagram showing an example of the configuration of a communication system for controlling the cameras 12a to 12c according to the present embodiment. The system is shown to include a master device 30, the cameras 12a to 12c, and other slave devices 34.

[0088] The camera 12a includes slave devices 32a and 32b and an imaging unit 40a. The operation of the imaging unit 40a is controlled by the slave devices 32a and 32b.

[0089] The imaging unit 40a includes an imaging element 44a that captures an image formed by the optical system 42a, and a driving unit 46a that drives at least one of the optical system 42a and the imaging element 44a. The driving unit 46a includes a voice coil motor composed of a combination of an air-core coil 460 and a magnet 462, and a voice coil motor composed of a combination of an air-core coil 464 and a magnet 466. The optical system 42, the imaging element 44, the air-core coils 460, 464, and the magnets 462, 466, etc. may be the same as the reference Figure 2 and Figure 3 The components described correspond to the components.

[0090] The hollow coil 460 and the magnet 462 of the driving unit 46 correspond to one of the directions (X direction and Y direction) in which the driving unit 46 drives the optical system 42 and the imaging element 44. The hollow coil 464 and the magnet 466 correspond to the other of the directions (X direction and Y direction) in which the driving unit 46 drives the optical system 42 and the imaging element 44.

[0091] Similarly, the camera 12b includes slave devices 32c and 32d and an imaging unit 40b. The camera 12c includes slave devices 32e and 32f and an imaging unit 40c. The imaging units 40b and 40c have the same structure as the imaging unit 40a.

[0092] As described above, the slave device 32 is provided in each of the plurality of imaging units 40. However, the slave device 32 may be provided at any position in the communication system as long as it is at a position capable of controlling the driving of either the optical system 42 or the imaging element 44.

[0093] As reference Figure 2 As described above, among the cameras 12a to 12c, when OIS control is performed on two cameras 12a and 12b, cameras 12b and 12c, or cameras 12c and 12a at once, four slave devices 32 are controlled. In this embodiment, such an embodiment will be described.

[0094] As reference Figure 3 As in the example described above, Figure 7 In the embodiment of the present invention, a substrate 16 is sometimes provided for one camera 12 to perform OIS and BIS control. In this case, two slave devices 32 (IC chips) are provided for OIS control of the camera 12, and three slave devices 32 (IC chips) are provided for BIS control on the substrate 16. In this way, a total of five slave devices 32 are controlled by the control signal of the master device 30.

[0095] The master device 30 controls the slave devices 32a to 32f and other slave devices 34. Specifically, the master device 30 controls the operation of the device by performing data communication of control signals based on serial clock (SCL) signals and serial data (SDA) signals with the slave devices 32a to 32f and other slave devices 34 via a bus. The master device 30 includes a communication unit 31 for performing data communication to send such control signals to the slave device 32 via a bus. In this way, a "communication system" including the master device 30, the slave devices 32a to 32f and other slave devices 34 is formed.

[0096] The slave devices 32a to 32f are devices that perform data communication with the master device 30 via the bus, and perform control based on a common address and an independent address based on a control signal output from the master device 30. In particular, the slave devices 32a and 32b control the electromagnetic actuator in the drive unit 46a, that is, the voice coil motor. In order to perform such control, a common address that is a "shared address" of multiple slave devices 32 and an independent address of each slave device 32 that uniquely identifies the multiple slave devices 32 are assigned to each slave device 32. The master device 30 can perform the ID and each setting of the slave device 32 with the independent address. The ID can be an index that can identify all the slave devices 32 with the same common address in ascending order. For example, when the same common address is assigned to six slave devices 32, the ID assigned to each of the six slave devices 32 can be any one of "ID1", "ID2", "ID3", "ID4", "ID5" and "ID6".

[0097] In this embodiment, similarly to the communication system 200, the slave devices 32a to 32f also communicate data with the master device 30 using the I2C communication method. The slave devices 32a to 32f are IC chips connected to the drivers 46a to 46c to control the operations of the drivers 46a to 46c.

[0098] The other slave device 34 is a device to which the master device 30 does not assign the common address assigned to the slave devices 32a to 32f. The other slave device 34 may have a common address different from that of the slave devices 32a to 32f (not shown). The other slave device 34 may have an independent address for being controlled by the master device 30 alone through a control signal. In the present embodiment, the other slave device 34 has an independent address: RRh.

[0099] Next, refer to Figure 8 The internal structure of each slave device 32 is described. Figure 8: is a diagram showing an example of the structure of the slave device 32. The slave device 32 includes input terminals 50, 52, a communication unit 60, a position sensor 70, an amplifier 72, an ADC 74 (ADC: Analog to Digital converter), an actuator driving unit 80, and output terminals 54, 56. Figure 7 The slave devices 32a to 32f shown have Figure 8 The internal structure of the slave device 32 is shown.

[0100] The slave device 32 controls the movement of the optical system 42 or the imaging element 44 to the target position based on the SCL signal input from the input terminal 50, the SDA signal input from the input terminal 52, and the position information of the magnet 462 or 466. To this end, the slave device 32 outputs a current of a desired magnitude from the output terminals 54, 56 to the air-core coil 460 or 464.

[0101] The communication unit 60 receives a control signal sent from the master device 30, and performs data communication with the master device 30 based on the control signal, so as to read out (read) or write in (write) data of a data length indicated by the data length information included in the control signal. In addition, an ID indicating a predetermined sequence may be uniquely assigned to the slave device 32, so that the communication unit 60 receives or sends data to or from the master device 30 in the predetermined sequence assigned to the slave devices 32a to 32f. The communication unit 60 includes a transceiver unit 62, an IC identification unit 64, an internal register 66, and a non-volatile memory 68.

[0102] The transceiver section 62 receives the SCL signal input from the input terminal 50 and the SDA signal input from the input terminal 52, and transmits a portion for identifying the common address or the individual address from the device 32 in the control signal to the IC identification section 64. In addition, the transceiver section 62 transmits data to be read from each internal register 66 or written to each internal register 66 to the internal register 66.

[0103] As the slave device 32 as the control object shown in the control signal, the IC identification unit 64 identifies whether the slave device 32 equipped with the IC identification unit 64 is the control object. Specifically, the IC identification unit 64 identifies whether a group of slave devices 32 with a common address may become the control object based on the part of the control signal sent by the transceiver unit 62 for identifying the common address or the independent address of the slave device 32. Or, the IC identification unit 64 identifies whether the slave device 32 with an independent address is the control object. In addition, when the IC identification unit 64 identifies that a group of slave devices 32 with a common address may become the control object, it identifies whether the slave device 32 is the control object according to the ID shown in the common address register 664 and the designated information contained in the control signal communicated from the master device 30. In addition, the IC identification unit 64 identifies the register address of the slave device 32 from which data should be read or written, the data length of the data, and the timing of access for reading or writing data according to the ID shown in the common address register 664 and the data length information contained in the control signal. The designated information and data length information contained in the control signal will be described in detail later.

[0104] The internal register 66 is a register for recording control information for the actuator driving unit 80 to control the electromagnetic actuator. The internal register 66 includes a target position register 660 , an operation mode register 662 , and a common address register 664 .

[0105] The target position register 660 is a register storing information on the target position of the actuator driving unit 80 driving the optical system 42 or the imaging element 44. The operation mode register 662 is a register storing information on the operation mode of the actuator driving unit 80 driving the optical system 42 or the imaging element 44.

[0106] The common address register 664 is a register indicating the common address and ID of the slave device 32. Therefore, the IC identification unit 64 can compare the common address bit indicated by the control signal with the value indicating the common address indicated by the common address register 664 to determine whether the slave device 32 belongs to the group of slave devices 32 that may become the control target in the control signal. In addition, the IC identification unit 64 refers to the designated information indicated by the control signal, specifically, the upper bit of the ADRS bit described later, and compares it with the ID of the common address register 664, thereby identifying the slave device 32 that is the control target communicating with the master device 30 this time. Moreover, when the IC identification unit 64 identifies that it is the slave device 32 that is the control target communicating with the master device 30 this time, it also identifies the timing of its own communication with the master device 30 according to the value indicating the ID indicated by the common address register 664 and the data length information, specifically, the information indicated by the lower bit of the ADRS bit described later. The common address register 664 functions as an "ID storage unit" for storing IDs uniquely assigned to each of a plurality of slave devices in a predetermined order.

[0107] The nonvolatile memory 68 is a memory for storing data of a larger capacity or data to be stored for a longer period of time, etc., for control information for the actuator driving unit 80 to control the electromagnetic actuator than the data stored in the internal register 66. The nonvolatile memory 68 is loaded in the slave device 32. The nonvolatile memory 68 may be a nonvolatile memory such as a flash memory.

[0108] The position sensor 70 detects the position of the magnet 462 or 466 based on the magnetic field around the magnet 462 or 466. For example, in particular, when the holding frame of the optical system 42 is provided with the magnet 462 or 466, the position sensor 70 detects the position of the optical system 42 by detecting the position of the magnet 462 or 466. The position sensor 70 is, for example, a magnetic sensor using a magnetic sensor element such as a Hall element, a TMR element using a tunnel magnetoresistance effect, or a GMR element using a giant magnetoresistance. The position sensor 70 outputs a voltage or current based on the detected magnetic field to the amplifier 72.

[0109] The amplifier 72 amplifies the voltage or current output from the position sensor 70 and outputs the amplified voltage or current to the ADC 74. The ADC 74 converts the voltage or current output from the amplifier 72 into a digital signal indicating the position information of the optical system 42 and outputs the digital signal to the actuator driver 80.

[0110] The actuator driving unit 80 supplies a voltage or current output from the output terminals 54 and 56 to drive the electromagnetic actuator, thereby controlling the current flowing through the air-core coil 460 or 464 constituting the electromagnetic actuator. Figure 2 and Figure 3 The voice coil motors mentioned in are examples of electromagnetic actuators. The actuator driving unit 80 includes a control unit 82 , a DAC 84 (DAC: Digital to Analog converter), a first driver 86 , and a second driver 88 .

[0111] The control unit 82 controls the current flowing in the air-core coil 460 or 464 constituting the electromagnetic actuator based on the control information indicated by the internal register 66 and the digital signal indicating the position information of the optical system 42 output from the ADC 74. The control unit 82 outputs the digital signal regarding the control information to control the current flowing in the air-core coil 460 or 464. The DAC 84 converts the digital signal output by the control unit 82 into an analog signal and outputs it to the first driver 86 or the second driver 88.

[0112] The first driver 86 and the second driver 88 supply voltage, current or power output from the output terminals 54 and 56 to the electromagnetic actuator according to the analog signal output from the DAC 84. The first driver 86 and the second driver 88 may be drivers for supplying currents of opposite polarities to the air-core coil 460 or 464.

[0113] In addition, refer to Fig. 9 The following figure illustrates the following situation: in the control signal when the master device 30 controls the slave device 32, the address information indicating the slave device 32 as the control target has a common address. However, the address information may also be as shown in FIG. Figure 5 and Figure 6 The control signal has independent address bits as described in the conventional art.

[0114] As such, in the case where the address information indicates an independent address, the control signal generated by the master device 30 may be as follows: Figure 5 and Figure 6 As in the example of , the register information includes register information indicating the register address of the slave device 32 from which the slave device 32 as the object of data communication should read (read) or write (write) data, corresponding to the independent address bit.

[0115] When the address information indicates the independent address of the slave device 32, the communication unit 60 performs data communication with the master device 30 by accessing the register address of the slave device 32 indicated by the register information to read out (read) or write in (write) data. Figures 4 to 6 The same processing is performed by the master device 20 and the slave device 22 shown in the communication system 200.

[0116] In this way, the master device 30 and the slave device 32 of the present embodiment can refer to Fig. 9 The processing using the common address bits and the reference Figures 4 to 6 In the master device 30 and the slave device 32 of the present embodiment, such processing can also be performed when it is desired to process an independent single slave device 32. In order to realize such processing, the master device 30 can generate and communicate corresponding control signals.

[0117] Fig. 9 An example of the control signal 90 according to the embodiment is shown. The control signal 90 is configured to include a common address bit 92, an ADRS bit 94, and data 96a to 96h.

[0118] The common address bit 92 is a bit for specifying a plurality of slave devices 32 that may be the object of communication with the master device 30 through one control signal. The common address bit 92 may be, for example, a bit for specifying a plurality of slave devices 32 that control the same control object such as the camera 10. In addition, the 1-bit length portion before the common address bit 92 indicates whether the slave device 32 should read (read) data or write (write) data. This 1-bit length portion corresponds to the "first bit".

[0119] The communication unit 60 determines whether the slave device 32 should read (read) data or write (write) data based on the value of the first bit. The common address bit 92 indicates an address shared by multiple slave devices. The address information is composed of the first bit and the common address bit 92. The communication unit 60 determines whether it is a group of slave devices 32 that may become the control object based on the comparison of the address information of the common address bit 92 and the common address stored in the common address register 664.

[0120] The ADRS bit 94 specifies at least one slave device 32 that is the target of data communication among the plurality of slave devices 32. The information specifying at least one slave device 32 in the information indicated by the ADRS bit 94 corresponds to "specified information". The communication unit 60 can determine the order of reading or writing its own data based on the ID assigned to each of the plurality of slave devices 32 and the specified information.

[0121] Furthermore, the ADRS bit 94 includes "data length information" indicating the register address of the internal register 66 to be accessed and the length of data received or sent from the device 32 specified by the specified information, in a portion other than the bit including the specified information.

[0122] When the communication unit 60 determines that it is a group of slave devices 32 that may become the control target based on the address information of the common address bit 92, it determines whether it is the slave device 32 that is the control target based on the designated information indicated by the ADRS bit 94 and its own ID. When the communication unit 60 determines that it is the slave device 32 that is the control target, it communicates with the master device 30 at a timing corresponding to the designated information, the data length information and its own ID to read or write data (one of the data 96a to 96h). Therefore, when the communication unit 60 is selected based on the designated information, it determines the order among the slave devices 32 selected from the plurality of slave devices 32 to read or write data of the data length indicated by the data length information from the register of the slave device 32 according to the ID of the slave device 32 provided with itself and the designated information indicated by the control signal, and performs data communication with the master device 30 at a timing corresponding to the order. On the other hand, when the communication unit 60 determines that it is not the slave device 32 that is the control target, it ignores the data 96a to 96h. Therefore, when the communication unit 60 itself is not selected according to the designated information, it is determined that it does not communicate with the master device 30. Thus, it is possible to cause specific slave devices 32 among a plurality of slave devices 32 having the same common address to act as control objects at the same time through one control signal 90. Moreover, even if there are slave devices 32 that are not control objects among the plurality of slave devices 32 having the same common address, the control signal 90 of the present embodiment does not need to include dummy data about the slave devices 32 that are not control objects. In addition, as will be described later, Fig.10 Let's describe ADRS bit 94.

[0123] In this way, the control target is specified for the combination of multiple slave devices 32 based on the address information and the designation information, and the data position to be read from or written into the internal register 66 is determined based on the data length information. The common address bit 92 and the ADRS bit 94 each include a 1-bit acknowledgement (ACK) bit, and the data 96a to 96h follow them.

[0124] The data 96a to 96h may be data for reading the internal data in the internal register 66 of each of the plurality of slave devices 32 and performing operation settings. Alternatively, the data 96a to 96h may be data for controlling the actuator driving unit 80. That is, the data 96a to 96h may be data for each of the plurality of slave devices 32 to control the driving unit 46 connected thereto according to the data 96a to 96h to drive at least one of the optical systems 42 and the imaging element 44.

[0125] In this embodiment, Figure 7There are six slave devices 32. Among the six IC chips, there are 15 combinations for operating two of them, 30 combinations for operating three of them, 15 combinations for operating four of them, 6 combinations for operating five of them, and 1 combination for operating six of them. Therefore, when controlling two to six IC chips, there are 57 combinations. Therefore, in order to express all these combinations, a 6-bit value is required.

[0126] Here, for example, six IC chips are set to IC1, IC2, IC3, IC4, IC5, and IC6, respectively. Moreover, when IC3=IC4, IC5=IC6 and two or more ICs among IC1 to IC6 are controlled, the number of combinations is 11. In this case, all modes for controlling more than two ICs can be included by a 4-bit value. In this embodiment, two pairs are formed for four IC chips from the six IC chips, and by controlling the IC chips included in the pair as if they were the same, the six IC chips can be controlled by the high bit of the 4-bit ADRS bit 94.

[0127] Fig.10 2 is a diagram showing an example of the structure of the ADRS bit 94. The 8-bit ADRS bit 94 includes, for example, 4 high-order bits 942 and 4 low-order bits 944.

[0128] In the upper bits 942 including the four bits ADRS[7] to ADRS[4], at least one slave device 32 to be the target of data communication among the plurality of slave devices 32 is assigned to each bit. The upper bits 942 correspond to the "first bit string".

[0129] When the upper bit 942 has a predetermined first value (e.g., 1), the communication unit 60 of the slave device 32 assigned to the bit determines that the slave device 32 is the object of data communication. On the other hand, when the upper bit 942 has a predetermined second value (e.g., 0), the communication unit 60 of the slave device 32 assigned to the bit determines that the slave device 32 is not the object of data communication.

[0130] The lower bits 944 of ADRS[3] to ADRS[0] include data length information corresponding to the register address and data length of the slave device 32 from which the slave device 32 should read (read) or write (write) data. The lower bits 944 correspond to the "second bit string".

[0131] The four bits ADRS[3] to ADRS[0] can take values ​​of 1 or 0, respectively. Therefore, as a pattern represented by the four bits ADRS[3] to ADRS[0], 16 states can be represented by each bit taking a different value. Through these 16 values, the lower bit 944 can represent 16 commands regarding the register address and data length of the slave device 32 from which data should be read (read) or written (written). For details about these 16 commands, refer to Fig.12 The control mapping is described in detail.

[0132] Fig.11 An example of a reference table showing combinations of control targets of the slave device 32 (IC chip) according to the embodiment is shown. The slave device 32 to be controlled is selected based on the values ​​of the upper bits 942 of the ADRS bits, namely, the four bits ADRS[7] to ADRS[4].

[0133] In this embodiment, when ADRS[7] shows a value of 1, IC1 becomes the control object, and when ADRS[7] shows a value of 0, IC1 does not become the control object. Similarly, when ADRS[6] shows a value of 1, IC1 becomes the control object, and when ADRS[6] shows a value of 0, IC1 does not become the control object.

[0134] If already referred to Fig. 9 As described above, control is performed such that the group of IC3 and IC4 is regarded as the same and the group of IC5 and IC6 is regarded as the same. When ADRS[5] shows a value of 1, the group of IC3 and IC4 is the control target, and when ADRS[5] shows a value of 0, the group of IC3 and IC4 is not the control target. Similarly, when ADRS[4] shows a value of 1, the group of IC5 and IC6 is the control target, and when ADRS[4] shows a value of 0, the group of IC5 and IC6 is not the control target.

[0135] For the predetermined value in the upper bit 942 of the ADRS bit, as the combination of the IC chip to be controlled, Fig.11 The reference table is only an example, and other combinations can also be used. For example, as IC1=IC2, IC3=IC4, the bits that control IC1 and IC2, the bits that control IC3 and IC4, the bits that control IC5, and the bits that control IC6 can be used. As a reference table for realizing the control of this embodiment, other reference tables can be used as long as it is a combination that can control six ICs with 4 bits.

[0136] Fig.12An example of a control map according to the embodiment is shown. ADRS[3:0], which is the lower bit 944 of the ADRS bit, can take values ​​from 0 to 15. In the control map, the control of the internal register 66 of the slave device 32 and its data length are shown according to the value taken by ADRS[3:0].

[0137] When ADRS[3:0] takes a value of 0, 1 byte is communicated at position 0 of the target position register 660 of the slave device 32. When ADRS[3:0] takes a value of 1, 1 byte is communicated at position 1 of the target position register 660 of the slave device 32. Position 1 in the target position register 660 may be a position continuous from position 0, or may be a position shifted by 1 byte from the position indicated by position 0. When ADRS[3:0] takes a value of 2, 1 byte is communicated at each of positions 0 and 1 of the continuous target position register 660 of the slave device 32, i.e., 2 bytes are communicated.

[0138] When ADRS[3:0] takes a value of 3, 1 byte communication is performed at the first position of the action mode register 662 of the slave device 32. When ADRS[3:0] takes a value of 4, 1 byte communication is performed at a second position different from the first position. The second position may be a position continuous from the first position, or may be a position shifted by 1 byte from the first position. When ADRS[3:0] takes a value of 5, 1 byte communication is performed at each of the first position and the second position of the action mode register 662 of the slave device 32, i.e., 2 bytes of communication are performed.

[0139] When ADRS[3:0] takes the value of 6, a predetermined action command is executed in the register at the third position in the action mode register 662 of the slave device 32. The action performed under this action command is a 1-byte communication. Regarding the case where ADRS[3:0] takes the value of 7 to 15, other predetermined action commands can also be determined. For these cases, the registers, register addresses, and data lengths accessed in the internal registers 66 of the slave device 32 can be shown in the control map.

[0140] The communication unit 60 refers to a control mapping such as the relationship between the data length information representing the lower bit 944 as the second bit string and the register address and data length of the slave device 32 from which the slave device 32 should read (read) or write (write) data. Thus, the IC identification unit 64 determines the register address and data length of the slave device 32 from which the slave device 32 should read (read) or write (write) data. In a case where the slave device 32 is the object of data communication, data of a data length determined based on the data length information is received or sent according to an ID representing a predetermined order and designated information by accessing the register address of the slave device 32 from which the slave device 32 should read (read) or write (write) data. In addition, Fig.12 The control map shown is an example of a “map” that indicates the relationship between the register address of the slave device 32 and the data length from which the slave device 32 should read or write data.

[0141] Fig.13 An example of the control signal 130 in the case of performing 1-byte writing according to the embodiment is shown. In the control signal 130, the first 8 bits of the common address bit 132 specify the group of slave devices 32 to be controlled.

[0142] Next, in the control signal 130, after the common address bit 132, the next 8-bit ADRS bit 134 is included in the form of an acknowledgment response (ACK) bit separated by 1 bit. The common address bit 132 specifies the group of slave devices 32 that may become the control object. In addition, the ADRS bit 134 is used to select the slave device 32 that is enabled as the control object, specify the register address of the internal register 66 that is the object of reading / writing, read / write the data corresponding to the command, and specify the length of the data to be read / written according to the command. Figure 5 In the example of , the control signal includes 8 independent address bits and 8 register address bits for specifying the slave devices 32 for six independent slave devices 32. In the control signal 130, the slave devices 32 and register addresses that are the processing targets of the command can be specified together by the 8 common address bits 32 and the 8 ADRS bits 134, so the bit string of the specified portion of the slave device 32 and the register address becomes shorter.

[0143] Then, the control signal 130 includes 8-bit data read / written from / to slave devices 32 of ID1 to ID6 with 1-bit ACK bit interposed therebetween. The total length of the bit string included in the control signal 130 is 72 bits.

[0144] In this way, by including the common address bit 132 and the ADRS bit 134, the control signal 130 indicating the process of selecting the slave device 32 and the length of data to be read or written, etc., for the slave devices 32 of ID1 to ID6 is simplified. Figure 5 Compared with the control signal written in 1 byte of 162 bits described above, the control signal becomes shorter. Therefore, in the control signal 130, the communication amount of the control content is saved.

[0145] An ID indicating a predetermined sequence is uniquely assigned so that the order in which the slave device 32 that is the control target among the slave devices 32a to 32f receives or sends data to the master device 30 can be identified. Based on the ID indicating the predetermined sequence and the designated information, the slave device 32 can determine whether it is the slave device 32 that is the control target and the timing of receiving or sending data to the master device 30.

[0146] Furthermore, each slave device 32 of the present embodiment starts operating at the same time (for example, simultaneously) when the communication of the control signal 130 is completed. Figure 5 In the example of control for moving the optical system 42 or the imaging element 44 from the current position to the target position in the XY plane, control is performed to align the drive timing of the actuators controlled by the slave devices 32a to 32f of the present embodiment. That is, in such a case, the control of driving the actuator of the optical system 42 or the imaging element 44 in the X direction and the control of driving the actuator of the optical system 42 or the imaging element 44 in the Y direction can be started at the same time. Thus, the movement of the optical system 42 or the imaging element 44 from the current position to the target position can be set to, for example, movement along a straight line connecting the current position and the target position. In this way, the movement of a driven object such as an optical system 42 or an imaging element 44 controlled by multiple slave devices 32 becomes smoother than when a common address is not used.

[0147] Fig.14 An example of the control signal 140 in the case of performing 2-byte writing according to the embodiment is shown. The control signal 140 also includes a common address bit 142, an ADRS bit 144, and an acknowledgment response (ACK) bit associated therewith, similarly to the control signal 130.

[0148] In the control signal 140, 2 bytes of data are written to the slave devices 32 of ID1 to ID6. Figure 6 Compared with the example, when writing 2 bytes of data to the six slave devices 32 of ID1 to ID6, Figure 6In the example of FIG. 1 , the slave device 32 to which data is to be written and the register address to which the data is to be written are specified by six 8-bit independent address bits and 8-bit register address bits.

[0149] On the other hand, in the control signal 140, in order to execute a command to multiple slave devices 32, the group of slave devices 32 indicated by the common address bit 142 may become the object of data writing. In addition, in the high bit 942 of the ADRS bit 144, whether the slave device 32 is the object of communication with the master device 30 (whether it is enabled) and the order of communication with the master device 30 are specified. The communication unit 60 refers to the ADRS bit 144 to identify the object of communication and the order of communication. In addition, in the data length information of the low bit 944 of the ADRS bit 144, the register address and data length predetermined for the command are specified. Thus, data is written to the internal register 66. In this way, in the control signal 140, by using the 8-bit common address bit 142 and the ADRS bit 144 respectively, it is not necessary to set the independent address bit and the register address bit one-to-one for the slave device 32.

[0150] The control signal 140 includes 2 bytes of data for writing to the slave devices 32 of ID1 to ID6 in addition to the common address bits 142 and the ADRS bits 144. Therefore, the total length of the bit string included in the control signal 140 is 126 bits.

[0151] In this way, by including the common address bit 142 and the ADRS bit 144, the control signal 140 indicating the processing of selecting the slave device 32 and the length of the data to be read or written for the slave devices 32 of ID1 to ID6 is compared with Figure 6 The 216-bit control signal shown in the figure is shortened and simplified. In addition, in each slave device 32 using the control signal 140, based on the ID read from the common address register 664 and the designation information and data length information of the slave device 32 as the control object shown in the ADRS bit 144, the slave device 32 that is the control object is determined among the multiple slave devices 32 that may be the control object, and the order in which the data is processed is determined. In addition, similar to the control signal 130, at the time point when the communication of the control signal 140 ends, the slave devices 32 start to operate together (for example, at the same time). As a result, the operation of the driven objects such as the optical system 42 or the camera element 44 controlled by the multiple slave devices 32 can be compared to Figure 6 The example is smoother.

[0152] Fig.15An example of the control signal 150 in the case of performing 2-byte writing according to the embodiment is shown. The control signal 150 also includes a common address bit 152, an ADRS bit 154, and an acknowledgment response (ACK) bit associated therewith, similarly to the control signals 130 and 140.

[0153] In the control signal 150, 2 bytes of data are written to the slave devices 32 of ID1, ID2, ID5, and ID6. The control signal 150 is a reference. Fig.10 and Fig.11 This is an example of a control signal based on the control when IC3=IC4 and IC5 and IC6 are set.

[0154] The example is in Fig.11 In the reference table corresponding to the ADRS bit, the high bits ADRS[7] to [4] of the ADRS bit 154 are ADRS[7]=1, ADRS[6]=1, ADRS[5]=0, and ADRS[4]=1. In this way, as the control signal 150, an example of the case where the high bits ADRS[7:4] of the ADRS bit 154=1101b are set is shown. In this way, some of the multiple slave devices 32 assigned the same common address can be set as the target, and data communication can be achieved between the master device 30 through one control signal 130.

[0155] Following the common address bit 152, ADRS bit 154 and their acknowledgement (ACK) bit, the control signal 150 includes 2 bytes of data (and an acknowledgement (ACK) bit) for writing to the slave devices 32 of ID1, ID2, ID5, and ID6. The total length of the bit string included in the control signal 150 is 90 bits.

[0156] In this way, by including the common address bit 152 and the ADRS bit 154, the control signal 150 indicating the processing of selecting the slave device 32 and the length of the data read or written for the slave devices 32 of ID1 to ID6 is simplified. In this case, the total length of the bit string included in the control signal 150 becomes larger than the control signal 140 relative to the reference bit 140. Figure 6 The control signal is shorter than the control signal for writing 2 bytes of 216 bits as described above.

[0157] The communication unit 60 determines whether it belongs to the group of slave devices 32 that may become the control target by using the common address indicated by the common address bit 152. Furthermore, the communication unit 60 identifies the slave device 32 that is the control target this time by comparing the value indicated by the upper bits ADRS [7] to [4] of the ADRS bit 154 with the ID of the common address register 664. In addition, the communication unit 60 identifies the order of data processing between the slave devices 32 that are the control targets this time based on the identification result of the slave device 32 that is the control target this time, its own ID read from the common address register 664, and the data length determined by the value indicated by the lower bits ADRS [3] to [0] of the ADRS bit 154. According to the correspondence between the common address bit 152 and the common address, it is possible to set the target position, etc. for multiple slave devices 32 by using the control signal 150 that is shorter than the case of using independent addresses.

[0158] Also, similarly to control signals 130 and 140, at the time when communication of control signal 150 is completed, slave devices 32 start operating simultaneously (e.g., simultaneously). Thus, based on control signal 150, slave device 32 can also smoothly control a driven object such as optical system 42 or imaging element 44.

[0159] The ID of the slave device 32 enabled as the control object shown in the ADRS bit 154 may not be all IDs with the same common address. In the slave device 32 of the present embodiment, the slave devices 32 of ID1, ID2, ID5, and ID6 are enabled. Based on the ID stored in the common address register 664 and the specified information of the ADRS bit 154, the communication unit 60 that determines that it is not the slave device 32 as the control object ignores the data after the confirmation response bit after the ADRS bit 154. Like this, by using the common address, ID and the specified information in combination, the freedom of the slave device 32 that can be specified is increased compared to the case where only the common address is used. In addition, the communication unit 60 that determines that it is not the slave device 32 as the control object ignores the data after the confirmation response bit after the ADRS bit 154, and the control signal 150 does not need to include virtual data for the slave device 32 outside the selection. Therefore, in the present embodiment, it is possible to avoid oppressing the communication band in the I2C communication method due to virtual data.

[0160] Furthermore, in the control signal 150 of the present embodiment, the timing and data length of accessing the internal register 66 of the slave device 32 as the object are determined based on the ID stored in the common address register 664, the designated information indicated by the ADRS bit 154, and the data length information. As in the present embodiment, when the slave devices 32 of ID1, ID2, ID5, and ID6 are enabled, the communication unit 60 of the slave devices 32 of ID1, ID2, ID5, and ID6 can access the internal register 66, and recognize the timing and data length of data communication with the master device 30 based on the ID, the designated information, and the data length information. When the communication unit 60 is the slave device 32 as the control object, it waits until the timing of data communication with the master device 30. Therefore, in the control signal 150, the communication unit 60 of the slave device 32 as the control object can access the internal register 66 at an appropriate timing and communicate data of an appropriate data length with the master device 30. As described above, in the present embodiment, the slave device 32 can recognize the timing and data length at which communication should be performed with the master device 30 and perform communication, so that the communication volume and communication time between the master device 30 and the slave device 32 can be reduced.

[0161] Fig.16 An example of the control signal 160 for performing 1-byte reading according to the embodiment is shown. In the control signal 160, the first bit included is a bit indicating writing or reading, and when reading, the first bit also specifies writing.

[0162] Next, the control signal 160 includes 8-bit common address bits 162. The control signal 160 includes an ADRS bit 164 with an acknowledgment (ACK) bit interposed therebetween.

[0163] In the control signal 160, Fig.15 Similarly, in the example Fig.11 In the reference table corresponding to the ADRS bit, the high bits ADRS[7] to [4] are ADRS[7]=1, ADRS[6]=1, ADRS[5]=0, and ADRS[4]=1. As such, as the control signal 160, an example is shown in which the high bit ADRS[7:4]=1101b of the ADRS bit 164 is set. Therefore, in the control signal 160, one byte of the slave device 32 of ID1, ID2, ID5, and ID6 is read. When data is read, the control signal 160 includes a bit indicating read in the bits indicating write or read, and then includes a common address bit 166. The control signal 160 includes an acknowledgment response (ACK) bit after the common address bit 166, and then includes a bit string indicating data 168a~168d regarding data 1 to data 4 that are actually read.

[0164] As with the control signal in the case of data writing, the overall length of the control signal 160 of this embodiment is greater than that based on Figure 3 The data length of the control signal for data reading in the conventional communication system 200 is short.

[0165] Fig.17 An example of the control signal 170 in the case of performing 2-byte reading according to the embodiment is shown. In the control signal 170, the first bit included is a bit indicating writing or reading, and the first bit specifies writing.

[0166] Next, the control signal 170 includes 8-bit common address bits 172. The control signal 170 includes an ADRS bit 174 with an acknowledgment (ACK) bit interposed therebetween.

[0167] In the control signal 170, Fig.15 and Fig.16 Similarly, in the example Fig.11 In the reference table corresponding to the ADRS bit, the high bits ADRS[7] to [4] are ADRS[7]=1, ADRS[6]=1, ADRS[5]=0, and ADRS[4]=1. As such, as the control signal 170, an example is shown in which the high bits ADRS[7:4]=1101b of the ADRS bit 174 are set. Therefore, in the control signal 170, 2 bytes of the slave devices 32 of ID1, ID2, ID5, and ID6 are read. When data is read, the control signal 170 includes a bit indicating read in the bits indicating write or read, and then includes a common address bit 176. After the common address bit 176, an acknowledgment response (ACK) bit is included, and then a bit string of data 178a~178h indicating data 1 to data 8 actually read is included.

[0168] As with the control signal in the case of data writing, the overall length of the control signal 170 of this embodiment is relatively large compared to that based on Figure 3 The data length of the control signal for data reading in the conventional communication system 200 is shortened.

[0169] According to the slave device 32 configured as described above, the communication unit 60 confirms that the common address of the address information is consistent with the common address register 664 set in the internal register 66, and determines whether it should read or write data based on the first bit indicated by the address information. The communication unit 60 refers to the upper bit 942 of the ADRS bit 94 and the Fig.11942, to determine whether it is assigned to the bit with "1" in the upper bit 942. In addition, when the address information indicates a common address and the slave device is assigned to the bit with "1" in the upper bit 942, the communication unit 60 determines that it is the object of data communication. In addition, the communication unit 60 determines that it is the object of data communication by referring to the lower bit 944 of the ADRS bit 94 and the bit with "1" in the upper bit 942. Fig.12 The control mapping shown is used to determine the register address and data length of the slave device 32 that should read or write data corresponding to the data length information of the lower bit 944.

[0170] On the other hand, when the communication unit 60 is assigned to a bit having "0" in the upper bit 942, it determines that it is not the object of data communication. Then, when it is the object of data communication, the communication unit 60 receives or transmits data of a data length determined based on the correspondence between the data length information indicated by the lower bit 944 and the control map in the order determined by the ID read from the common address register 664 and the designation information indicating the slave device 32 as the control object indicated by the ADRS bit 94.

[0171] Fig.18 An example of a flowchart of the operation of the IC recognition unit 64 according to the embodiment is shown. The operation performed by the IC recognition unit 64 is configured to include steps S100 to S134.

[0172] The slave device 32 receives the communication data including the control signal from the master device 30 (step S100). Specifically, the transceiver 62 in the communication unit 60 can receive the communication data from the input terminals 50 and 52. The transceiver 62 transmits the portion of the control signal indicating whether the slave device 32 is the control target to the IC identification unit 64.

[0173] Next, in this embodiment, the processing steps S110 to S134 performed by the IC recognition unit 64 are described. The IC recognition unit 64 reads the common address and ID of the slave device 32 from the internal register 66. The IC recognition unit 64 compares the common address bit with the common address read from the common address register 664 based on the part of the control signal indicating whether the slave device 32 is the control object (step S110). If the comparison result shows that the contents are consistent, the process proceeds to step S112, and if the contents are inconsistent, the process proceeds to step S118.

[0174] Next, the IC identification unit 64 determines whether to perform a read process or a write process on the internal register 66 in the slave device 32 based on the bit indicating which process is to be performed between the read (R) process and the write (W) process shown before the common address bit (step S112). Next, the IC identification unit 64 compares the (enabled) bit (equivalent to the enable signal) indicating the IC to be controlled shown by the ADRS bit with the ID shown in the common address register 664 to verify whether they are consistent (step S114). If the comparison result is that the contents are consistent, the process proceeds to step S116, and if the contents are inconsistent, the process proceeds to step S118.

[0175] In step S110 or step S114, if the comparison result is not consistent ("No"), the IC recognition unit 64 returns a negative response (NACK) in the identification of whether it is the slave device 32 to be controlled (step S118). At the same time as the negative response (NACK) of the IC recognition unit 64, the processing of the slave device 32 in the control signal of the communication data communicated in step S100 is completed. Therefore, if the communication unit 60 itself is not selected according to the designation information in the control signal, the communication unit 60 does not perform data communication with the master device 30.

[0176] Then, the IC recognition unit 64 refers to Fig.11 The reference table shown in FIG. 1 is used to determine the IDs of all slave devices 32 that are the objects of data communication in this control signal. The IC identification unit 64 arranges all the determined IDs in ascending order to determine the order of its own IDs shown in the internal register 66, thereby determining the order in which the slave devices 32 are controlled (step S116). On the other hand, the IC identification unit 64 reads the data length information from the lower bits of the ADRS bit, and compares the content of the data length information with the control map (step S120).

[0177] Thus, the IC recognition unit 64 determines the register address to be accessed in the register (step S122). The information about the register address to be accessed in the register is used in step S134. In addition, the IC recognition unit 64 determines the data length to be processed in the register for the register address to be accessed (step S124). The information about the data length is used in step S126.

[0178] The IC identification unit 64 adds up the order in which the slave device 32 is controlled and the data length processed on the register (step S126). When the order of the slave device 32 is set to N, the IC identification unit 64 calculates (N-1)×data length (data order). For example, if the order of the slave device 32 is "3", the IC identification unit 64 adds the two data lengths (calculates 2×data length). Thus, the IC identification unit 64 can determine the selected slave device 32 as the object or the order and timing of data processing under the clock indicated by the clock signal of the slave device 32 being processed, that is, the order of data processing (data order) and the timing corresponding to the order (step S128). In the case of read processing, the IC identification unit 64 recognizes that: after the ACK following the ADRS bit 94, wait for an amount corresponding to (N-1)×data length (data order) to access the designated register in the slave device 32 to read data. In the case of write processing, the IC identification unit 64 recognizes that after the ACK following the common address bits 166 and 176 whose first bits are designated to be written, it waits for an amount corresponding to (N-1)×data length (data order) and accesses the designated register in the slave device 32 to write data.

[0179] The IC identification unit 64 counts the number of data under the clock through a counter (not shown), and compares whether the number of data is consistent with the data sequence (step S130). If the number of data reaches the data sequence of the processing object, the process proceeds to step S134, and if the number of data does not reach the data sequence of the processing object, the process proceeds to step S132.

[0180] When the number of data does not reach the data sequence of the processing target, the IC recognition unit 64 waits (step S132), and again proceeds to the process of comparing whether the number of data matches the data sequence (step S130).

[0181] When the number of data reaches the data sequence of the processing target, the IC identification unit 64 accesses the register of the target register address of the slave device 32 based on the information of the register address to be accessed in the register, and performs a read process or a write process of the data of the byte length specified by the data length determined in step S124 (step S134). Thus, the control information to be used in the actuator driving unit 80 is processed.

[0182] Through the above processing, the operation of the IC identification unit 64 is realized. Thus, the data communication method in this embodiment is realized. Therefore, multiple ICs are set as control objects at the same time, and the signal length of the control signal is shortened, so that the operation of the IC identification unit 64 that can support the control signal that can prevent the pressure of the communication band is realized.

[0183] The present invention has been described above using the embodiments, but the protection scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that the modes to which such changes or improvements are made can also be included in the protection scope of the present invention.

[0184] It should be noted that the execution order of each process such as actions, processes, steps and stages in the device, system, program and method shown in the claims, specifications and drawings can be implemented in any order as long as there is no special indication of "before...", "prior to", etc. and the output of the previous process is not used in the subsequent process. Even if the action flow in the claims, specifications and drawings is described using "first", "next", etc. for convenience, it does not mean that it must be implemented in this order.

[0185] Description of Reference Numerals

[0186] 10: camera device; 12: camera; 14: base (substrate); 16, 26: substrate; 18, 44: camera element; 20, 30: master device; 22, 32: slave device; 24, 28: bit string; 31, 60: communication unit; 34: other slave devices; 40: camera unit; 42, 120: optical system; 46: drive unit; 50, 52: input terminal; 54, 56: output terminal; 62: transceiver unit; 64: IC recognition unit; 66: internal register; 68: non-volatile memory; 70: position sensor; 72: amplifier; 74: ADC; 80: actuator drive unit; 82: control unit; 84: DAC; 86: first driver; 88: second driver; 90, 130, 140: 40, 150, 160, 170: control signal; 92, 132, 142, 152, 162, 166, 172, 176: shared address bit; 94, 134, 144, 154, 164, 174: ADRS bit; 96, 168, 178: data; 100: user terminal; 121, 123, 125: voice coil motor; 122, 124, 126, 460, 464: air-core coil; 127, 128, 129: IC chip; 200: communication system; 260, 263, 266, 462, 466: magnet; 660: target position register; 662: action mode register; 664: shared address register; 942: high bit; 944: low bit.

Claims

1. A slave device that communicates data with a master device via a bus, wherein the slave device is characterized in that: An ID storage unit that stores an ID uniquely assigned in a predetermined order to each of the plurality of slave devices; and A communication unit that receives a control signal sent from the master device, the control signal including address information indicating an address shared by the plurality of slave devices, designation information that specifies at least one slave device among the plurality of slave devices that is the object of data communication, and data length information indicating the length of data received or sent by the slave device specified by the designation information in a predetermined order, wherein the communication unit determines not to communicate with the master device when it is not selected according to the designation information, and when it is selected according to the designation information, determines the order among the selected slave devices among the plurality of slave devices to read data of the data length indicated by the data length information from a register of the slave device or write data to a register of the slave device according to the ID and the designation information, and performs data communication with the master device at a timing corresponding to the order.

2. The slave device according to claim 1, characterized in that: Each of the plurality of slave devices is uniquely assigned a predetermined order, The designation information has a first bit string, and at least one slave device that is the target of data communication among the plurality of slave devices is assigned to each bit of the first bit string. When the slave device is assigned to the bit having the first value in the first bit string, the communication unit receives or transmits data of the data length indicated by the data length information in accordance with the predetermined order and the designation information, When the slave device is assigned to the bit having the second value in the first bit string, the communication unit determines that the slave device is not a target of data communication.

3. The slave device according to claim 1, characterized in that: The address information includes a first bit indicating whether the slave device should read data or write data. The communication unit determines whether the slave device should read data or write data based on the first bit.

4. The slave device according to claim 1, characterized in that: The data length information has a second bit string corresponding to the register address of the slave device to which the slave device should read or write data and the data length, The communication unit determines the register address and data length of the slave device to be read or written by the slave device corresponding to the second bit string included in the data length information by referring to a mapping indicating the relationship between the second bit string and the register address and data length of the slave device to be read or written by the slave device, When the slave device is the object of data communication, the communication unit receives or sends data of the data length indicated by the data length information in accordance with the predetermined order and the designated information by accessing the register address of the slave device from which the slave device should read or write data.

5. The slave device according to claim 1, characterized in that: Each of the plurality of slave devices is uniquely assigned a predetermined order, The address information includes a first bit indicating whether the slave device should read data or write data. The designation information has a first bit string, and at least one slave device that is the target of data communication among the plurality of slave devices is assigned to each bit of the first bit string. The data length information has a second bit string corresponding to the register address of the slave device to which the slave device should read or write data and the data length, The communication unit determines whether the slave device should read data from the register or write data to the register based on the first bit, When the address information indicates the common address and the slave device is assigned to a bit having a first value in the first bit string, the communication unit determines that the slave device is a target of data communication, When the address information indicates the common address and the slave device is assigned to the bit having the second value in the first bit string, the communication unit determines that the slave device is not a target of data communication, In a case where the slave device is the object of data communication, the communication unit determines the register address and data length of the slave device to which the slave device should read or write data corresponding to the second bit string included in the data length information by referring to a mapping representing the relationship between the second bit string and the register address and data length of the slave device to which the slave device should read or write data, When the slave device is the object of data communication, the communication unit receives or sends data of the data length indicated by the data length information in accordance with the predetermined order and the designated information by accessing the register address of the slave device from which the slave device should read or write data.

6. The slave device according to claim 1, characterized in that: The address information indicates the common address or an independent address uniquely identifying each slave device among the plurality of slave devices, In the case where the address information indicates the independent address, the control signal includes, instead of the designation information and the data length information, register information indicating a register address of the slave device corresponding to the independent address from which the slave device as the object of data communication should read or write data, When the address information indicates the independent address of the slave device, the communication unit performs data communication with the master device to read or write data by accessing the register address of the slave device indicated by the register information.

7. The slave device according to claim 1, characterized in that: The slave device performs data communication with the master device via I2C communication.

8. The slave device according to claim 1, characterized in that: The slave device is an integrated circuit chip.

9. A communication system, characterized in that: have: A plurality of slave devices according to claim 1; and The master device sends the control signal to the plurality of slave devices via the bus.

10. A camera device, characterized in that: have: The communication system according to claim 9; and a plurality of imaging units, each of which has an optical system, an imaging element, and a driving unit, wherein the imaging element captures an image formed by the optical system, and the driving unit drives at least one of the optical system and the imaging element, Each of the plurality of slave devices drives at least one of the optical system and the imaging element by controlling the driving unit according to the data.

11. A camera device, characterized in that: have: The communication system according to claim 9; and An imaging unit includes an optical system, an imaging element, and a driving unit, wherein the imaging element captures an image formed by the optical system, and the driving unit drives at least one of the optical system and the imaging element. Each of the plurality of slave devices drives at least one of the optical system and the imaging element by controlling the driving unit according to the data.

12. A master device that performs data communication with a plurality of slave devices via a bus, wherein the master device is characterized in that: A communication unit is provided, which performs data communication with at least one slave device among the multiple slave devices that is the object of data communication by sending a control signal to the multiple slave devices via the bus, wherein the control signal includes address information indicating an address shared by the multiple slave devices, designation information specifying at least one slave device among the multiple slave devices that is the object of data communication, and data length information indicating the length of data received or sent by the slave device specified by the designation information in a predetermined order.

13. A data communication method, wherein data communication is performed between a master device and a plurality of slave devices via a bus, wherein the data communication method is characterized in that: The following phases are included: A slave device among the plurality of slave devices receives a control signal from the master device, the control signal including address information indicating an address shared by the plurality of slave devices, designation information designating at least one slave device among the plurality of slave devices to be a target of data communication, and data length information indicating a length of data received or transmitted in a predetermined order by the slave device designated by the designation information; as well as When the slave device itself is not selected according to the designated information, data communication is not performed with the master device. When the slave device is designated as the object of data communication according to the designated information, the slave device performs data communication with the master device based on the ID of the slave device and the control signal, so as to read data of the data length indicated by the data length information from the register of the slave device or write data to the register of the slave device in accordance with the predetermined order and the designated information.

14. The data communication method according to claim 13, characterized in that: Each of the plurality of slave devices is uniquely assigned a predetermined order, The designation information has a first bit string, and at least one slave device that is the target of data communication among the plurality of slave devices is assigned to each bit of the first bit string. The data communication method further comprises the following stages: receiving or transmitting data of a data length indicated by the data length information in accordance with the predetermined order and the designation information, in a case where the slave device is assigned to a bit having a first value in the first bit string; as well as In a case where the slave device is assigned to the bit having the second value in the first bit string, it is determined that the slave device is not a target of data communication.

15. The data communication method according to claim 13, characterized in that: The address information includes a first bit indicating whether the slave device should read data or write data. The data communication method further comprises the following stage: judging, based on the first bit, whether the slave device should read data or write data.

16. The data communication method according to claim 13, characterized in that: The data length information has a second bit string corresponding to the register address of the slave device to which the slave device should read or write data and the data length, The data communication method further comprises the following stages: Determine the register address and data length of the slave device corresponding to the second bit string and at which the slave device should read or write data, by referring to a mapping representing the relationship between the second bit string and the register address and data length of the slave device at which the slave device should read or write data; as well as When the slave device is the object of data communication, data of the data length indicated by the data length information is received or sent in accordance with the predetermined order and the designated information by accessing the register address of the slave device from which the slave device should read or write data.

17. The data communication method according to claim 13, characterized in that: Each of the plurality of slave devices is uniquely assigned a predetermined order, The address information includes a first bit indicating whether the slave device should read data or write data. The designation information has a first bit string, and at least one slave device that is the target of data communication among the plurality of slave devices is assigned to each bit of the first bit string. The data length information has a second bit string corresponding to the register address of the slave device to which the slave device should read or write data and the data length, The data communication method further comprises the following stages: Based on the first bit, determining whether the slave device should read data from the register or write data to the register; When the address information indicates the common address and the slave device is assigned to a bit having a first value in the first bit string, determining that the slave device is a target of data communication; When the address information indicates the common address and the slave device is assigned to the bit having the second value in the first bit string, determining that the slave device is not a target of data communication; In a case where the slave device is an object of data communication, determining the register address and data length of the slave device to which the slave device should read or write data corresponding to the second bit string included in the data length information by referring to a mapping indicating the relationship between the second bit string and the register address and data length of the slave device to which the slave device should read or write data; as well as When the slave device is the object of data communication, data of the data length indicated by the data length information is received or sent in accordance with the predetermined order and the designated information by accessing the register address of the slave device from which the slave device should read or write data.

18. The data communication method according to claim 13, characterized in that: The address information indicates the common address or an independent address uniquely identifying each slave device among the plurality of slave devices, In the case where the address information indicates the independent address, the control signal includes, instead of the designation information and the data length information, register information indicating a register address of the slave device corresponding to the independent address from which the slave device as the object of data communication should read or write data, The data communication method further includes the following stage: when the independent address of the slave device is indicated in the address information, data communication is performed with the master device to read or write data by accessing the register address of the slave device indicated by the register information.

19. The data communication method according to claim 13, characterized in that: The slave device performs data communication with the master device via I2C communication.

20. The data communication method according to claim 13, characterized in that: The slave device is an integrated circuit chip.

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