Wiring board

Abstract

The quality of the wiring substrate is improved. A wiring board according to an embodiment has a first surface (1F) and a second surface (1B), and includes: a first stacked portion (10) having a first surface and including first conductor layers (12), first insulating layers (11), and first via conductors (13) that are alternately stacked; a third laminated part (30) having a third conductor layer (32), a third insulating layer (31), and a third via conductor (33), which are alternately laminated, and having a second surface; and a second build-up section (20) that is disposed between the first build-up section and the third build-up section, and that includes a second conductor layer (22) and a second insulating layer (21) that are alternately stacked, and a second via conductor (23) that penetrates the second insulating layer. The diameter of the first via hole conductor is smaller than that of the second via hole conductor, the diameter of the second via hole conductor is smaller than that of the third via hole conductor, and the second lamination part comprises a plurality of second insulating layers and a plurality of second conductor layers.

Description

Technical Field

[0001] The present invention relates to a wiring substrate. Background Art

[0002] Patent document 1 discloses a coreless substrate having a first surface and a second surface opposite to the first surface. The coreless substrate includes a plurality of (three) insulating layers. Vias are formed in the three insulating layers, penetrating the insulating layers and electrically connecting wiring arranged above and below the insulating layers. The sizes (diameter and height) of the vias penetrating different insulating layers among the three insulating layers are different. The size of the via increases for each insulating layer from the via formed in the insulating layer on the first surface side toward the via formed in the insulating layer on the second surface side.

[0003] Patent Document 1: International Publication No. 2010 / 010910

[0004] In the coreless substrate disclosed in Patent Document 1, the size of the via hole formed in each insulating layer is different. It is considered that there are cases where the structure of the circuit that can be formed through the via hole of the same size is relatively limited. Summary of the invention

[0005] The wiring substrate of the present invention has a first surface and a second surface on the opposite side to the first surface, and includes: a first build-up portion including alternately stacked first conductor layers and first insulating layers and a first via-hole conductor penetrating the first insulating layer, the first build-up portion having the first surface; a third build-up portion including alternately stacked third conductor layers and third insulating layers and a third via-hole conductor penetrating the third insulating layer, the third build-up portion having the second surface; and a second build-up portion disposed between the first build-up portion and the third build-up portion, including alternately stacked second conductor layers and second insulating layers and a second via-hole conductor penetrating the second insulating layer. The diameter of the first via-hole conductor is smaller than the diameter of the second via-hole conductor, the diameter of the second via-hole conductor is smaller than the diameter of the third via-hole conductor, and the second build-up portion includes a plurality of the second insulating layers and a plurality of the second conductor layers.

[0006] According to the embodiment of the present invention, it is possible to provide a high-quality wiring substrate having a wiring circuit having a relatively complex structure with relatively stable characteristic impedance by passing through via-hole conductors of similar size (diameter). BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a cross-sectional view showing an example of a wiring substrate according to an embodiment of the present invention.

[0008] Figure 2AThis is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0009] Figure 2B This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0010] Figure 2C This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0011] Figure 2D This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0012] Figure 2E This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0013] Figure 2F This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0014] Figure 2G This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0015] Figure 2H This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0016] Fig.2I This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0017] Figure 2J This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0018] Figure 2K This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0019] Figure 2L This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0020] Figure 2M This is a diagram showing an example of a method for manufacturing a wiring board as one embodiment of the present invention.

[0021] Description of symbols

[0022] 1: wiring substrate; 10: first build-up portion; 20: second build-up portion; 30: third build-up portion; 11: insulating layer (first insulating layer); 21: insulating layer (second insulating layer); 31: insulating layer (third insulating layer); 12: conductor layer (first conductor layer); 22: conductor layer (second conductor layer); 32: conductor layer (third conductor layer); 13: via conductor (first via conductor); 23: via conductor (second via conductor); 33: via conductor (third via conductor); 12p, 32p: conductor pads; FW: wiring; E1, E2: electronic components; GS: supporting substrate; EA1, EA2: component mounting areas. DETAILED DESCRIPTION

[0023] A wiring substrate according to one embodiment will be described with reference to the drawings. Figure 1 1 is a cross-sectional view showing a wiring substrate 1 as an example of a wiring substrate according to an embodiment. The wiring substrate 1 is merely an example of a wiring substrate according to this embodiment. The stacked structure of the wiring substrate according to this embodiment and the number of conductor layers and insulating layers are not limited to Figure 1 The stacked structure of the wiring substrate 1 and the number of conductor layers and insulating layers included in the wiring substrate 1 are shown. In addition, the referenced drawings are not intended to show the exact ratio of each component, but are depicted in a manner that makes it easy to understand the characteristics of the present invention.

[0024] The wiring substrate 1 of the embodiment has a laminated structure including a first laminated portion 10, a second laminated portion 20, and a third laminated portion 30 each consisting of a plurality of conductor layers and insulating layers laminated alternately. The wiring substrate 1 has two surfaces (a first surface 1F and a second surface 1B on the opposite side to the first surface 1F) perpendicular to its thickness direction.

[0025] The first laminated part 10 has one surface 10F and another surface 10B opposite to the one surface 10F. The second laminated part 20 has one surface 20F and another surface 20B opposite to the one surface 20F. The third laminated part 30 has one surface 30F and another surface 30B opposite to the one surface 30F. Figure 1 As shown, one surface 10F of the first build-up part 10 constitutes the first surface 1F. The second surface 1B is constituted by the other surface 30B of the third build-up part 30.

[0026] In the example shown in the figure, second build-up section 20 is arranged below first build-up section 10 so that one surface 20F of second build-up section 20 faces another surface 10B of first build-up section 10. Third build-up section 30 is arranged below second build-up section 20 so that one surface 30F of third build-up section 30 faces another surface 20B of second build-up section 20.

[0027] In addition, Figure 1 In the description of the wiring substrate 1 of the present embodiment shown, one surface 10F of the first build-up portion 10, that is, the first surface 1F side of the wiring substrate 1 is referred to as "upper" or "upper side", and the second surface 1B side of the wiring substrate 1 is referred to as "lower" or "lower side". In addition, among the various components, the surface of the wiring substrate 1 facing the first surface 1F side is also referred to as the "upper surface", and the surface of the wiring substrate 1 facing the second surface 1B side is also referred to as the "lower surface".

[0028] In the example shown in the figure, the first build-up part 10, the second build-up part 20, and the third build-up part 30 include a plurality of insulating layers and a plurality of conductor layers, respectively. In the wiring substrate of the embodiment, at least the second build-up part 20 includes a plurality of insulating layers and a plurality of conductor layers. Specifically, in the example shown in the figure, the first build-up part 10 includes 4 first insulating layers 11 and 4 first conductor layers 12, the second build-up part 20 includes 7 second insulating layers 21 and 7 second conductor layers 22, and the third build-up part 30 includes 2 third insulating layers 31 and 3 third conductor layers 32. That is, an example is shown in which the number of layers of the second insulating layer 21 is greater than the number of layers of the first insulating layer 11, and the number of layers of the second conductor layer 22 is greater than the number of layers of the first conductor layer 12.

[0029] As shown in the figure, the first build-up portion 10 has an insulating layer (first insulating layer) 11 and a conductor layer (first conductor layer) 12 that are alternately stacked. The conductor layers that are opposite to each other (conductor layers 12 to each other, or conductor layer 12 and conductor layer 22) are connected by a via conductor (first via conductor) 13 with one insulating layer 11 interposed therebetween. The second build-up portion 20 has an insulating layer (second insulating layer) 21 and a conductor layer (second conductor layer) 22 that are alternately stacked. The conductor layers that are opposite to each other (conductor layers 22 to each other, conductor layer 12 and conductor layer 22, or conductor layer 22 and conductor layer 32) are connected by a via conductor (first via conductor) 23 with one insulating layer 21 interposed therebetween. The third build-up portion 30 has an insulating layer (third insulating layer) 31 and a conductor layer (third conductor layer) 32 that are alternately stacked. Conductive layers facing each other (conductive layers 32 , or conductive layer 22 and conductive layer 32 ) with one insulating layer 31 interposed therebetween are connected by via-hole conductors (third via-hole conductors) 33 .

[0030] The first via-hole conductor 13 included in the first build-up portion 10, the second via-hole conductor 23 included in the second build-up portion 20, and the third via-hole conductor 33 included in the third build-up portion 30 have different sizes. Specifically, the diameter of the first via-hole conductor 13, the diameter of the second via-hole conductor 23, and the diameter of the third via-hole conductor 33 are different, and the diameter of the first via-hole conductor 13 is smaller than the diameter of the second via-hole conductor 23, and the diameter of the second via-hole conductor 23 is smaller than the diameter of the third via-hole conductor 33. In addition, the "diameter" in the description of the via-hole conductors 13, 23, and 33 refers to the distance between the two longest points on the outer periphery in the cross section along the horizontal direction (the extension direction of the insulating layers 11, 21, and 31). The shape of the horizontal cross section of the via-hole conductors 13, 23, and 33 is not necessarily limited to a circle, and can have any shape such as a circle, an ellipse, and a rectangle when viewed from above.

[0031] In particular, regarding the diameters of the via-hole conductors 13, 23, and 33, “the diameter of the first via-hole conductor 13 is smaller than the diameter of the second via-hole conductor 23” means that the maximum value of the diameter at the upper surface of the lower conductor layer (conductor layer 12 or conductor layer 22) of the first via-hole conductor 13 connected to the first via-hole conductor 13 in the first build-up portion 10 is smaller than the minimum value of the diameter at the upper surface of the lower conductor layer (conductor layer 22 or conductor layer 32) of the second via-hole conductor 23 connected to the second via-hole conductor 23 in the second build-up portion 20. In addition, “the diameter of the second via-hole conductor 23 is smaller than the diameter of the third via-hole conductor 33” means that the maximum value of the diameter at the upper surface of the lower conductor layer (conductor layer 22 or conductor layer 32) of the second via-hole conductor 23 connected to the second via-hole conductor 23 in the second build-up portion 20 is smaller than the minimum value of the diameter at the upper surface of the lower conductor layer 33 of the third via-hole conductor 33 connected to the third via-hole conductor 33 in the third build-up portion 30.

[0032] As described above, in the wiring substrate of the embodiment, there are a plurality of build-up parts (first build-up part 10, second build-up part 20, and third build-up part 30) each including via conductors of different diameters, and at least the second build-up part 20 includes a plurality of insulating layers 21 and a plurality of conductor layers 22. The wiring substrate of the embodiment has a plurality of build-up parts, each of which has via conductors of different diameters, so that a wiring circuit having a relatively stable characteristic impedance and passing through the via conductor can be formed in each build-up part. Furthermore, by at least one of the build-up parts including a plurality of insulating layers and a plurality of conductor layers, a more complex wiring circuit can be formed in each build-up part. For example, it is also possible to form a stripline structure wiring in a build-up part including a plurality of insulating layers and a plurality of conductor layers. In addition, the diameter of the first via conductor 13 on the upper surface of the lower conductor layer to which the first via conductor 13 is connected is about 10 μm. The diameter of the second via conductor 23 on the upper surface of the lower conductor layer to which the second via conductor 23 is connected is about 50 μm. The diameter of the third via-hole conductor 33 on the upper surface of the lower conductor layer to which the third via-hole conductor 33 is connected is approximately 100 μm.

[0033] One surface 10F of the first build-up portion 10 is formed by the upper surfaces of the uppermost first insulating layer 11 and the conductive layer 12 in the first build-up portion 10. The other surface 10B of the first build-up portion 10 is formed by the lower surface of the lowermost insulating layer 11 in the first build-up portion 10. One surface 20F of the second build-up portion 20 is formed by the upper surfaces of the uppermost second insulating layer 21 and the conductive layer 22 in the second build-up portion 20. The other surface 20B of the second build-up portion 20 is formed by the lower surface of the lowermost insulating layer 21 in the second build-up portion 20. One surface 30F of the third build-up portion 30 is formed by the upper surfaces of the uppermost third insulating layer 31 and the conductive layer 32 in the third build-up portion 30. The other surface 30B of the third build-up portion 30 is formed by the lower surface of the lowermost insulating layer 31 in the third build-up portion 30.

[0034] In addition, the conductor layer 22 constituting one surface 20F of the second build-up portion 20 and the via-hole conductor 13 formed on the lowermost insulating layer 11 of the first build-up portion 10 are formed integrally. Of the via-hole conductor 13 and the conductor layer 22 formed integrally, the layer corresponding to the lower surface of the insulating layer 11 constituting the other surface 10B of the first build-up portion 10 is regarded as the boundary between the first build-up portion 10 and the second build-up portion 20. That is, the layer corresponding to the lower surface of the insulating layer 11 constituting the other surface 10B of the first build-up portion 10 (the layer corresponding to the upper surface of the conductor layer 22 constituting one surface 20F of the second build-up portion 20) corresponds to the boundary between the via-hole conductor 13 and the conductor layer 22. In addition, the conductor layer 32 constituting one surface 30F of the third build-up portion 30 and the via-hole conductor 23 formed on the lowermost insulating layer 21 of the second build-up portion 20 are formed integrally. In the integrally formed via-hole conductor 23 and conductor layer 32, the layer corresponding to the lower surface of the insulating layer 21 constituting the other surface 20B of the second laminated portion 20 (the layer corresponding to the upper surface of the conductor layer 32 constituting the one surface 30F of the third laminated portion 30) is regarded as the boundary between the second laminated portion 20 and the third laminated portion 30.

[0035] Each conductor layer 12 is patterned to have a predetermined conductor pattern. The first conductor layer 12 constituting the first build-up portion 10 includes relatively fine wiring (first wiring) FW, and can have a relatively high-density circuit wiring. In the illustrated example, the conductor layer 12 constituting one surface 10F is formed into a pattern having a plurality of conductor pads 12p. The conductor pad 12p is the outermost surface of the wiring substrate 1, and constitutes a component mounting surface of the wiring substrate 1 that can be connected to external electronic components. The component mounting surface of the wiring substrate 1 can have a plurality of component mounting areas. For example, Figure 1 As shown in the example of , two component mounting areas (EA1, EA2) can be formed corresponding to the areas where the electronic components E1, E2 are to be mounted.

[0036] In the example shown in the figure, when the external electronic component is mounted on the wiring substrate 1, the upper surface of the exposed conductor pad 12p can be electrically and mechanically connected to the external electronic component via a conductive bonding material (not shown) such as solder between the connection pads of the external electronic component. At this time, a plating layer (not shown) such as a nickel layer and a tin layer can also be formed in advance on the upper surface of the conductor pad 12p.

[0037] When a plurality of component mounting regions are formed, a conductor pattern that allows conductor pads 12p located in different component mounting regions to be electrically connected to each other can be formed in conductor layer 12 in first build-up portion 10. A plurality of electronic components mounted during use of wiring substrate 1 can be electrically connected to each other via conductor layer 12 of first build-up portion 10 in a short path. In addition, this can improve the degree of freedom of circuit design via a plurality of electronic components that can be mounted during use of wiring substrate 1.

[0038] Examples of the electronic components E1 and E2 that can be mounted on the wiring substrate 1 include electronic components such as active components such as semiconductor integrated circuit devices and transistors. Specifically, for example, they may be integrated circuits such as logic chips in which logic circuits are assembled, processing devices such as MPUs (Micro Processor Units), and memory elements such as HBMs (High Bandwidth Memory).

[0039] The first insulating layer 11 of the first laminated part 10 can be formed of insulating resins such as epoxy resin and phenolic resin. The insulating layer 11 can include any one of fluororesin, liquid crystal polymer (LCP), polytetrafluoroethylene resin (PTFE), polyester resin (PE), and modified polyimide resin (MPI). The conductors constituting the conductor layer 12 and the via conductor 13 can be copper, nickel, etc., and copper is preferably used. Figure 1 In the example shown, the conductor layer 12 and the via conductor 13 are shown as a single layer, but the conductor layer 12 and the via conductor 13 may also be configured as a multilayer structure. For example, the conductor layer 12 and the via conductor 13 may include a metal film layer 121 (see Figure 2G ) and a plated film layer 122 which can be, for example, an electroplated film layer (see Figure 2G ) has a two-layer structure.

[0040] The via conductor 13 that connects the conductor layers 12 that face each other across the insulating layer 11 is formed by filling the through hole 11a that penetrates the insulating layer 11 with a conductor. Figure 1 In the example shown in FIG. 1 , the via-hole conductor 13 is formed integrally with the conductor layer 12 provided thereunder. The via-hole conductor 13 formed in the lowermost insulating layer 11 shown in the figure is formed integrally with the conductor layer 22 .

[0041] The through hole 11a for forming the via conductor 13 can be formed by irradiating a laser beam at a position of the insulating layer 11 where the via conductor 13 is formed, for example, from the surface side of the lower side of each insulating layer 11. The diameter of the formed through hole 11a is large on the side irradiated with the laser beam and small on the side opposite to the side irradiated with the laser beam (the inner side). Therefore, the through hole 11a can be formed so that the diameter is large on the lower side and small on the upper side. Figure 1As shown, each via conductor 13 included in the first build-up portion 10 is formed into a tapered shape that decreases in diameter from the second surface 10B of the first build-up portion 10 toward the first surface 10F. In addition, "reduced in diameter" only means that the distance between the two longest points on the outer periphery in the horizontal cross section of the via conductor 13 becomes smaller. For example, the through hole 11a can be formed so that the aspect ratio of the via conductor 13 (the shortest distance from the upper surface of the lower conductor layer connected to the via conductor 13 to the lower surface of the upper conductor layer / the diameter of the via conductor 13 on the upper surface of the lower conductor layer) is about 0.5 or more and 1.0 or less.

[0042] The conductor layer 12 of the wiring substrate 1 can have a high-density wiring (first wiring) FW with a relatively small pattern width and a relatively small distance between patterns. The wiring FW can have the smallest pattern width and the smallest distance between patterns among the wirings constituting the wiring substrate 1. In the example shown in the figure, three conductor layers 12 among the plurality of conductor layers 12 included in the first build-up portion 10 have the wiring FW as the high-density wiring. However, the number of conductor layers 12 including the wiring FW included in the first build-up portion 10 is not limited.

[0043] Wiring (first wiring) FW included in first build-up portion 10 may have a pattern width smaller than the minimum value of the pattern width of wiring included in conductor layer 22 (second conductor layer 22) in second build-up portion 20 and conductor layer 32 (third conductor layer 32) in third build-up portion 30. In addition, wiring (first wiring) FW included in first build-up portion 10 may have a pattern distance smaller than the minimum value of the pattern distance of wiring included in conductor layer 22 (second conductor layer 22) in second build-up portion 20 and conductor layer 32 (third conductor layer 32) in third build-up portion 30. Specifically, for example, the wiring width of wiring FW is 3 μm or less, and the spacing between wirings is 3 μm or less. By providing first build-up portion 10 with relatively fine wiring FW, wiring having more appropriate characteristics corresponding to the electrical signal that can be transmitted by the wiring in first build-up portion 10 may be provided. In addition, from the same viewpoint, the aspect ratio of conductor layer 12 having wiring FW may be set to, for example, 2.0 or more and 4.0 or less. Furthermore, the conductor pattern that electrically connects the conductor pads 12p located in different component mounting regions described above can be formed of the wiring FW.

[0044] When the conductor layer 12 is formed to include the wiring FW formed at the fine pitch and aspect ratio as described above, it is sometimes preferable that the via conductor 13 is also formed at a fine pitch. It is necessary to form a through hole 11a with a small diameter for the via conductor 13 in the insulating layer 11. Therefore, the insulating layer 11 may contain an inorganic filler such as fine particles composed of silicon dioxide (SiO2), aluminum oxide, or mullite, but in order to easily form the through hole 11a with a small diameter, it is sometimes preferable that the insulating layer 11 does not contain an inorganic filler.

[0045] In the first build-up part 10 including the conductor layer 12 including the wiring FW, the thickness of the insulating layer 11 is, for example, about 7 μm to 10 μm. In this case, the insulating layer 11 preferably does not include a core material (reinforcement material) made of glass fiber, aramid fiber, etc. The thickness of the conductor layer 12 is, for example, 7 μm or less.

[0046] The insulating layer 21 constituting the second laminated portion 20 and the insulating layer 31 constituting the third laminated portion 30 can be formed using the same insulating resin as the insulating layer 11. Each insulating layer 11, 21, 31 can contain the same insulating resin in each laminated portion, or can contain different insulating resins from each other. Each insulating layer 21, 31 can also contain a core material (reinforcement material) composed of glass fiber or aramid fiber. In the example shown in the figure, the insulating layer 31 of the third laminated portion 30 contains a core material 31b composed of glass fiber, for example. Each insulating layer 21, 31 sometimes also contains an inorganic filler (not shown) composed of fine particles such as silica (SiO2), alumina or mullite.

[0047] The conductor layer 22 of the second build-up portion 20 and the conductor layer 32 of the third build-up portion 30 and the via-hole conductors 23 and 33 can be formed using any metal such as copper or nickel, similarly to the conductor layer 12 and the via-hole conductor 13. Figure 1 As shown, each via-hole conductor 23 included in second build-up portion 20 and each via-hole conductor 33 included in third build-up portion 30 are formed into a tapered shape with a diameter decreasing from second surface 1B side toward first surface 1F side of wiring substrate 1 , similarly to via-hole conductor 13 of first build-up portion 10 .

[0048] As described above, the pattern width and the distance between patterns of the wiring included in the conductor layer 22 of the second build-up portion 20 and the conductor layer 32 of the third build-up portion 30 are larger than the pattern width and the distance between patterns of the wiring included in the conductor layer 12 of the first build-up portion 10. The thickness of the conductor layer 22 is formed thicker than the thickness of the conductor layer 12, for example, about 10μm to 15μm. For example, the minimum value of the wiring width of the wiring included in the conductor layer 22 is about 4μm to 10μm, and the minimum value of the spacing between the wiring is about 6μm to 15μm. In the second build-up portion 20, the thickness of the insulating layer 21 is, for example, about 20μm to 30μm.

[0049] exist Figure 1In the wiring substrate 1 of the example shown, the thickness of the insulating layer 31 of the third build-up part 30 is greater than the thickness of the insulating layer 11 of the first build-up part 10, and greater than the thickness of the insulating layer 21 of the second build-up part 20. The thickness of the conductor layer 32 of the third build-up part 30 is greater than the thickness of the conductor layer 12 of the first build-up part 10, and greater than the thickness of the conductor layer 22 of the second build-up part 20. For example, the thickness of the insulating layer 31 is about 100 μm or more and 200 μm or less. Therefore, in the case of the example shown in the figure, the total thickness of the insulating layer 31 in the third build-up part 30 (specifically, the shortest distance between the upper surface of the insulating layer 31 constituting one surface 30F and the lower surface of the insulating layer 31 constituting the other surface 30B) can be 200 μm or more. In addition, the thickness of the conductor layer 32 can be about 20 μm.

[0050] Similar to the conductor layer 12 and the via conductor 13, the conductor layers 22, 32 and the via conductors 23, 33 are sometimes composed of a multilayer structure, for example, they can have a two-layer structure including a metal film layer which can be a sputtered film layer or a chemically plated film layer and a plated film layer which can be, for example, an electroplated film layer.

[0051] exist Figure 1 In the example of FIG. 1 , the wiring substrate 1 further includes a solder resist layer 41 formed on the second surface 1B formed by the surfaces of the insulating layer 31 and the conductor layer 32. The solder resist layer 41 is formed using, for example, a photosensitive polyimide resin or epoxy resin. An opening 41a is formed in the solder resist layer 41, and the conductor pad 32p of the conductor layer 32 of the third build-up portion 30 is exposed from the opening 41a.

[0052] Furthermore, when the wiring substrate 1 itself is mounted on an external element such as an external wiring substrate (for example, a motherboard of any electrical device), the second surface 1B of the wiring substrate 1 opposite to the first surface 1F, which is a component mounting surface of the wiring substrate 1, can be a connection surface connected to the external element. The conductor pad 32p can be connected to any substrate, electrical component, or mechanical component.

[0053] The wiring substrate 1 of the embodiment is preferably configured as a coreless wiring substrate that does not include a core layer. The second build-up portion 20 is arranged between the first build-up portion 10 and the third build-up portion 30. In the example shown in the figure, the first build-up portion 10, the second build-up portion 20, and the third build-up portion 30 are stacked continuously. However, there may be a case where a further build-up portion including an insulating layer and a conductor layer exists between the first build-up portion 10 and the second build-up portion 20, or between the second build-up portion 20 and the third build-up portion 30.

[0054] Next, refer to Figure 2A to Figure 2M , to manufacture Figure 1The manufacturing method of the wiring substrate of the embodiment is described by taking the case of the wiring substrate 1 shown in FIG. 1 as an example. In addition, each structural element formed in the manufacturing method described below can be used in any other embodiment unless otherwise specified. Figure 1 In the description of the wiring substrate 1, the material exemplified as the material of the corresponding structural element is formed. In the description of the manufacturing of the wiring substrate 1, the side close to the support substrate GS is referred to as "lower" or "lower side", and the side away from the support substrate GS is referred to as "upper" or "upper side". Therefore, the surface of each element constituting the wiring substrate 1 facing the support substrate GS side is also referred to as the "lower surface", and the surface facing the side opposite to the support substrate GS is also referred to as the "upper surface".

[0055] Wiring substrate 1 can be formed by manufacturing first build-up portion 10 on supporting substrate GS, manufacturing second build-up portion 20 on first build-up portion 10, and manufacturing third build-up portion 30 on second build-up portion 20 (see Figure 1 ).

[0056] In addition, in the following, Figure 2A to Figure 2M In Figure 2A to Figure 2J In each conductor layer, the metal film layer and the electroplating film layer, which are structural elements of each conductor layer, are separated and depicted as two layers, but in Figure 2K to Figure 2M In the example, each conductor layer is Figure 1 Likewise depicted in a single layer.

[0057] First, if Figure 2A As shown, a support substrate GS having good surface flatness, such as a glass substrate, is prepared. On the surfaces of both sides of the support substrate GS, a metal film layer 121 is formed via an adhesive layer AL containing an azobenzene-based polymer adhesive that can be attached or detached by light irradiation. The metal film layer 121 is, for example, a metal film (preferably a copper film) layer formed by chemical plating or sputtering. The metal film layer 121 can be composed of a relatively thin metal foil.

[0058] Then, if Figure 2B As shown, the conductor layer 12 including a plurality of conductor pads 12 p including a metal film layer 121 and a plated film layer 122 is formed on the support substrate GS via an adhesive layer AL.

[0059] In forming the conductor layer 12, for example, a plating resist is formed on the metal film layer 121, and an opening corresponding to the formation area of ​​the pattern of the conductor pad 12p is formed on the plating resist by, for example, photolithography. Then, by electroplating using the metal film layer 121 as a seed layer, a plated film layer 122 is formed in the opening. After the plated film layer 122 is formed, the plating resist is removed, and the metal film layer 121 exposed by removing the plating resist is etched to form a Figure 2B Status shown.

[0060] Then, if Figure 2C As shown, an insulating layer 11 covering the conductor layer 12 is stacked. As the insulating layer 11, for example, an insulating resin such as epoxy resin or phenolic resin can be used. Fluorine resin, liquid crystal polymer (LCP), polyvinyl fluoride resin (PTFE), polyester resin (PE), or modified polyimide resin (MPI) can also be used. The insulating layer 11 is formed by thermally pressing these resins formed into a film. Next, the via conductor 13 (see FIG. 1 ) in the insulating layer 11 is formed. Figure 1 ) is formed by irradiating a through hole 11a by, for example, a carbon dioxide laser or an excimer laser. The laser is irradiated from the upper side of the insulating layer 11. The through hole 11a formed can be formed so that its diameter decreases from the upper side to the lower side in the figure. The through hole 11a formed can be formed so that the diameter of the upper surface of the insulating layer 11 is about 10 μm.

[0061] Although not shown in the figure, the formation of the through hole 11a based on the irradiation of laser such as carbon dioxide laser can be performed by covering the surface of the insulating layer 11 with a protective film such as polyethylene terephthalate (PET) film for protection while irradiating the laser. The through hole 11a that penetrates the protective film and the insulating layer 11 is formed. In addition, after the through hole 11a is formed, in order to prevent the decrease in the adhesion during the formation of the conductor layer 12 caused by the processing modified product generated at the bottom of the through hole 11, a desmear treatment can be performed. The desmear treatment is preferably a dry desmear treatment using plasma gas. The desmear treatment can also be performed while protecting the surface of the insulating layer 11 in a state where a protective film such as polyethylene terephthalate (PET) film is formed on the surface of the insulating layer 11.

[0062] In addition, Figure 2C And the following references Figure 2D to Figure 2M In the figure, the laminate formed on one surface of the support substrate GS is shown, and the laminate that can be formed on the surface on the opposite side is omitted. However, the surface on the opposite side may also be formed with the same form and number of laminates, or with a conductor layer and an insulating layer of a form and number different from those on one surface, or may not be formed.

[0063] Then, if Figure 2D As shown, a metal film layer 121 is formed on the inner wall of the through hole 11a and the surface of the insulating layer 11 by chemical plating or sputtering. In addition, when a protective film is provided on the surface of the insulating layer 11 during the formation of the through hole 11a and / or the desmear treatment, the protective film can be stripped and removed before the metal film layer 121 is formed.

[0064] Then, if Figure 2EAs shown, a metal film layer 121 is provided with a conductive layer 12 (see Figure 2H ) includes a plating resist R1 having an opening R11 corresponding to the conductor pattern included therein.

[0065] Then, if Figure 2F As shown, by electroplating the metal film layer 121 as a power supply layer, a plated film layer 122 is formed in the opening R11 of the plating resist R1.

[0066] Then, if Figure 2G As shown, after the plating resist R1 is removed, the portion of the metal film layer 121 not covered by the plated film layer 122 is removed by etching or the like. As a result, the conductor layer 12 having the wiring FW and having a two-layer structure composed of the metal film layer 121 and the plated film layer 122 is formed. In addition, the inside of the through hole 11a is completely filled with the conductor constituting the plated film layer 122, thereby forming the via conductor 13. For example, the thickness of the conductor layer 12 can be formed to be about 7 μm or less.

[0067] Then, if Figure 2H As shown, a desired number of insulating layers 11 and conductive layers 12 and via-conductors 13 penetrating through the insulating layers 11 are formed by the same method as the above-mentioned method of forming the insulating layers 11 , conductive layers 12 , and via-conductors 13 .

[0068] Then, if Fig.2I As shown, a first build-up portion 10 is formed on the upper side of the conductor layer 12 (see Figure 2J ) of the outermost insulating layer 11 of the insulating layer 11. Then, by laser processing, the via conductor 13 (refer to Figure 1 ) is formed in the insulating layer 11 at a position corresponding to the formation position of the via-hole conductor 13.

[0069] Then, if Figure 2J As shown, the conductor layer 22 is formed simultaneously with the via conductor 13 filling the through hole 11a by using any conductor pattern forming method such as the semi-additive method. The first build-up portion 10 having a plurality of first insulating layers 11, first conductor layers 12, and first via conductors 13 is formed, and one surface 20F constituting the second build-up portion 20 (see Figure 1 ) is formed as a second conductor layer 22.

[0070] Then, if Figure 2KAs shown, the desired multiple insulating layers 21 and conductor layers 22 and via-hole conductors 23 filling through-holes 21a penetrating each insulating layer 21 are further formed by the same method as the method for forming the uppermost insulating layer 11, via-hole conductors 13, and conductor layer 22 in the first laminated portion 10. The formed through-holes 21a are formed so that the diameter of the upper surface of the insulating layer 21 has a value at least larger than the diameter of the upper surface of the insulating layer 11 of the through-holes 11a. The through-holes 21a can be formed so that the diameter of the upper surface of the insulating layer 21 is about 50 μm. On the formed uppermost insulating layer 21, a conductor layer 32 is formed simultaneously with the via-hole conductors 23 filling through-holes 21a. The formation of the second laminated portion 20 on the first laminated portion 10 and the formation of one surface 30F of the third laminated portion 30 (see Figure 1 ) is formed as a conductor layer 32.

[0071] Then, if Figure 2L As shown, an insulating layer 31, a conductor layer 32, and a via conductor 33 filling a through hole 31a penetrating the insulating layer 31 are further formed on the outermost insulating layer 21 and the conductor layer 32 of the second build-up part 20. The insulating layer 31, the conductor layer 32, and the via conductor 33 are formed by the same method as the method of forming the insulating layer 21, the conductor layer 32, and the via conductor 23. As the insulating resin forming the insulating layer 31, a prepreg containing an insulating resin such as epoxy resin, BT resin, etc. impregnated in a reinforcing material (core material) 31b composed of glass fiber can be used. As shown in the figure, a third build-up part 30 including two layers of insulating layers 31 and three layers of conductor layers 32 can be formed. For example, the insulating layer 31 can be formed to have a thickness of about 100 μm or more and about 200 μm or less, and its total thickness (in the example shown in the figure, the total thickness of the two layers of insulating layers 31) is 200 μm or more. Through hole 31a is formed so that the diameter of the upper surface of insulating layer 31 is at least larger than the diameter of through hole 21a of insulating layer 21. Through hole 31a can be formed so that the diameter of the upper surface of insulating layer 31 is about 100 μm.

[0072] Next, a solder resist layer 41 is formed by forming a photosensitive epoxy resin or polyimide resin layer on the surface of the insulating layer 31 and the conductive layer 32. Then, the opening 41a defining the conductive pad 32p is formed by photolithography.

[0073] Then, if Figure 2M As shown, the support substrate GS is removed. The lower surface of the conductor pad 12p and the lower surface of the insulating layer 11 are exposed. In the removal of the support substrate GS, after the adhesive layer AL is irradiated with, for example, laser light to soften it, the support substrate GS is peeled off from the conductor pad 12p and the insulating layer 11. In addition, the adhesive layer AL that may remain on the surface of the conductor pad 12p and the insulating layer 11 can be removed by cleaning. Completion Figure 1 The wiring substrate 1 is shown.

[0074] The wiring substrate of the embodiment is not limited to the structures illustrated in the drawings and the structures, shapes and materials illustrated in this specification. Each buildup portion included in the wiring substrate of the embodiment can have any number of insulating layers and conductive layers. For example, there may be a case where the insulating layer 31 constituting the third buildup portion 30 does not include the core material 31b. There may be a case where the thickness of the insulating layer 31 constituting the third buildup portion 30 is smaller than the thickness of the insulating layer 21 in the second buildup portion. There may be a case where the thickness of the conductive layer 32 constituting the third buildup portion 30 is smaller than the thickness of the conductive layer 22 in the second buildup portion.

Claims

1. A wiring substrate comprising a first surface and a second surface opposite to the first surface, The wiring substrate comprises: a first build-up portion including first conductor layers and first insulating layers that are alternately stacked and a first via conductor that penetrates the first insulating layer, the first build-up portion having the first surface; a third build-up portion including third conductor layers and third insulating layers stacked alternately and a third via conductor penetrating the third insulating layer, the third build-up portion having the second surface; and The second build-up portion is disposed between the first build-up portion and the third build-up portion, and includes second conductor layers and second insulating layers that are alternately stacked, and a second via conductor that penetrates the second insulating layer. in, The diameter of the first via-hole conductor is smaller than the diameter of the second via-hole conductor, The diameter of the second via conductor is smaller than the diameter of the third via conductor. The second build-up portion includes a plurality of the second insulating layers and a plurality of the second conductive layers.

2. The wiring substrate according to claim 1, wherein: The first build-up portion includes a plurality of the first insulating layers and a plurality of the first conductive layers.

3. The wiring substrate according to claim 1, wherein The number of the second insulating layers is greater than the number of the first insulating layers, and the number of the second conductive layers is greater than the number of the first conductive layers.

4. The wiring substrate according to claim 1, wherein: The third build-up portion includes a plurality of third insulating layers and a plurality of third conductive layers.

5. The wiring substrate according to claim 1, wherein The total thickness of the third insulating layer in the third build-up portion is 200 μm or more.

6. The wiring substrate according to claim 1, wherein The first conductor layer includes a first wiring, The wiring width of the first wiring is smaller than the minimum wiring width of the wiring included in the second conductor layer, The interval between the first wirings is smaller than the minimum interval between the wirings included in the second conductor layer.

7. The wiring substrate according to claim 6, wherein: The aspect ratio of the first wiring is greater than or equal to 2.0 and less than or equal to 4.0, The first wiring has a wiring width of 3 μm or less. The interval between the first wirings is 3 μm or less.

8. The wiring substrate according to claim 6, wherein: The first build-up portion has a plurality of conductive pads exposed on the first surface. The first surface has a plurality of component mounting areas each including the conductor pad. The conductor pads arranged in different component mounting regions among the plurality of component mounting regions are connected via the first wiring.

9. The wiring substrate according to claim 1, wherein: The diameter of the first via-hole conductor on the upper surface of the lower conductor layer to which the first via-hole conductor is connected is approximately 10 μm.

10. The wiring substrate according to claim 1, wherein The third insulating layer includes a core material.

11. The wiring substrate according to claim 10, wherein: The core material is glass fiber.

12. The wiring substrate according to claim 1, wherein The first via-hole conductor, the second via-hole conductor, and the third via-hole conductor have shapes that decrease in diameter from the second surface toward the first surface.

13. The wiring substrate according to claim 1, wherein The first conductor layer and the first via conductor include a first seed layer covering the surface of the first insulating layer and the inner surface of the first via opening, and a first plating film layer on the first seed layer. The second conductor layer and the second via conductor include a second seed layer covering the surface of the second insulating layer and the inner surface of the second via opening, and a second plating film layer on the second seed layer. The first seed layer includes a sputtered film, The second seed layer includes a chemical plating film.

14. The wiring substrate according to claim 1, wherein The conductive layer on the surface of the second build-up portion on the first build-up portion side and the via-conductor formed on the insulating layer of the first build-up portion closest to the second build-up portion are formed integrally.

Images