Multilayer circuit board and manufacturing method thereof

Abstract

The invention discloses a multilayer circuit board and a manufacturing method thereof, and relates to the technical field of electronic circuit additive manufacturing. According to the manufacturing method, a printing process and an etching process are combined, and circuit patterns of different levels in the multilayer circuit board are produced by using different process structures, so that the production efficiency of the circuit board can be effectively improved, and the waste and pollution treatment cost is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuit additive manufacturing, and in particular relates to a multilayer circuit board and a manufacturing method thereof. Background Art

[0002] Double-sided or multi-layer circuit boards on the market are mostly produced and processed using chemical etching technology. Although the technology is mature and can meet the production and processing of higher-precision circuit patterns, it has low production efficiency, severe environmental pollution, high waste costs and pollution treatment costs. In addition, as the country's demand for environmental improvement and carbon emission control continues to increase, its cost will continue to increase in the future. Summary of the invention

[0003] In view of this, an object of the present invention is to provide a method for manufacturing a multilayer circuit board, a double-sided circuit board and a multilayer circuit board, so as to solve the problems of low production efficiency, large environmental pollution, high waste cost and pollution treatment cost of traditional circuit board processes.

[0004] In some illustrative embodiments, the method for manufacturing the multilayer circuit board includes: preparing a first insulating layer; forming a first printed circuit pattern on a first surface of the first insulating layer using a conductive paste, and forming a first plated circuit pattern by electroplating on the first printed circuit pattern; preparing a stack; the stack includes: a second insulating layer having a first surface and a second surface vertically opposite to each other, and a metal foil layer formed on the first surface of the second insulating layer; bonding the second surface of the second insulating layer of the stack to the surface of the first insulating layer where the plated circuit pattern is located; opening a hole through the first insulating layer and the first printed circuit pattern to the first insulating layer; A first blind hole of a first plated circuit pattern, and a second blind hole penetrating the metal foil layer and the second insulating layer and directly reaching the first plated circuit pattern; forming a second printed circuit pattern on the second surface of the first insulating layer by using a conductive paste, and filling the first blind hole to form a conductive column for realizing conductive interconnection between the second printed circuit pattern and the first plated circuit pattern; performing hole metallization treatment on the second blind hole to obtain a metallized hole for realizing conductive interconnection between the metal foil layer and the first plated circuit pattern; electroplating the second printed circuit pattern to form a second plated circuit pattern, and etching the metal foil layer to form an etched circuit pattern.

[0005] In some optional embodiments, the minimum line width and / or minimum line distance of the printed circuit pattern is greater than that of the etched circuit pattern.

[0006] In some optional embodiments, the metallization treatment of the second blind hole includes: using the stacked structure formed with the second printed circuit pattern and the conductive column as a semi-process circuit board, and temporarily bonding two semi-process circuit boards with the second printed circuit surface; forming a conductive carbon layer electrically connected to the metal foil layer and the first plated circuit pattern on the hole wall of the second blind hole, and then forming a plated metal layer on the conductive carbon layer by electroplating; after the electroplating is completed, separating and restoring the semi-process circuit board.

[0007] In some optional embodiments, the first metal foil layer and / or the second metal foil layer has or does not have surface plating during the electroplating process.

[0008] In some optional embodiments, the electroplating of the second printed circuit pattern to form a second plated circuit pattern includes: using the stacked structure formed with the second printed circuit pattern and the conductive column as a semi-process circuit board, and temporarily bonding two semi-process circuit boards with the surface where the metal foil layer is located; electroplating the second printed circuit pattern to form a second plated circuit pattern; and after the electroplating is completed, separating and restoring the semi-process circuit board.

[0009] In some optional embodiments, temporary bonding of the two half-process circuit boards is achieved through an adhesive layer; wherein the adhesive layer includes: a stacked first adhesive layer, a carrier layer and a second adhesive layer; wherein the stress strength of the carrier layer is greater than that of the first adhesive layer and / or the second adhesive layer; and the adhesion of the first adhesive layer and / or the second adhesive layer to the carrier layer is greater than that to the half-process circuit board.

[0010] In some optional embodiments, before applying the conductive paste, it also includes: forming a primer layer on the printing surface of the conductive paste, and the conductive paste is applied on the primer layer; wherein the primer layer is used to improve the adhesion of the conductive paste on the supporting surface.

[0011] Another object of the present invention is to provide a multilayer circuit board to solve the problems in the prior art.

[0012] In some illustrative embodiments, the multilayer circuit board is obtained by any of the manufacturing methods described above.

[0013] In some illustrative embodiments, the multilayer circuit board includes: a second plated circuit pattern, a second printed circuit pattern, a first insulating layer, a first printed circuit pattern, a first plated circuit pattern, a second insulating layer, and an etched circuit pattern stacked in sequence; wherein the first plated circuit pattern is formed on the first printed circuit pattern, the second plated circuit pattern is formed on the second printed circuit pattern, the first printed circuit pattern and the second printed circuit pattern are interconnected by conductive columns passing through the first insulating layer, and the first plated circuit pattern and the etched circuit pattern are interconnected by metallized holes passing through the second insulating layer.

[0014] In some illustrative embodiments, a covering layer is formed on the etched circuit pattern and / or the second plated circuit pattern; wherein the covering layer shields part or all of the etched circuit pattern and / or the second plated circuit pattern; and / or, a primer layer is formed between the first insulating layer and the first printed circuit pattern and / or between the first insulating layer and the second printed circuit pattern, and the conductive column penetrates the primer layer; wherein the primer layer is used to enhance the adhesion of the conductive paste on the first insulating layer.

[0015] Compared with the prior art, this application has the following advantages:

[0016] The present invention can effectively improve the production efficiency of circuit boards and reduce waste and pollution treatment costs by combining the printing process with the etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is an example of a process of a method for manufacturing a circuit board in an embodiment of the present invention;

[0018] Figure 2 This is a process example of a method for manufacturing a circuit board in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] It should be noted that the various technical features in the embodiments of the present invention can be combined with each other without conflict.

[0021] The present invention discloses a method for manufacturing a multilayer circuit board. Specifically, Figure 1-2 As shown, Figure 1 This is an example of a process for manufacturing a multilayer circuit board in an embodiment of the present invention; Figure 2 This is a process example of a method for manufacturing a multilayer circuit board in an embodiment of the present invention. The method for manufacturing a multilayer circuit board includes:

[0022] Step S11, preparing a first insulating layer 110;

[0023] The first insulating layer can be made of a hard board or a soft board. The hard board includes but is not limited to: FR-4, CEM-1, 22F, CEM-3, wood, glass, plastic, PMMA (Acrylic), etc.; the soft board includes but is not limited to PET, PVC, PU, ​​PC, PP, PA, PI, CPI (transparent PI), TPE, TPU, TPV, etc.;

[0024] Step S12: forming a first printed circuit pattern 310 on the first surface of the first insulating layer 110 by using a conductive paste;

[0025] The printing process used in the embodiments of the present invention includes but is not limited to screen printing, direct writing printing, inkjet printing, etc.

[0026] The conductive paste in the embodiment of the present invention refers to a composite low-temperature conductive paste mainly composed of a conductive filler, a resin binder and a solvent. After the paste is fully cured, the solvent will fully evaporate, thereby converting it into a conductive film in which the conductive filler is bound by the resin film-forming material.

[0027] The conductive filler is not limited to one or at least two of metal particles, graphene, conductive carbon black, carbon nanotubes, and conductive particles such as core-shell structures; the metal particles are not limited to one or at least two of gold, silver, copper, iron, nickel, zinc, and silver-coated copper powder; the resin binder can be any resin on the market, including but not limited to one or at least two of epoxy resin, acrylic resin, naphthalene-containing epoxy resin, polyaromatic epoxy resin, multifunctional epoxy resin, bismaleimide resin, and polyimide resin. The present application does not limit the selection of solvents.

[0028] The curing method of the conductive paste in the embodiment of the present invention is not limited to thermosetting, photocuring, electromagnetic radiation or other curing methods.

[0029] Step S13, electroplating to form a first plated circuit pattern 410 on the first printed circuit pattern 310;

[0030] The first plated circuit pattern mainly functions to improve one or more of the conductivity, stability, solderability, oxidation resistance, surface properties, etc. of the printed circuit pattern.

[0031] In some embodiments, the plated metal includes, but is not limited to, gold, silver, copper, iron, aluminum, zinc, nickel, and the like.

[0032] Step S14, preparing a stacked body;

[0033] The laminate includes: a second insulating layer 120 having a first surface and a second surface vertically opposite to each other, and a metal foil layer 210 formed on the first surface of the second insulating layer;

[0034] The second insulating layer may be made of a hard board or a soft board. The hard board includes but is not limited to: FR-4, CEM-1, 22F, CEM-3, wood, glass, plastic, PMMA (Acrylic), etc.; the soft board includes but is not limited to PET, PVC, PU, ​​PC, PP, PA, PI, CPI (transparent PI), TPE, TPU, TPV, etc.;

[0035] The metal foil layer includes, but is not limited to, gold, silver, copper, iron, aluminum, zinc, nickel, etc. The metal foil layer may also include a conductive alloy material with the aforementioned materials as main components.

[0036] The metal foil layer may be formed on the insulating layer by lamination or deposition (chemical deposition, evaporation or sputtering), etc., and the present invention is not limited thereto.

[0037] Step S15, laminating the second surface of the second insulating layer 120 of the stacked body with the surface of the first insulating layer 110 where the first plated circuit pattern 410 is located;

[0038] Optionally, the two can be bonded together by an adhesive layer 810 .

[0039] Step S16, opening a first blind hole penetrating through the first insulating layer 110 and the first printed circuit pattern 310 and directly reaching the first plated circuit pattern 410, and a second blind hole penetrating through the metal foil layer 210 and the second insulating layer 120 and directly reaching the first plated circuit pattern 410;

[0040] The first blind hole and / or the second blind hole are not limited to being realized by mechanical drilling or laser drilling, and can be specifically etched from the second surface of the first insulating layer / the second insulating layer until the first plating circuit pattern is etched.

[0041] Optionally, after the first blind hole and / or the second blind hole are processed, the process may further include: using a plasma generator to clean the blind hole, thereby removing the remaining first insulating layer and / or second insulating layer, exposing the complete metal surface at the bottom of the blind hole as much as possible, so as to improve the reliability of subsequent conductive interconnection and reduce contact resistance.

[0042] Preferably, the temperature of the first insulating layer and / or the second insulating layer can be controlled to reach the glass transition temperature of the material, and then surface treatment can be performed by plasma, which can effectively improve the removal effect of residual impurities.

[0043] Step S17, forming a second printed circuit pattern 320 on the second surface of the first insulating layer 110 by using a conductive paste, and filling the first blind hole to form a conductive column 510 for realizing conductive interconnection between the second printed circuit pattern 320 and the first plated circuit pattern 410;

[0044] The second printed circuit pattern and the conductive column can be formed by one printing process or by multiple printing processes, and the present application does not limit this. In the embodiment of separate forming, the forming order of the conductive column and the second printed circuit pattern can be reversed, depending on actual needs, and the present application does not limit this.

[0045] The printing process used in the embodiments of the present invention includes but is not limited to screen printing, direct writing printing, inkjet printing, etc.

[0046] Preferably, for the embodiment using the screen printing process, the second printed circuit pattern and the conductive column can be formed respectively through two printing processes, and the control parameters of each printing process are different to meet the molding quality of the surface molding and the plugging hole.

[0047] Step S18, performing hole metallization processing on the second blind hole to obtain a metallized hole that realizes conductive interconnection between the metal foil layer 210 and the first plated circuit pattern 410;

[0048] Optionally, a conductive carbon layer 515 electrically connected to the metal foil layer 210 and the first plated circuit pattern 410 is formed on the hole wall of the second blind hole, and then a plated metal layer 520 is formed on the conductive carbon layer 515 by electroplating (wherein the plated metal layer is not limited to the hole wall metal or the columnar structure that plates the entire blind hole), thereby forming a metallized hole;

[0049] Specifically, a conductive carbon layer electrically connected to the metal foil layer and the second metal foil layer is formed on the hole wall of the second blind hole, and a plated metal layer is formed on the conductive carbon layer by electroplating. The conductive carbon layer is not limited to conductive carbon black or conductive graphite, and is not limited to being achieved by black hole or black shadow processing. In other embodiments, the conductive carbon layer can also be formed by laser carbon planting (laser ablation to form a surface carbon layer) and other methods.

[0050] The metal foil layer may or may not be plated on the surface during the electroplating process, depending on the thickness of the metal foil layer and the raw material, as well as the target thickness of the etching circuit pattern; if surface plating is not required, a metal foil layer may be used for masking.

[0051] Step S19 , electroplating the second printed circuit pattern 320 to form a second plated circuit pattern 420 , and etching the metal foil layer 210 to form an etched circuit pattern 210E.

[0052] In this step, the order of forming the second plating circuit pattern and the etching circuit pattern can be reversed, and this application does not limit this.

[0053] In some embodiments, the process of forming the metallized hole in step S18 may include:

[0054] The stacked structure formed with the second printed circuit pattern 320 and the conductive pillar 510 is used as a semi-processed circuit board, and two semi-processed circuit boards are temporarily bonded together at the surface where the second printed circuit 320 is located; wherein the temporary bonding can be achieved by the adhesive layer 820.

[0055] A conductive carbon layer 515 electrically connected to the metal foil layer 210 and the first plated circuit pattern 410 is formed on the hole wall of the second blind hole, and a plated metal layer 520 is formed on the conductive carbon layer 515 by electroplating;

[0056] After the electroplating is completed, the semi-process circuit board is separated and restored.

[0057] In some embodiments, the process of electroplating the second plated circuit pattern on the second printed circuit pattern in step S19 may include:

[0058] The stacked structure formed with the second printed circuit pattern 320 and the conductive pillars 510 is used as a semi-processed circuit board, and two semi-processed circuit boards are temporarily bonded together at the surface where the metal foil layer 210 is located; the temporary bonding can be achieved by the adhesive layer 830.

[0059] Electroplating the second printed circuit pattern 320 to form a second plated circuit pattern 420;

[0060] After the electroplating is completed, the semi-process circuit board is separated and restored.

[0061] In some embodiments, temporary bonding of the two half-process circuit boards can be achieved through an adhesive layer (820 and / or 830); wherein the adhesive layer includes: a stacked first adhesive layer, a carrier layer, and a second adhesive layer; wherein the stress strength of the carrier layer is greater than that of the first adhesive layer and / or the second adhesive layer; and the adhesion of the first adhesive layer and / or the second adhesive layer to the carrier layer is greater than that to the half-process circuit board.

[0062] Through the design of the carrier layer and the double-sided adhesive layer and the adhesion between them, on the one hand, the problem of the single adhesive layer being difficult to remove is solved, making the adhesive layer easy to peel off; on the other hand, the addition of a carrier layer with a certain structural strength is conducive to reducing bubbles between the colloid bonding surfaces, making the bonding surfaces tighter, and avoiding leakage of the plating liquid causing undesirable plating on the metal foil layer.

[0063] The carrier layer includes but is not limited to a non-adhesive soft board or a hard board.

[0064] In some embodiments, before applying the conductive paste, it also includes: forming a primer layer on the printing surface of the conductive paste, and the conductive paste is applied on the primer layer; wherein the primer layer is used to improve the adhesion of the conductive paste on the supporting surface.

[0065] The primer layer includes but is not limited to a first primer layer 710 between the first insulating layer 110 and the first printed circuit layer 310 and / or a second primer layer 720 between the first insulating layer 110 and the second printed circuit layer 320 .

[0066] The applicant has found that in the double-sided circuit boards / multi-layer circuit boards currently on the market, circuits with higher laying density and higher precision can be implemented using only one or several layers of two or more layers of circuits, without all of them being designed as higher precision circuits. Therefore, the traditional etching process can be used to implement the circuits with higher precision requirements (that is, the circuits actually occupy more area within a specified range), while the circuits of other layers can be implemented using a printing process with relatively lower precision.

[0067] Furthermore, since the etching target is directed toward the side with a higher laying density, the amount of metal foil actually etched away is greatly reduced. While ensuring quality, the waste cost and pollution treatment cost can be effectively reduced.

[0068] In some embodiments, the minimum line width and / or minimum line distance of the first printed circuit pattern in the embodiments of the present invention is greater than that of the etched circuit pattern.

[0069] In some embodiments, the printed circuit pattern is laid out on the insulating layer at a density lower than that of the etched circuit pattern.

[0070] Optionally, the minimum line pitch and / or minimum line width of the etched circuit pattern may be in the range of 1-100 μm, while the minimum line pitch and / or minimum line width of the printed circuit pattern may be in the range of 2-200 μm.

[0071] Those skilled in the art should understand that although the two ranges overlap, the minimum line spacing and / or minimum line width of the etched circuit pattern can be selected to be smaller than the actual parameters of the minimum line spacing and / or minimum line width of the printed circuit pattern according to needs.

[0072] An embodiment of the present invention discloses a multi-layer circuit board, which can be obtained by any of the above-mentioned manufacturing methods.

[0073] An embodiment of the present invention discloses a multilayer circuit board, comprising: a second plated circuit pattern 420, a second printed circuit pattern 320, a first insulating layer 110, a first printed circuit pattern 310, a first plated circuit pattern 410, a second insulating layer 120, and an etched circuit pattern 210E stacked in sequence; wherein the first plated circuit pattern 410 is formed on the first printed circuit pattern 310, the second plated circuit pattern 420 is formed on the second printed circuit pattern 320, the first printed circuit pattern 310 and the second printed circuit pattern 320 are interconnected by a conductive column 510 penetrating the first insulating layer 110, and the first plated circuit pattern 410 and the etched circuit pattern 210E are interconnected by a metallized hole penetrating the second insulating layer 120.

[0074] In some embodiments, a covering layer is formed on the etching circuit pattern and / or the second plating circuit pattern; wherein the covering layer shields a part or the whole of the etching circuit pattern and / or the second plating circuit pattern.

[0075] In some embodiments, a primer layer is formed between the first insulating layer and the first printed circuit pattern and / or between the first insulating layer and the second printed circuit pattern, and the conductive column penetrates the primer layer; wherein the primer layer is used to enhance the adhesion of the conductive paste on the first insulating layer.

[0076] The primer layer includes but is not limited to a first primer layer 710 between the first insulating layer 110 and the first printed circuit layer 310 and / or a second primer layer 720 between the first insulating layer 110 and the second printed circuit layer 320 .

[0077] In some embodiments, the minimum line width and / or minimum line distance of the first printed circuit pattern in the embodiments of the present invention is greater than that of the etched circuit pattern.

[0078] In some embodiments, the printed circuit pattern is laid out on the insulating layer at a density lower than that of the etched circuit pattern.

[0079] Optionally, the minimum line pitch and / or minimum line width of the etched circuit pattern may be in the range of 1-100 μm, while the minimum line pitch and / or minimum line width of the printed circuit pattern may be in the range of 2-200 μm.

[0080] Those skilled in the art should understand that although the two ranges overlap, the minimum line spacing and / or minimum line width of the etched circuit pattern can be selected to be smaller than the actual parameters of the minimum line spacing and / or minimum line width of the printed circuit pattern according to needs.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a multilayer circuit board, characterized in that: include: preparing a first insulating layer; forming a first printed circuit pattern on the first surface of the first insulating layer using a conductive paste, and forming a first plated circuit pattern by electroplating on the first printed circuit pattern; Prepare a layer of laminate; The laminated body comprises: a second insulating layer having a first surface and a second surface vertically opposite to each other, and a metal foil layer formed on the first surface of the second insulating layer; The second surface of the second insulating layer of the stacked body is bonded to the surface of the first insulating layer where the first plated circuit pattern is located; A first blind hole is formed which penetrates through the first insulating layer and the first printed circuit pattern and directly reaches the first plated circuit pattern, and a second blind hole is formed which penetrates through the metal foil layer and the second insulating layer and directly reaches the first plated circuit pattern; forming a second printed circuit pattern on the second surface of the first insulating layer by using a conductive paste, and filling the first blind hole to form a conductive column for realizing conductive interconnection between the second printed circuit pattern and the first plated circuit pattern; Performing hole metallization processing on the second blind hole to obtain a metallized hole that realizes conductive interconnection between the metal foil layer and the first plated circuit pattern; The second printed circuit pattern is electroplated to form a second plated circuit pattern, and the metal foil layer is etched to form an etched circuit pattern.

2. The method according to claim 1, characterized in that: The minimum line width and / or minimum line distance of the printed circuit pattern is greater than that of the etched circuit pattern.

3. The method according to claim 1, characterized in that: The step of performing hole metallization processing on the second blind hole comprises: Using the stacked structure formed with the second printed circuit pattern and the conductive pillars as a half-process circuit board, and temporarily bonding two half-process circuit boards together with the surface where the second printed circuit is located; forming a conductive carbon layer electrically connected to the metal foil layer and the first plated circuit pattern on the hole wall of the second blind hole, and then forming a plated metal layer on the conductive carbon layer by electroplating; After the electroplating is completed, the semi-process circuit board is separated and restored.

4. The method according to claim 1 or 3, characterized in that: The first metal foil layer and / or the second metal foil layer may or may not have surface plating added during the electroplating process.

5. The method according to claim 1, characterized in that: The step of electroplating the second printed circuit pattern to form a second plated circuit pattern comprises: Using the stacked structure formed with the second printed circuit pattern and the conductive pillars as a half-process circuit board, and temporarily bonding two half-process circuit boards together with the surface where the metal foil layer is located; Electroplating the second printed circuit pattern to form a second plated circuit pattern; After the electroplating is completed, the semi-process circuit board is separated and restored.

6. The method according to claim 3 or 5, characterized in that: Temporary bonding of the two half-process circuit boards is achieved through an adhesive layer; wherein the adhesive layer includes: a stacked first adhesive layer, a carrier layer, and a second adhesive layer; wherein the stress strength of the carrier layer is greater than that of the first adhesive layer and / or the second adhesive layer; and the adhesion of the first adhesive layer and / or the second adhesive layer to the carrier layer is greater than that to the half-process circuit board.

7. The manufacturing method according to claim 1, characterized in that: Before applying the conductive paste, it also includes: forming a primer layer on the printing surface of the conductive paste, and the conductive paste is applied on the primer layer; wherein the primer layer is used to improve the adhesion of the conductive paste on the supporting surface.

8. A multilayer circuit board, characterized in that: Obtained by the preparation method described in any one of claims 1-7.

9. A multilayer circuit board, characterized in that: include: A second plated circuit pattern, a second printed circuit pattern, a first insulating layer, a first printed circuit pattern, a first plated circuit pattern, a second insulating layer, and an etched circuit pattern are stacked in sequence; wherein the first plated circuit pattern is formed on the first printed circuit pattern, the second plated circuit pattern is formed on the second printed circuit pattern, the first printed circuit pattern and the second printed circuit pattern are interconnected by a conductive column passing through the first insulating layer, and the first plated circuit pattern and the etched circuit pattern are interconnected by a metallized hole passing through the second insulating layer.

10. The multilayer circuit board according to claim 9, characterized in that: A covering layer is formed on the etched circuit pattern and / or the second plated circuit pattern; wherein the covering layer shields part or all of the etched circuit pattern and / or the second plated circuit pattern; and / or, a primer layer is formed between the first insulating layer and the first printed circuit pattern and / or between the first insulating layer and the second printed circuit pattern, and the conductive column penetrates the primer layer; wherein the primer layer is used to enhance the adhesion of the conductive paste on the first insulating layer.

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