Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a preparation method thereof. The preparation method comprises: providing a substrate, and forming first isolation layers and second isolation layers in an alternating stack on the substrate; etching the first isolation layers and the second isolation layers to form a capacitor hole group, the capacitor hole group comprising at least two capacitor sub-holes arranged at intervals along a first direction and extending to the substrate; performing lateral etching on the second isolation layers from the capacitor sub-holes to form first surrounding grooves surrounding the capacitor sub-holes; forming a first capacitor electrode extending along the first direction and filling the first surrounding grooves; forming a capacitor dielectric layer on the sidewalls and the bottom of the capacitor sub-holes, and forming a second capacitor electrode on the surface of the capacitor dielectric layer. The embodiments of the present disclosure can effectively improve the performance of the device.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] In the traditional fabrication process of three-dimensional memory devices, a stacked structure of silicon / silicon germanium is typically prepared first. Before forming the transistors and capacitors of the memory cells, the stacked structure is etched to form isolation trenches. The isolation trenches are used to isolate the transistors and / or capacitors that will be formed later. The isolation trenches are then filled with an insulating dielectric layer.

[0003] However, as the number of stacked layers in three-dimensional memory devices increases, the isolation trench depth increases. At this point, the bottom of the isolation trench may not be completely etched, resulting in incorrect electrical connections between the underlying transistors and / or capacitors, causing unstable performance of the entire memory cell and thus affecting device performance. Summary of the Invention

[0004] Based on this, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same that can reduce the process difficulty of manufacturing a memory device, especially a three-dimensional memory device.

[0005] A method for preparing a semiconductor structure, comprising:

[0006] Providing a substrate, and forming a first isolation layer and a second isolation layer alternately stacked on the substrate;

[0007] Etching the first isolation layer and the second isolation layer to form a capacitor hole group, wherein the capacitor hole group includes at least two capacitor sub-holes arranged at intervals along a first direction and extending to the substrate;

[0008] performing side etching on the second isolation layer from the capacitor hole to form a first surrounding groove surrounding the capacitor hole;

[0009] forming a first capacitor electrode extending along the first direction and filling the first surrounding groove;

[0010] A capacitor dielectric layer is formed on the sidewall and bottom of the capacitor hole, and a second capacitor electrode is formed on the surface of the capacitor dielectric layer.

[0011] In one embodiment, the shortest distance between the capacitor sub-holes adjacent to each other along the first direction in the same capacitor sub-hole group is H1, and the etching depth of the second isolation layer lateral-etched from the capacitor sub-hole is H2, where H2>=0.5H1.

[0012] In one embodiment, forming a capacitor hole group penetrating the stacked structure includes:

[0013] forming a plurality of capacitor hole groups spaced apart along a second direction, wherein the second direction intersects the first direction, and a plane defined by the second direction and the first direction intersects an extension direction of the capacitor holes;

[0014] Furthermore, the shortest distance between the capacitor sub-holes adjacent to each other along the second direction is H3, and H3>2H2.

[0015] In one embodiment, H3>=3H2.

[0016] In one embodiment, a capacitor region and a transistor region arranged along the first direction are provided on the substrate, and the capacitor hole group is located in the capacitor region.

[0017] The etching of the first isolation layer and the second isolation layer to form a capacitor hole group also forms a word line hole arranged opposite to the capacitor hole group in the first direction, wherein the word line hole is located in the transistor region and extends to the substrate;

[0018] Before the side etching of the second isolation layer from the capacitor quantum hole, the method further includes:

[0019] filling a sacrificial layer in the word line hole;

[0020] After forming a capacitor dielectric layer on the sidewall and bottom of the capacitor sub-hole and forming a second capacitor electrode on the surface of the capacitor dielectric layer, the method further includes:

[0021] removing the sacrificial layer located in the word line hole;

[0022] performing side etching on the second isolation layer from the word line hole to form a second surrounding groove surrounding the word line hole, wherein the second surrounding groove exposes the first capacitor electrode;

[0023] forming a channel layer in the second surrounding trench;

[0024] A gate dielectric layer is formed on the sidewall of the word line hole, and a word line is formed on the surface of the gate dielectric layer.

[0025] A semiconductor structure comprising:

[0026] substrate;

[0027] A first isolation layer and a second isolation layer alternately stacked on the substrate;

[0028] a first capacitor electrode comprising at least two annular portions arranged along a first direction, adjacent annular portions being connected to each other, and the first capacitor electrode being located between adjacent first isolation layers and being wrapped by the second isolation layer;

[0029] a second capacitor electrode, surrounded by the annular portion, penetrating the alternately stacked first isolation layers and second isolation layers and extending to the substrate;

[0030] a capacitor dielectric layer, surrounded by the annular portion, located between the second capacitor electrode and the first capacitor electrode, and located on a sidewall of the second capacitor electrode;

[0031] In which, the shortest distance between adjacent capacitor dielectric layers in the first direction is H1, the width of the first capacitor electrode in the second direction is H2, H2>=0.5H1, the second direction intersects with the first direction, and the plane determined by the second direction and the first direction intersects with the extension direction of the capacitor sub-hole.

[0032] In one embodiment, the semiconductor structure includes a plurality of first capacitor electrodes spaced apart along the second direction, and the shortest distance between adjacent capacitor dielectric layers along the second direction is H3, where H3>2H2.

[0033] In one embodiment, H3>=3H2.

[0034] In one embodiment,

[0035] A capacitor region and a transistor region are provided on the substrate and arranged along the first direction, the first capacitor electrode is located in the capacitor region, and a transistor connected to the first capacitor electrode is provided in the transistor region;

[0036] The transistor includes:

[0037] a word line, penetrating the first isolation layer and the second isolation layer and extending to the substrate, and arranged opposite to the first capacitor electrode in the first direction;

[0038] a gate dielectric layer, located on a sidewall of the word line;

[0039] The channel layer is located between adjacent first isolation layers, connected to the first capacitor electrode, and wrapped by the second isolation layer. The channel layer surrounds the gate dielectric layer.

[0040] In one embodiment,

[0041] A bit line region is further provided on the substrate. The transistor region is located between the capacitor region and the bit line region in the first direction. A bit line is provided in the bit line region.

[0042] The bit line is located between adjacent first isolation layers, and the bit line and the first capacitor electrode are respectively connected to two sides of the channel layer, and the bit line extends along the second direction.

[0043] The method for preparing the above-mentioned semiconductor structure first forms a capacitor sub-hole extending to the substrate in the alternating stack of the first isolation layer and the second isolation layer, and then laterally etches the second isolation layer from the capacitor sub-hole, thereby directly forming a capacitor (including a first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode). At the same time, the first isolation layer and the second isolation layer that are initially deposited can be used as isolation dielectric layers to insulate and isolate the capacitor, thereby eliminating the need to etch to form isolation trenches. Therefore, this embodiment can effectively reduce the process difficulty of preparing storage devices, especially three-dimensional storage devices, and can effectively prevent capacitor misconnection, thereby improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0045] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in one embodiment;

[0046] Figures 2 to 14 Schematic diagram of the structure obtained in different orientations in each step of the preparation process of the semiconductor structure provided in one embodiment, wherein: Figure 14 Schematic diagram of the structure of a semiconductor structure provided in different orientations according to an embodiment.

[0047] Description of reference numerals:

[0048] 100-substrate, 210-first isolation layer, 220-second isolation layer, 310-first capacitor electrode, 311-annular portion, 320-capacitor dielectric layer, 330-second capacitor electrode, 331-electrode layer, 332-filling conductive layer, 400-sacrificial layer, 500-transistor, 510-channel layer, 520-gate dielectric layer, 530-word line, 531-metal diffusion barrier layer, 532-metal layer, 600-bit line, 10-capacitor hole group, 11-capacitor sub-hole, 20-first surrounding groove, 30-word line hole, 40-second surrounding groove, 50-etched opening, 60-bit line groove. DETAILED DESCRIPTION

[0049] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0051] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0052] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0053] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] In one embodiment, see Figure 1 , provides a method for preparing a semiconductor structure, comprising the following steps:

[0055] Step S100, see Figure 2 , providing a substrate 100, and forming a first isolation layer 210 and a second isolation layer 220 alternately stacked on the substrate 100;

[0056] Step S200, please refer to Figure 3 , etching the first isolation layer 210 and the second isolation layer 220 to form a capacitor hole group 10, wherein the capacitor hole group 10 includes at least two capacitor sub-holes 11 arranged at intervals along the first direction and extending to the substrate 100;

[0057] Step S400, please refer to Figure 6 , the second isolation layer 220 is laterally etched from the capacitor hole 11 to form a first surrounding groove 20 surrounding the capacitor hole 11;

[0058] Step S500, please refer to Figure 7 , forming a first capacitor electrode 310 extending along the first direction and filling the first surrounding groove 20;

[0059] Step S600, please refer to Figure 8 A capacitor dielectric layer 320 is formed on the sidewall and bottom of the capacitor hole 11 , and a second capacitor electrode 330 is formed on the surface of the capacitor dielectric layer 320 .

[0060] In step S100, refer to Figure 2 The substrate 100 may be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. For example, the substrate 100 may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 100 may also include a Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator substrate.

[0061] Meanwhile, the substrate 100 may be a single-layer structure or a multi-layer structure. When the substrate 100 comprises a multi-layer structure, it may include a substrate and other structures or film layers formed on the substrate.

[0062] When forming the alternating stack of first isolation layers 210 and second isolation layers 220 on substrate 100, the first isolation layers 210 and the second isolation layers 220 can be repeatedly and alternately formed on substrate 100 through a deposition process. The first isolation layers 210 and the second isolation layers 220 are made of different materials. The first isolation layers 210 may include, but are not limited to, silicon oxide. The second isolation layers 220 may include, but are not limited to, silicon nitride.

[0063] The deposition process may include, but is not limited to, one or more of a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition (HDP), a plasma enhanced deposition process, and a spin-on dielectric layer (SOD).

[0064] The second isolation layer 220 may be formed at least one layer. As an example, multiple first isolation layers 210 and multiple second isolation layers 220 may be formed. Each second isolation layer 220 may be formed with a first isolation layer 210 on both sides. This facilitates the formation of a three-dimensional device.

[0065] In step S200, refer to Figure 3 , a first patterned photoresist can be first formed on the top first isolation layer 210. The first patterned photoresist can have a first opening. The first opening can define the size and position of the capacitor hole 11. Then, based on the first patterned photoresist, the first isolation layer 210 and the second isolation layer 220 are dry-etched, etc., to form a plurality of capacitor holes 11 that are spaced apart and extend to the substrate 100. Among them, at least two capacitor holes 11 spaced apart along the first direction form a capacitor hole group 10. As an example, the capacitor holes 11 in the same capacitor hole group 10 can be arranged at equal intervals along the first direction.

[0066] In step S400, refer to Figure 6 The second isolation layer 220 can be laterally etched back from the capacitor hole 11 by wet etching or dry etching, thereby forming a surrounding groove surrounding the capacitor hole 11.

[0067] In step S500, refer to Figure 7 A first capacitor electrode material layer can be deposited on the surface of the structure formed after forming the first surrounding groove 20. The first capacitor electrode material layer is then etched to remove the first capacitor electrode material layer outside the first surrounding groove 20. The first capacitor electrode material layer remaining within the first surrounding groove 20 forms the first capacitor electrode 310.

[0068] The material of the first capacitor electrode 310 may include, but is not limited to, titanium nitride (TiN). For example, the material of the first capacitor electrode 310 may also include indium tin oxide (ITO). For another example, the material of the first capacitor electrode 310 may also include molybdenum (MO), tantalum titanium (TaTi), tungsten nitride (WN), etc.

[0069] In step S600, refer to Figure 8 After forming the first capacitor electrode 310, a capacitor dielectric material layer can be deposited on the surface of the resulting structure, and then a second capacitor electrode material layer can be deposited on the surface of the capacitor dielectric material layer. As an example, the second capacitor electrode material layer can include an electrode material layer and a filling material layer. The electrode material layer can be formed on the surface of the capacitor dielectric material layer. The filling material layer can be formed on the surface of the electrode material layer and fill the remaining space of the capacitor sub-hole 11.

[0070] Afterwards, the second capacitor electrode material layer and the capacitor dielectric material layer located outside the capacitor hole 11 can be removed by a process such as chemical mechanical polishing (CMP). The remaining capacitor dielectric material layer forms the capacitor dielectric layer 320. The remaining second capacitor electrode material layer forms the second capacitor electrode 330. When the second capacitor electrode material layer includes an electrode material layer and a filling material layer, the remaining electrode material layer forms the electrode layer 331, and the remaining filling material layer forms the filling conductive layer 332. That is, the second capacitor electrode 330 now includes the electrode layer 331 and the filling conductive layer 332.

[0071] The first capacitor electrode 310 , the capacitor dielectric layer 320 opposite thereto, and the second capacitor electrode 330 may form a capacitor 300 .

[0072] The material of the capacitor dielectric layer 320 may include, but is not limited to, high dielectric constant materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3). The material of the electrode layer 331 may include, but is not limited to, titanium nitride (TiN). For example, the material of the electrode layer 331 may also include indium tin oxide (ITO). For another example, the material of the electrode layer 331 may also include molybdenum (MO), tantalum titanium (TaTi), tungsten nitride (WN), etc. The material of the filling conductive layer 332 may include, but is not limited to, silicon germanium (SiGe) or doped polycrystalline silicon.

[0073] It is understandable that in order to make the image clear, Figures 8 to 14 In FIG. 5( c ), the capacitor dielectric layer 320 and the electrode layer 331 are omitted.

[0074] In this embodiment, by first forming a capacitor hole 11 extending to the substrate 100 in the alternating stack of the first isolation layer 210 and the second isolation layer 220, and then laterally etching the second isolation layer 220 from the capacitor hole 11, the capacitor 300 (including the first capacitor electrode 310, the capacitor dielectric layer 320 and the second capacitor electrode 330) can be directly formed. At the same time. The first isolation layer 210 and the second isolation layer 220 that are initially deposited can be used as isolation dielectric layers to insulate and isolate the capacitor 300, thereby eliminating the need to etch to form isolation trenches. Therefore, this embodiment can effectively reduce the process difficulty of preparing memory devices, especially three-dimensional memory devices, and can effectively prevent the capacitor 300 from being incorrectly connected, thereby improving device performance.

[0075] It is understandable that the size of the capacitor hole 11 is larger than that of a conventional isolation trench. Therefore, the capacitor hole 11 of this embodiment does not have the problem of being unable to complete etching when a large number of stacked layers are present, as in the case of conventional isolation trenches.

[0076] In one embodiment, see Figure 6 The shortest distance between adjacent capacitor holes 11 along the first direction in the same capacitor hole group 10 is H1. Meanwhile, in step S400, the etching depth of the second isolation layer 220 from the capacitor hole 11 is H2, and H2>=0.5H1.

[0077] At this time, after the lateral etching, the capacitor sub-holes 11 adjacent to each other along the first direction in the same capacitor hole group 10 are connected to each other.

[0078] Therefore, after filling the first surrounding trench 20 to form the first capacitor electrode 310 in step S500, a first capacitor electrode 310 can be formed that extends along the first direction and surrounds multiple capacitor sub-holes 11 within the same capacitor hole group 10 in the first direction. The width of the first capacitor electrode 310 in the second direction is H2. The plane defined by the second direction and the first direction intersects the extension direction of the capacitor sub-hole 11.

[0079] As an example, the first direction may be perpendicular to the second direction. A plane defined by the second direction and the first direction may be perpendicular to an extension direction of the capacitor aperture 11 .

[0080] In this case, the first capacitor electrode 310 may include at least two annular portions 311 arranged along the first direction. Each annular portion 311 may be formed within a first surrounding groove 20. Adjacent annular portions 311 are interconnected. Furthermore, the first capacitor electrode 310 and the second isolation layer 220 are both located between adjacent first isolation layers 210. Furthermore, the first capacitor electrode 310 is surrounded by the second isolation layer 220.

[0081] After the capacitor dielectric layer 320 and the second capacitor electrode 330 are formed in step S600 , the shortest distance between adjacent capacitor dielectric layers 320 in the first direction is H1 .

[0082] In this embodiment, the first capacitor electrode 310 can form a capacitor 300 together with the capacitor dielectric layer 320 in the plurality of capacitor sub-holes 11 in the same capacitor hole group 10 and the second capacitor electrode 330, thereby effectively increasing the capacitance value of the capacitor 300.

[0083] In one embodiment, see Figure 3 , step S200 includes:

[0084] In step S210 , a plurality of capacitor hole groups 10 are formed and arranged at intervals along a second direction, wherein the second direction intersects the first direction, and a plane defined by the second direction and the first direction intersects an extension direction of the capacitor holes 11 .

[0085] As an example, the capacitor aperture 11 may extend vertically, and a plane defined by the second direction and the first direction may be perpendicular to the extension direction of the capacitor aperture 11 .

[0086] When the shortest distance between adjacent capacitor holes 11 along the first direction within the same capacitor hole group 10 is H1, and the etching depth of the second isolation layer 220 from the capacitor hole 11 is H2, and H2>=0.5H1, each capacitor hole group 10 in the multiple capacitor hole groups 10 arranged at intervals along the second direction can form a corresponding capacitor 300.

[0087] Also, see Figure 6 , the shortest distance between adjacent capacitor sub-holes 11 along the second direction is set to H3, H3>2H2.

[0088] At this time, after the lateral etching in step S400 , the second isolation layer 220 between the capacitor hole groups 10 adjacent along the second direction will not be etched through, so that the first surrounding trenches 20 adjacent along the second direction can be insulated and isolated by the second isolation layer 220 .

[0089] Therefore, after the first surrounding trench 20 is subsequently filled to form the first capacitor electrode 310, and the capacitor dielectric layer 320 and the second capacitor electrode 330 are formed, the first capacitor electrodes 310 adjacent in the second direction can be insulated and isolated by the second isolation layer 220. Therefore, the capacitors 300 adjacent in the second direction formed based on the capacitor hole groups 10 adjacent in the second direction can be effectively insulated and isolated by the second isolation layer 220.

[0090] Meanwhile, after the capacitor dielectric layers 320 are formed, the shortest distance between adjacent capacitor dielectric layers 320 in the second direction is H3.

[0091] As an example, H3>=3H2 can be set. In this case, after the lateral etching in step S400, the width of the second isolation layer 220 between adjacent capacitor hole groups 10 in the second direction is theoretically greater than or equal to H2, thereby ensuring that the capacitors 300 adjacent to each other in the second direction are reliably isolated.

[0092] In one embodiment, see Figure 3 A capacitor region A1 and a transistor region A2 arranged along a first direction are provided on the substrate 100 , and the capacitor hole group 10 is located in the capacitor region A1 .

[0093] At the same time, in step S200 , the first isolation layer 210 and the second isolation layer 220 are etched to form the capacitor hole group 10 . At the same time, a word line hole 30 is formed opposite to the capacitor hole group 10 in the first direction. The word line hole 30 is located in the transistor region and extends to the substrate 100 .

[0094] At this time, in step S200, a first patterned photoresist can first be formed on the top first isolation layer 210. The first patterned photoresist can have a first opening and a second opening. The first opening is located in the capacitor area A1 and can define the size and position of the capacitor sub-hole 11. The second opening is located in the transistor area A2 and can define the size and position of the word line hole 30. Then, based on the first patterned photoresist, the first isolation layer 210 and the second isolation layer 220 are dry-etched, etc., to form the capacitor sub-hole 11 in the capacitor area A1 and the word line hole 30 in the transistor area A2.

[0095] At the same time, before step 400, the method further includes:

[0096] In step S300 , a sacrificial layer 400 is filled in the word line hole 30 .

[0097] At this time, see Figure 4 as well as Figure 5 First, a sacrificial material layer can be formed in the word line hole 30, in the capacitor hole 11, and on the upper surface of the top first isolation layer 210 by a chemical vapor deposition process or the like. Then, the sacrificial material layer located on the upper surface of the top first isolation layer 210 is removed by a chemical mechanical polishing (CMP) process to form a sacrificial layer 400. Thereafter, a second patterned photoresist can be formed. The second patterned photoresist can cover the sacrificial layer 400 located in the word line hole 30, while exposing the remaining sacrificial material layer located in the capacitor hole 11. Thereafter, the sacrificial layer 400 in the capacitor hole 11 can be etched away. At the same time, the sacrificial layer 400 in the word line hole 30 is retained.

[0098] The material of the sacrificial layer 400 may include, but is not limited to, polysilicon.

[0099] After the sacrificial layer 400 is filled in the word line hole 30 , the first capacitor electrode 310 , the capacitor dielectric layer 320 and the second capacitor electrode 330 formed in steps S400 to S600 will not be formed in the word line hole 30 , thereby not affecting the subsequent fabrication of the transistor 500 .

[0100] After step S600, the method further includes:

[0101] Step S710, please refer to Figure 9 , removing the sacrificial layer 400 located in the word line hole 30;

[0102] Step S720, please refer to Figure 10 , the second isolation layer 220 is laterally etched from the word line hole 30 to form a second surrounding groove 40 surrounding the word line hole 30 , wherein the second surrounding groove 40 exposes the first capacitor electrode 310 ;

[0103] Step S730, please refer to Figure 11 , forming a channel layer 510 in the second surrounding trench 40;

[0104] Step S740, please refer to Figure 12 A gate dielectric layer 520 is formed on the sidewall of the word line hole 30 , and a word line 530 is formed on the surface of the gate dielectric layer 520 .

[0105] In step S710, refer to Figure 9 The sacrificial layer 400 located in the word line hole 30 may be removed by wet etching or the like.

[0106] In step S720, refer to Figure 10 The second isolation layer 220 between the first isolation layers 210 can be etched back from the word line hole 30 by wet etching, thereby forming a second surrounding groove 40 surrounding the word line hole 30. The second surrounding groove 40 exposes the first capacitor electrode 310.

[0107] The lateral etching depth of the second isolation layer 220 from the capacitor sub-hole 11 is H2, the lateral etching depth of the second isolation layer 220 from the word line hole 30 is H4, and the shortest distance between the word line hole 30 and the capacitor sub-hole 11 adjacent to it along the first direction is H5. (H2+H4)>=H5 can be set so that the second surrounding trench 40 exposes the first capacitor electrode 310.

[0108] In step S730, refer to Figure 11A channel material layer can be first deposited on the surface of the structure obtained after forming the second surrounding groove 40. The channel material layer is then etched to remove the portion outside the second surrounding groove 40. The portion remaining within the second surrounding groove 40 forms the channel layer 510. The material of the channel layer 510 may include, but is not limited to, indium gallium zinc oxide (IGZO).

[0109] Because the second surrounding trench 40 surrounds the wordline hole 30, the channel layer 510 surrounds the wordline hole 30, thereby facilitating the formation of a channel-all-around (CAA) transistor 500. Furthermore, because the second surrounding trench 40 exposes the first capacitor electrode 310 and the channel layer 510 fills the second surrounding trench 40, the channel layer 510 can be connected to the first capacitor electrode 310, thereby enabling one of the source and drain regions of the transistor 500 to be connected to the first capacitor electrode 310 of the capacitor 300.

[0110] In step S740, refer to Figure 12 A gate dielectric material layer can be formed on the sidewalls of the wordline hole 30, the bottom of the wordline hole 30, and the upper surface of the top first isolation layer 210. A wordline material layer can then be deposited on the surface of the gate dielectric material layer. The wordline material layer can fill the remaining space in the wordline hole 30. Subsequently, the gate dielectric material layer and the wordline material layer outside the wordline hole 30 can be removed using a process such as chemical mechanical polishing (CMP). The remaining gate dielectric material layer forms the gate dielectric layer 520. The remaining wordline material layer forms the wordline 530.

[0111] The material of the gate dielectric layer 520 may include, but is not limited to, a high-k dielectric layer. The word line 530 may include a metal diffusion barrier layer 531 and a metal layer 532. The metal diffusion barrier layer 531 may include, but is not limited to, titanium nitride. The material of the metal layer 532 may include, but is not limited to, tungsten (W).

[0112] After the gate dielectric layer 520 and the word line 530 are formed, the word line 530 , the gate dielectric layer 520 and the channel layer 510 may form a CAA transistor 500 .

[0113] It is understandable that in order to make the image clear, Figures 12 to 14 In FIG. 5( c ), the gate dielectric layer 520 and the metal diffusion barrier layer 531 are omitted.

[0114] In one embodiment, a bit line 600 region A3 is further provided on the substrate, and the transistor region A2 is located between the capacitor region A1 and the bit line 600 region A3 in the first direction.

[0115] After step S740, the method further includes:

[0116] Step S810, please refer to Figure 13 , forming an etched opening 50 extending along a second direction and penetrating the substrate 100 in the bit line 600 region A3, the second direction intersecting the first direction, and a plane defined by the second direction and the first direction intersecting the extension direction of the capacitor hole 11;

[0117] Step S820, please continue to refer to Figure 13 , the second isolation layer 220 is laterally etched from the etched opening 50 to form a bit line trench 60 extending along the second direction and exposing the channel layer 510 ;

[0118] Step S830, please refer to Figure 14 , forming a bit line 600 in the bit line trench 60 .

[0119] In step S810, refer to Figure 13 A third patterned photoresist may be formed on the upper surface of the structure obtained after forming the gate dielectric layer 520 and the word line 530. The third patterned photoresist may have a third opening, which may be located in the bit line 600 region A3 and extend along the second direction.

[0120] Then, etching can be performed based on the third patterned photoresist to form an etched opening 50 extending along the second direction and penetrating the substrate 100. Thereafter, the third patterned photoresist is removed.

[0121] In step S820, refer to Figure 13 The second isolation layer 220 located between the first isolation layers 210 can be etched back from the self-etched opening 50 by wet etching or the like, thereby forming a bit line trench 60 extending along the second direction and exposing the channel layer 510 .

[0122] The lateral etching depth of the second isolation layer 220 from the word line hole 30 is H4, the lateral etching depth of the second isolation layer 220 from the etched opening 50 is H6, and the shortest distance between the etched opening 50 and the word line hole 30 along the first direction is H7. (H6+H4)>=H7 can be set so that the bit line trench 60 can expose the channel layer 510.

[0123] In step S830, refer to Figure 14 After the bit line 600 is formed in the bit line trench 60 , the bit line 600 extends along the second direction. Since the bit line trench 60 exposes the channel layer 510 , the bit line 600 can be connected to the channel layer 510 , thereby allowing the other of the source region and the drain region of the transistor 500 to be connected to the bit line 600 .

[0124] As an example, after step S830, the method further includes:

[0125] In step S840 , an insulating dielectric layer is filled in the etched opening 50 .

[0126] The insulating dielectric layer may be protected by, but is not limited to, a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), or a silicon oxynitride layer (SiON).

[0127] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0128] In one embodiment, see Figure 14 The present invention also provides a semiconductor structure, which includes a substrate 100 , a first isolation layer 210 , a second isolation layer 220 , a first capacitor electrode 310 , a second capacitor electrode 330 , and a capacitor dielectric layer 320 .

[0129] The substrate 100 may be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. For example, the substrate 100 may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 100 may also include a Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator substrate.

[0130] Meanwhile, the substrate 100 may be a single-layer structure or a multi-layer structure. When the substrate 100 comprises a multi-layer structure, it may include a substrate and other structures or film layers formed on the substrate.

[0131] The first isolation layer 210 and the second isolation layer 220 are alternately stacked and disposed on the substrate 100. The first isolation layer 210 and the second isolation layer 220 are made of different materials. The first isolation layer 210 may include, but is not limited to, silicon oxide. The second isolation layer 220 may include, but is not limited to, silicon nitride.

[0132] The second isolation layer 220 may have at least one layer. As an example, the semiconductor structure may have multiple first isolation layers 210 and multiple second isolation layers 220. Each second isolation layer 220 may have a first isolation layer 210 on both sides. This facilitates the formation of a three-dimensional device.

[0133] The first capacitor electrode 310 can include at least two annular portions 311 arranged along a first direction. Adjacent annular portions 311 are connected to each other. Furthermore, the first capacitor electrode 310 and the second isolation layer 220 are both located between adjacent first isolation layers 210. Furthermore, the first capacitor electrode 310 is surrounded by the second isolation layer 220.

[0134] The material of the first capacitor electrode 310 may include, but is not limited to, titanium nitride (TiN). For example, the material of the first capacitor electrode 310 may also include indium tin oxide (ITO). For another example, the material of the first capacitor electrode 310 may also include molybdenum (MO), tantalum titanium (TaTi), tungsten nitride (WN), etc.

[0135] The second capacitor electrode 330 and the capacitor dielectric layer 320 are both surrounded by the annular portion 311. Each surrounding portion of the first capacitor electrode 310 can contain the second capacitor electrode 330 and the capacitor dielectric layer 320. The capacitor dielectric layer 320 is located between the second capacitor electrode 330 and the first capacitor electrode 310.

[0136] The second capacitor electrode 330 penetrates the alternately stacked first isolation layer 210 and second isolation layer 220 and extends to the substrate 100. The capacitor dielectric layer 320 is located on the sidewalls of the second capacitor electrode 330. As an example, the capacitor dielectric layer 320 can also be located at the bottom of the second capacitor electrode 330. The first capacitor electrode 310, the capacitor dielectric layer 320 opposite thereto, and the second capacitor electrode 330 can form a capacitor 300.

[0137] As an example, the second capacitor electrode 330 may include an electrode layer 331 and a filling conductive layer 332. The material of the electrode layer 331 may include, but is not limited to, titanium nitride (TiN). For example, the material of the electrode layer 331 may also include indium tin oxide (ITO). For another example, the material of the electrode layer 331 may also include molybdenum (MO), tantalum titanium (TaTi), tungsten nitride (WN), etc. The material of the filling conductive layer 332 may include, but is not limited to, silicon germanium (SiGe) or doped polycrystalline silicon.

[0138] At the same time, the shortest distance between adjacent capacitor dielectric layers 320 in the first direction is H1, the width of the first capacitor electrode 310 in the second direction is H2, H2>=0.5H1, the second direction intersects with the first direction, and the plane determined by the second direction and the first direction intersects with the extension direction of the capacitor sub-hole 11.

[0139] In this embodiment, the first capacitor electrode 310 and the second isolation layer 220 are both located between adjacent first isolation layers 210. Furthermore, the first capacitor electrode 310 is enclosed by the second isolation layer 220. In this case, the first isolation layer 210 and the second isolation layer 220 can be used to insulate and isolate the capacitor. Therefore, during the fabrication of the semiconductor structure of this embodiment, there is no need to etch and form isolation trenches. Therefore, this embodiment can effectively reduce the process difficulty of fabricating memory devices, especially three-dimensional memory devices, and can effectively prevent capacitor misconnection, thereby improving device performance.

[0140] Furthermore, the first capacitor electrode 310 can include at least two annular portions 311 arranged along a first direction. Adjacent annular portions 311 are interconnected. A second capacitor electrode 330 and a capacitor dielectric layer 320 can be located within each surrounding portion of the first capacitor electrode 310. Therefore, the first capacitor electrode 310, the plurality of second capacitor electrodes 330, and the capacitor dielectric layer 320 can collectively form a capacitor, thereby effectively increasing the capacitance of the capacitor.

[0141] In one embodiment, the semiconductor structure includes a plurality of first capacitor electrodes 310 spaced apart along the second direction. A second capacitor electrode 330 and a capacitor dielectric layer 320 may be located within each surrounding portion of each first capacitor electrode 310 .

[0142] The shortest distance between the capacitor dielectric layers 320 adjacent to each other along the second direction is H3, and H3>2H2.

[0143] In one embodiment, H3>=3H2. In the second direction, the width of the second isolation layer 220 between adjacent first capacitor electrodes 310 is greater than or equal to H2, thereby ensuring reliable isolation of adjacent capacitors along the second direction.

[0144] In one embodiment, a capacitor region and a transistor region arranged along a first direction are provided on the substrate 100 . The first capacitor electrode 310 is located in the capacitor region. A transistor 500 connected to the first capacitor electrode 310 is provided in the transistor region.

[0145] The transistor 500 includes a word line 530 , a gate dielectric layer 520 , and a channel layer 510 .

[0146] The word line 530 extends through the first isolation layer 210 and the second isolation layer 220 to the substrate 100 and is disposed opposite the first capacitor electrode 310 in the first direction. The gate dielectric layer 520 is located on the sidewalls of the word line 530. As an example, the gate dielectric layer 520 can also be located at the bottom of the word line 530.

[0147] The word line 530 may include a metal diffusion barrier layer 531 and a metal layer 532. The metal diffusion barrier layer 531 may be located between the gate dielectric layer 520 and the metal layer 532. The metal diffusion barrier layer 531 may include, but is not limited to, ITO or titanium nitride. The material of the metal layer 532 may include, but is not limited to, tungsten (W).

[0148] The material of the gate dielectric layer 520 may include, but is not limited to, a high dielectric constant material layer.

[0149] The material of the channel layer 510 may include, but is not limited to, indium gallium zinc oxide (IGZO).

[0150] The channel layer 510 , the first capacitor electrode 310 , and the second isolation layer 220 are all located between adjacent first isolation layers 210 . The channel layer 510 is connected to the first capacitor electrode 310 and is wrapped by the second isolation layer 220 . The channel layer 510 surrounds the gate dielectric layer 520 .

[0151] In one embodiment, a bit line 600 region is further provided on the substrate 100 . The transistor region is located between the capacitor region and the bit line 600 region in the first direction. A bit line 600 is provided in the bit line 600 region.

[0152] The bit line 600, the channel layer 510, the first capacitor electrode 310 and the second isolation layer 220 are all located between adjacent first isolation layers 210. The bit line 600 and the first capacitor electrode 310 are respectively connected to both sides of the channel layer 510. Furthermore, the bit line 600 extends along the second direction.

[0153] As an example, the semiconductor structure may further include an insulating dielectric layer. The insulating dielectric layer is located on a side of the bit line 600 away from the transistor region.

[0154] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0155] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, and forming a first isolation layer and a second isolation layer alternately stacked on the substrate; Etching the first isolation layer and the second isolation layer to form a capacitor hole group, wherein the capacitor hole group includes at least two capacitor sub-holes arranged at intervals along a first direction and extending to the substrate; performing side etching on the second isolation layer from the capacitor hole to form a first surrounding groove surrounding the capacitor hole; forming a first capacitor electrode extending along the first direction and filling the first surrounding groove; A capacitor dielectric layer is formed on the sidewall and bottom of the capacitor hole, and a second capacitor electrode is formed on the surface of the capacitor dielectric layer.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The shortest distance between the capacitor sub-holes adjacent to each other along the first direction in the same capacitor sub-hole group is H1, and the etching depth of the second isolation layer lateral-etched from the capacitor sub-hole is H2, where H2>=0.5H1.

3. The method for preparing a semiconductor structure according to claim 2, wherein: The forming of the capacitor hole group penetrating the stacked structure includes: forming a plurality of capacitor hole groups spaced apart along a second direction, wherein the second direction intersects the first direction, and a plane defined by the second direction and the first direction intersects an extension direction of the capacitor holes; Furthermore, the shortest distance between the capacitor sub-holes adjacent to each other along the second direction is H3, and H3>2H2.

4. The method for preparing a semiconductor structure according to claim 3, wherein: H3>=3H2.

5. The method for preparing a semiconductor structure according to claim 1 or 2, wherein: The substrate is provided with a capacitor region and a transistor region arranged along the first direction, and the capacitor hole group is located in the capacitor region. The etching of the first isolation layer and the second isolation layer to form a capacitor hole group also forms a word line hole arranged opposite to the capacitor hole group in the first direction, wherein the word line hole is located in the transistor region and extends to the substrate; Before the side etching of the second isolation layer from the capacitor quantum hole, the method further includes: filling a sacrificial layer in the word line hole; After forming a capacitor dielectric layer on the sidewall and bottom of the capacitor sub-hole and forming a second capacitor electrode on the surface of the capacitor dielectric layer, the method further includes: removing the sacrificial layer located in the word line hole; performing side etching on the second isolation layer from the word line hole to form a second surrounding groove surrounding the word line hole, wherein the second surrounding groove exposes the first capacitor electrode; forming a channel layer in the second surrounding trench; A gate dielectric layer is formed on the sidewall of the word line hole, and a word line is formed on the surface of the gate dielectric layer.

6. A semiconductor structure, characterized in that include: substrate; A first isolation layer and a second isolation layer alternately stacked on the substrate; a first capacitor electrode comprising at least two annular portions arranged along a first direction, adjacent annular portions being connected to each other, and the first capacitor electrode being located between adjacent first isolation layers and being wrapped by the second isolation layer; a second capacitor electrode, surrounded by the annular portion, penetrating the alternately stacked first isolation layers and second isolation layers and extending to the substrate; a capacitor dielectric layer, surrounded by the annular portion, located between the second capacitor electrode and the first capacitor electrode, and located on a sidewall of the second capacitor electrode; In which, the shortest distance between adjacent capacitor dielectric layers in the first direction is H1, the width of the first capacitor electrode in the second direction is H2, H2>=0.5H1, the second direction intersects with the first direction, and the plane determined by the second direction and the first direction intersects with the extension direction of the second capacitor electrode.

7. The semiconductor structure according to claim 6, wherein: The semiconductor structure includes a plurality of first capacitor electrodes arranged at intervals along the second direction, and the shortest distance between adjacent capacitor dielectric layers along the second direction is H3, where H3>2H2.

8. The semiconductor structure according to claim 7, wherein: H3>=3H2.

9. The semiconductor structure according to claim 6, wherein: A capacitor region and a transistor region are provided on the substrate and arranged along the first direction, the first capacitor electrode is located in the capacitor region, and a transistor connected to the first capacitor electrode is provided in the transistor region; The transistor includes: a word line, penetrating the first isolation layer and the second isolation layer and extending to the substrate, and arranged opposite to the first capacitor electrode in the first direction; a gate dielectric layer, located on a sidewall of the word line; The channel layer is located between adjacent first isolation layers, connected to the first capacitor electrode, and wrapped by the second isolation layer. The channel layer surrounds the gate dielectric layer.

10. The semiconductor structure according to claim 9, wherein: A bit line region is further provided on the substrate. The transistor region is located between the capacitor region and the bit line region in the first direction. A bit line is provided in the bit line region. The bit line is located between adjacent first isolation layers, and the bit line and the first capacitor electrode are respectively connected to two sides of the channel layer, and the bit line extends along the second direction.

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