Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate and m word lines. The substrate comprises a plurality of discrete active region columns; the plurality of active region columns are positioned on the front surface of the substrate and extend along the vertical direction; and the plurality of active region columns are arranged along the first direction and the second direction to form an array with m rows and n columns. The m word lines extend in the first direction and are arranged in the second direction; wherein the (2i-1) th word line and the (2i) th word line are located in the first groove between the (2i-1) th row of active region columns and the (2i) th row of active region columns, and cover the side walls of the corresponding active region columns respectively; and an air gap is formed between the (2i-1) th word line and the 2i th word line.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a semiconductor structure and a method for forming the same. Background Art

[0002] 3D stacking technology is to form three-dimensional integration in the vertical direction by using stacking technology or through interconnection and other micro-machining technologies. 3D stacking technology can package more than two chips with different functions in the original package, thereby realizing the functional diversification of the chip. In related technologies, the structure of the chip used for stacking still has room for further optimization. Summary of the invention

[0003] In view of this, the embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which can improve integration and electrical performance.

[0004] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] An embodiment of the present disclosure provides a semiconductor structure, which includes: a substrate, including a plurality of discrete active area columns; the plurality of active area columns are located on the front side of the substrate and extend in a vertical direction; the plurality of active area columns are arranged in a first direction and a second direction to form an array of m rows and n columns; wherein m and n are both greater than 1, and the first direction and the second direction intersect and are respectively perpendicular to the vertical direction; m word lines extend in the first direction and are arranged in the second direction; wherein the 2i-1th and 2ith word lines are located in a first groove between the 2i-1th and 2ith row active area columns and respectively cover the side walls of the corresponding active area columns; there is an air gap between the 2i-1th and 2ith word lines; wherein i is greater than or equal to 1 and less than m / 2.

[0006] In the above scheme, the semiconductor structure also includes: multiple isolation structures, extending along the first direction and arranged in sequence along the second direction; multiple isolation structures are located in the second trench between the active area columns in the 2i-th row and the 2i+1-th row; the depth of the second trench is greater than the depth of the first trench.

[0007] In the above solution, the semiconductor structure further includes: a gate oxide layer formed between each of the word lines and the side wall of the corresponding active area column.

[0008] In the above scheme, the semiconductor structure also includes: a plurality of node contact structures, each of which is located at the top of a corresponding active area column; and a plurality of bit line contact structures, the bottom ends of every two active area columns are connected to a corresponding bit line contact structure.

[0009] In the above scheme, the semiconductor structure further includes: n bit lines extending along the second direction and located on the back side of the substrate; each of the bit lines is electrically connected to the bottom end of a corresponding column of the active region pillars through the bit line contact structure.

[0010] In the above solution, the semiconductor structure further includes: a plurality of capacitors; each of the capacitors is electrically connected to the top of a corresponding active region column through a node contact structure.

[0011] In the above solution, the angle between the first direction and the second direction is 60°; and the plurality of capacitors are arranged in a honeycomb shape.

[0012] In the above solution, the semiconductor structure further includes: a dielectric layer, covering the top ends of the plurality of active region pillars and surrounding the side walls of the plurality of node contact structures.

[0013] In the above solution, the semiconductor structure further includes: a pad structure, which is located on the back side of the substrate and is electrically connected to the corresponding bit line.

[0014] The present disclosure also provides a method for forming a semiconductor structure, the method comprising: providing a substrate; forming a plurality of initial active region columns extending in a vertical direction on the front side of the substrate; forming an array of m / 2 rows and n columns of the plurality of initial active region columns along a first direction and a second direction; forming a shallow trench isolation structure between adjacent initial active region columns; wherein m and n are both greater than 1, and the first direction and the second direction are respectively perpendicular to the vertical direction; etching the shallow trench isolation structure to form a first trench extending in the first direction between two adjacent rows of the initial active region columns; wherein the remaining A shallow trench isolation structure covers the side walls of the initial active area column to form a gate oxide layer; m word lines extending along the first direction are formed; wherein the 2i-1th and 2ith word lines are formed in a corresponding first trench and respectively cover the corresponding side walls of the initial active area column; wherein i is greater than or equal to 1 and less than m / 2; in the middle of each row of the initial active area columns, a second trench extending along the first direction is etched to divide each row of the initial active area columns into two rows of active area columns; a dielectric layer is deposited to cover the top of the active area column and an air gap is formed between the 2i-1th and 2ith word lines.

[0015] In the above scheme, after depositing the dielectric layer to cover the top of the active area column, the method also includes: forming a patterned mask on the dielectric layer; etching the dielectric layer according to the mask to form a plurality of through holes in the dielectric layer; each of the through holes exposes the top of a corresponding active area column; depositing a plurality of node contact structures in the plurality of through holes; each of the node contact structures is connected to the top of a corresponding active area column; forming a plurality of capacitors; each of the capacitors is electrically connected to the top of a corresponding active area column through a node contact structure.

[0016] In the above scheme, after forming multiple capacitors, the method also includes: thinning the back side of the substrate; forming multiple bit line contact structures at the bottom ends of multiple active area columns; connecting the bottom ends of every two active area columns to a corresponding bit line contact structure; filling metal material into the substrate from the back side of the substrate to form n bit lines; each bit line is electrically connected to the bottom end of a corresponding column of active area columns through the bit line contact structure.

[0017] In the above solution, after forming n bit lines and a plurality of bit line contact structures, the method further comprises: forming a pad structure on the back side of the substrate; the pad structure is electrically connected to the corresponding bit line.

[0018] In the above scheme, forming m word lines extending along the first direction includes: filling the first trench with word line conductive material; etching the word line conductive material in each first trench to cut the word line conductive material into two parts to form two word lines.

[0019] In the above solution, after etching to form the second trench, the method further includes: depositing a dielectric material in the second trench to form an isolation structure extending along the first direction.

[0020] It can be seen that the embodiment of the present disclosure provides a semiconductor structure and a method for forming the same. The semiconductor structure includes: a substrate and m word lines. The substrate includes a plurality of discrete active area columns; the plurality of active area columns are located on the front side of the substrate and extend in a vertical direction; the plurality of active area columns are arranged in a first direction and a second direction to form an array of m rows and n columns; wherein m and n are both greater than 1, and the first direction and the second direction intersect and are respectively perpendicular to the vertical direction. The m word lines extend in a first direction and are arranged in a second direction; wherein the 2i-1th and 2ith word lines are located in the first groove between the 2i-1th and 2ith rows of active area columns and cover the side walls of the corresponding active area columns respectively; there is an air gap between the 2i-1th and 2ith word lines; wherein i is greater than or equal to 1 and less than m / 2. It can be understood that the embodiment of the present disclosure sets an array of active area pillars, and then sets the 2i-1th and 2ith word lines in the first trench between the 2i-1th and 2ith rows of active area pillars, and sets an air gap between the 2i-1th and 2ith word lines 20. In this way, the 2i-1th and 2ith word lines with a smaller spacing are electrically isolated by using an air gap with better insulation and lower dielectric constant. At the same time, the spacing between the 2ith and 2i+1th word lines is enlarged, so that the parasitic capacitance C between each two adjacent word lines is wl That is, the embodiment of the present disclosure does not need to increase the spacing between adjacent active area pillars, so that the overall area occupied by the semiconductor structure is small, and at the same time, the parasitic capacitance C between adjacent word lines is guaranteed. wl That is, the embodiment of the present disclosure provides a semiconductor structure with high integration and good electrical performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0022] Figure 2 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 2 ;

[0023] Figure 3 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 3 ;

[0024] Figure 4 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 4 ;

[0025] Figure 5 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 5 ;

[0026] Figure 6 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 6 ;

[0027] Figure 7 A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 1 ;

[0028] Figure 8 A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 2 ;

[0029] Fig. 9 A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 3 ;

[0030] Fig. 10A A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 1 ;

[0031] Fig. 10B A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 2 ;

[0032] Fig.11A A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 3 ;

[0033] Fig. 11B A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 4 ;

[0034] Fig. 12A A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 5 ;

[0035] Fig. 12B A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 6 ;

[0036] Fig.13A A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 7 ;

[0037] Fig. 13B A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 8 ;

[0038] Fig.14A A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 9 ;

[0039] Fig. 14B Structural schematic diagram 10 of a method for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0040] Fig.15 Structural schematic diagram eleven of a method for forming a semiconductor structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0042] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0043] If similar descriptions of "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0044] In this document, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element or there can be an intervening layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, it may be "under" the other layer / element when the orientation is reversed.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0046] Figure 1 and Figure 2 is an optional structural diagram of a semiconductor structure provided by an embodiment of the present disclosure, wherein: Figure 1 is a top view, Figure 2 For along Figure 1 Sectional view of the center line A-A1.

[0047] like Figure 1and Figure 2 As shown, the semiconductor structure includes: a substrate 00 and m word lines 20. The substrate 00 includes a plurality of discrete active region pillars 10. The plurality of active region pillars 10 are located on the front side of the substrate 00 and extend along a vertical direction Z. The plurality of active region pillars 10 are arranged along a first direction X and a second direction Y to form an array of m rows and n columns. Wherein, m and n are both greater than 1, and the first direction X and the second direction Y intersect and are respectively perpendicular to the vertical direction Z.

[0048] The m word lines 20 extend along the first direction X and are arranged along the second direction Y. The 2i-1th and 2ith word lines 20 are located in the first trench between the 2i-1th and 2ith active area pillars 10 and cover the sidewalls of the corresponding active area pillars 10, respectively. An air gap 30 is provided between the 2i-1th and 2ith word lines 20. Wherein, i is greater than or equal to 1 and less than m / 2.

[0049] In the embodiments of the present disclosure, reference Figure 1 and Figure 2 The substrate 00 is made of semiconductor materials, such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. The substrate 00 includes a plurality of discrete active region pillars 10, each of which can form a corresponding transistor; thus, the plurality of active region pillars 10 arranged in an array can form an array of transistors.

[0050] In the present disclosure, continue to refer to Figure 1 and Figure 2 , the 2i-1th and 2ith word lines 20 are located in the first trench between the 2i-1th and 2ith rows of active area pillars 10, and cover the side walls of the corresponding active area pillars 10 respectively. That is to say, every two word lines 20 are located in the first trench between the corresponding two rows of active area pillars 10; here, each row of active area pillars 10 is arranged along the first direction X. At the same time, each word line 20 covers the side walls of the corresponding row of active area pillars 10; in this way, the portion of the active area pillars 10 covered by the word lines 20 can form a channel of a transistor, and the voltage on the word lines 20 can control the opening or closing of the channel.

[0051] For further information, please refer to Figure 1 and Figure 2 , m word lines 20 are arranged along the second direction Y, and the spacing between two adjacent word lines 20 is different. On the one hand, the spacing between the 2ith word line 20 and the 2i+1th word line 20 (i.e., two adjacent word lines 20 located in different first trenches) is larger, so the parasitic capacitance C between the 2ith word line 20 and the 2i+1th word line 20 is wlOn the other hand, if the spacing between the 2i-1st and 2i-th word lines 20 (i.e., two adjacent word lines 20 in the same first trench) is small, an air gap 30 is provided between the 2i-1st and 2i-th word lines 20. Compared with general dielectrics, the air gap 30 has better insulation and lower dielectric constant, so that the parasitic capacitance C between the 2i-1st and 2i-th word lines 20 can be reduced. wl Also kept to a small scale.

[0052] It can be understood that the embodiment of the present disclosure provides a novel semiconductor structure, in which active area pillars 10 arranged in an array are provided, and then, the 2i-1th and 2ith word lines 20 are provided in the first trench between the 2i-1th and 2ith rows of active area pillars 10, and an air gap 30 is provided between the 2i-1th and 2ith word lines 20. In this way, the 2i-1th and 2ith word lines 20 with a smaller spacing are electrically isolated by using the air gap 30 with better insulation and lower dielectric constant, and at the same time, the spacing between the 2ith and 2i+1th word lines 20 is enlarged, so that the parasitic capacitance C between each two adjacent word lines is wl All are kept in a small range.

[0053] That is to say, the embodiment of the present disclosure does not need to increase the spacing between adjacent active region pillars 10, so that the overall occupied area of ​​the semiconductor structure is small, and at the same time, the parasitic capacitance C between adjacent word lines is guaranteed. wl That is, the embodiment of the present disclosure provides a semiconductor structure with high integration and good electrical performance.

[0054] In some embodiments of the present disclosure, reference Figure 1 and Figure 2 The semiconductor structure further includes: a plurality of isolation structures 40. The plurality of isolation structures 40 extend along the first direction X and are sequentially arranged along the second direction Y. The plurality of isolation structures 40 are located in the second trench between the 2i-th row and the 2i+1-th row of active region pillars 10. The depth of the second trench is greater than the depth of the first trench.

[0055] In the present disclosure, continue to refer to Figure 1 and Figure 2 The air gap 30 is located in the first trench between the 2i-1th row and the 2ith row of active area pillars 10, that is, the air gap 30 is located between the 2i-1th and 2ith word lines 20; and the isolation structure 40 is located in the second trench between the 2ith row and the 2i+1th row of active area pillars 10, that is, the isolation structure 40 is located between the 2ith and 2i+1th word lines 20.

[0056] It can be understood that the air gap 30 and the isolation structure 40 are arranged at intervals in the second direction Y; among them, between the word lines 20 with smaller spacing (i.e., between the 2i-1th and 2ith word lines 20), the air gap 30 with better insulation and lower dielectric constant is used; and between the word lines 20 with larger spacing (i.e., between the 2ith and 2i+1th word lines 20), the isolation structure 40 is used; thereby, the parasitic capacitance C between the word lines 20 is guaranteed. wl Keep it small.

[0057] At the same time, compared with the air gap 30, the isolation structure 40 has stronger stability and can provide good support for the entire semiconductor structure; thus, the spaced air gap 30 and the isolation structure 40 can also take into account the stability of the entire semiconductor structure and avoid collapse or structural damage.

[0058] In the present disclosure, continue to refer to Figure 1 and Figure 2 The depth of the second trench where the isolation structure 40 is located is greater than the depth of the first trench where the air gap 30 is located. In this way, the isolation structure 40 can better isolate the active area pillars 10 in different rows to avoid short circuits and crosstalk.

[0059] In some embodiments of the present disclosure, reference Figure 2 The semiconductor structure further includes a gate oxide layer 11. The gate oxide layer 11 is formed between each word line 20 and the side wall of the corresponding active area column 10. In this way, the voltage on the word line 20 can be used as the gate voltage of the transistor to control the opening or closing of the channel in the active area column 10.

[0060] It can be understood that the word line 20 covers the sidewall of the active region pillar 10 to control the opening or closing of the channel; in this way, the contact area between the word line 20 and the channel is larger, thereby increasing the control force on the channel, making the opening or closing of the channel more thorough; furthermore, the on-state current I of the transistor can be increased. on , and reduce the transistor's off current I off , thereby reducing power consumption.

[0061] Figure 3 An optional schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure, Figure 3 It is a cross-sectional view.

[0062] In some embodiments of the present disclosure, reference Figure 3The semiconductor structure further includes: a plurality of node contact structures (Node Contact, NC) 12 and a plurality of bit line contact structures (Bit Line Contact, BLC) 13. Each node contact structure 12 is located at the top of a corresponding active area column 10; and the bottom ends of every two active area columns 10 are connected to a corresponding bit line contact structure 13.

[0063] It can be understood that, on the one hand, multiple node contact structures 12 and multiple bit line contact structures 13 are respectively arranged at the top and bottom ends of the active area column 10 (i.e., the front and back sides of the substrate), so that there is enough space to arrange the node contact structures 12 and the bit line contact structures 13, and the node contact structures 12 and the bit line contact structures 13 can be designed to be larger in size, thereby reducing the resistance of the node contact structures 12 and the bit line contact structures 13, and then reducing the power consumption of the entire semiconductor structure. On the other hand, since the node contact structures 12 and the bit line contact structures 13 are respectively arranged at the two ends of the active area column 10, in the manufacturing process, the node contact structures 12 and the bit line contact structures 13 can be processed from the two ends respectively without interfering with each other, thereby simplifying the manufacturing process.

[0064] In the present disclosure, continue to refer to Figure 3 , the bottom ends of every two active area pillars 10 are connected to a corresponding bit line contact structure 13. Compared with each active area pillar corresponding to a bit line contact structure, the size of each bit line contact structure 13 can be made larger in the embodiment of the present disclosure; thus, on the one hand, the resistance of the bit line contact structure 13 itself is lower, and on the other hand, the contact surface between the bit line contact structure 13 and the bit line is larger; thus, the power consumption of the entire semiconductor structure is reduced.

[0065] Figure 4 and Figure 5 is an optional structural diagram of a semiconductor structure provided by an embodiment of the present disclosure, wherein: Figure 4 is a top view, Figure 5 For along Figure 4 The sectional view of the middle section line A-A1. It should be noted that Figure 4 Due to shielding relationships, the middle portion of each bit line 50 is shielded and not shown.

[0066] In some embodiments of the present disclosure, reference Figure 4 and Figure 5 The semiconductor structure further includes: n bit lines 50. The n bit lines 50 extend along the second direction Y and are located on the back side of the substrate. Each bit line 50 is electrically connected to the bottom end of a corresponding column of active region pillars 10 through a bit line contact structure 13.

[0067] It can be understood that the bit line 50 is set on the back side of the substrate. In this way, during the manufacturing process, the bit line can be cut from the back side, and there is no need to set an array boundary. The size of each unit can be designed to be smaller; thereby, on the one hand, the integration level can be improved, and on the other hand, it is easier to arrange various areas in chip design, reducing the design difficulty.

[0068] Figure 6 is an optional structural diagram of a semiconductor structure provided by an embodiment of the present disclosure, Figure 6 It is a cross-sectional view.

[0069] In some embodiments of the present disclosure, reference Figure 6 The semiconductor structure further includes: a plurality of capacitors 60. Each capacitor 60 is electrically connected to the top of a corresponding active region pillar 10 through a node contact structure 12.

[0070] In the disclosed embodiment, the capacitor 60 may be a sleeve capacitor. The lower plate in each capacitor 60 is electrically connected to the top of a corresponding active region column 10. In this way, the active region column 10 forms a transistor, and then one end of the source or drain of the transistor is connected to the lower plate in the capacitor 60, thereby forming a 1T1C (1Transistor-1Capacitor) storage unit.

[0071] In some embodiments of the present disclosure, reference Figure 1 or Figure 4 , the angle between the first direction X and the second direction Y can be 60°. Figure 6 The multiple capacitors 60 in the semiconductor device can be arranged in a honeycomb shape. In this way, on the one hand, the cross-sectional size of each capacitor 60 can be increased, thereby increasing the capacity of each capacitor 60; on the other hand, the stability of the entire semiconductor structure is also made stronger.

[0072] In some embodiments of the present disclosure, reference Figure 5 The semiconductor structure further includes a dielectric layer 41. The dielectric layer 41 covers the tops of the plurality of active region pillars 10 and surrounds the sidewalls of the plurality of node contact structures 12 to electrically isolate different node contact structures 12.

[0073] In some embodiments of the present disclosure, reference Figure 6 The semiconductor structure further includes a pad structure 70. The pad structure 70 is located on the back side of the substrate and is electrically connected to the corresponding bit line 50. The pad structure 70 can be bonded to the corresponding pad of other chips, for example, hybrid bonding of the memory chip and the logic chip, thereby realizing a 3D stacking structure.

[0074] It should be noted that FIG. 10A to FIG. 15 The intermediate structure in the method for forming a semiconductor structure provided by the embodiment of the present disclosure is shown, which is used to describe and clearly illustrate the steps of the method for forming a semiconductor structure. Fig. 10A , Fig.11A , Fig. 12A , Fig.13A and Fig.14A is a top view, Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B and Fig. 14B It is the corresponding cross-sectional view (the cross-sectional line is A-A1).

[0075] Figure 7 An optional flow chart of a method for forming a semiconductor structure provided in an embodiment of the present disclosure. Figure 7 As shown, the method for forming a semiconductor structure includes S101 to S105, which will be described in combination with each step.

[0076] S101. Provide a substrate; a plurality of initial active area columns extending along the vertical direction are formed on the front side of the substrate; the plurality of initial active area columns form an array of m / 2 rows and n columns along a first direction and a second direction; a shallow trench isolation structure is formed between adjacent initial active area columns; wherein m and n are both greater than 1, and the first direction and the second direction are respectively perpendicular to the vertical direction.

[0077] In the embodiments of the present disclosure, reference Fig. 10A and Fig. 10B , a plurality of initial active region pillars 01 extending along the vertical direction Z on the front side of the substrate 00. The plurality of initial active region pillars 01 form an array of m / 2 rows and n columns along the first direction X and the second direction Y. Among them, each row of initial active region pillars 01 is arranged along the first direction X, and each column of initial active region pillars 01 is arranged along the second direction Y. The first direction X and the second direction Y are respectively perpendicular to the vertical direction Z.

[0078] Continue to refer Fig. 10A and Fig. 10B A shallow trench isolation structure 42 is formed between adjacent initial active region pillars 01. The shallow trench isolation structure 42 is made of a dielectric material (such as semiconductor oxide) to electrically isolate different initial active region pillars 01.

[0079] S102, etching the shallow trench isolation structure to form a first trench extending along a first direction between two adjacent rows of initial active area pillars; wherein the remaining shallow trench isolation structure covers the sidewalls of the initial active area pillars to form a gate oxide layer.

[0080] In the embodiment of the present disclosure, Fig. 10A and Fig. 10BThe shallow trench isolation structure 42 is etched to form a first trench extending along the first direction X between two adjacent rows of initial active area pillars 01. Fig.11A and Fig. 11B The remaining shallow trench isolation structure 42 covers the sidewalls of the initial active area pillar 01 to form a gate oxide layer 11.

[0081] S103, forming m word lines extending along the first direction; wherein the 2i-1th and 2ith word lines are formed in a corresponding first trench and respectively cover the side walls of the corresponding initial active area column; wherein i is greater than or equal to 1 and less than m / 2.

[0082] In the embodiments of the present disclosure, reference Fig.11A and Fig. 11B , a word line 20 extending along the first direction X can be formed in the first trench. Wherein, every two word lines 20 are formed in a corresponding first trench, each word line 20 covers the side wall of the corresponding initial active area column 01, and the gate oxide layer 11 is located between the word line 20 and the side wall of the initial active area column 01.

[0083] In some embodiments of the present disclosure, the following steps can be performed to form Fig.11A and Fig. 11B The word line 20 shown in the figure: first, the word line conductive material is filled in the first trench; then, in each first trench, the word line conductive material is etched to cut the word line conductive material into two parts, thereby forming two word lines 20. In this way, two word lines 20 are formed in one first trench, and a gap is formed at the position where the etching is cut, and then an air gap can be formed.

[0084] S104 , etching to form a second trench extending along the first direction in the middle of each row of initial active area columns, so as to divide each row of initial active area columns into two rows of active area columns.

[0085] In the embodiment of the present disclosure, after the word line 20 is formed, Fig.11A and Fig. 11B The middle of each row of initial active area pillars 01 is etched to form a second groove extending along the first direction X; thus, Fig.11A and Fig. 11B Each row of initial active area column 01 is divided into Fig. 12A and Fig. 12B There are two rows of active area pillars 10. Among them, the initial active area pillar 01 located at the edge does not cover the word line 20 on its outer side; therefore, after it is etched and divided into two halves, only the half covering the word line 20 serves as the active area pillar 10.

[0086] That is to say, Fig.11A and Fig. 11BEach initial active area column 01 in is divided into Fig. 12A and Fig. 12B Thus, the plurality of active area pillars 10 form an array of m rows and n columns along the first direction X and the second direction Y.

[0087] At the same time, the 2i-1th and 2ith word lines 20 are located in the first trench between the 2i-1th and 2ith active area pillars 10, and respectively cover the sidewalls of the corresponding active area pillars 10. The portion of the active area pillar 10 covered by the word line 20 can form a channel of a transistor, and the voltage on the word line 20 can control the opening or closing of the channel.

[0088] It can be understood that the word line 20 covers the sidewall of the active region pillar 10 to control the opening or closing of the channel; in this way, the contact area between the word line 20 and the channel is larger, thereby increasing the control force on the channel, making the opening or closing of the channel more thorough; furthermore, the on-state current I of the transistor can be increased. on , and reduce the transistor's off current I off , thereby reducing power consumption.

[0089] In some embodiments of the present disclosure, reference Fig. 12A and Fig. 12B After etching to form the second trenches and dividing each row of initial active area pillars into two corresponding rows of active area pillars 10 , a dielectric material may be deposited in the second trenches to form an isolation structure 40 extending along the first direction X.

[0090] It can be understood that the isolation structure 40 is located between the 2ith and 2i+1th active area pillars 10, and between the 2ith and 2i+1th word lines 20. Between the word lines 20 with a larger spacing (i.e., between the 2ith and 2i+1th word lines 20), the isolation structure 40 is used to ensure that the parasitic capacitance C between the word lines 20 is wl At the same time, the isolation structure 40 can play a good supporting role for the entire semiconductor structure, thereby ensuring the stability of the entire semiconductor structure.

[0091] In the present disclosure, continue to refer to Fig. 12B The depth of the second trench where the isolation structure 40 is located is greater than the depth of the first trench where the air gap 30 is located. In this way, the isolation structure 40 can better isolate the active area pillars 10 in different rows to avoid short circuits and crosstalk.

[0092] S105 , depositing a dielectric layer to cover the top of the active region pillar and forming an air gap between the 2i-1th and 2ith word lines.

[0093] In the embodiments of the present disclosure, reference Fig. 12A and Fig. 12B After forming the word line 20, a dielectric layer can be deposited to cover the top of the active region pillar 10, so that an air gap 30 is formed between the 2i-1th and 2ith word lines (i.e., between the word lines 20 located in the same first trench). Compared with general dielectrics, the air gap 30 has better insulation and lower dielectric constant, so that the 2i-1th word line can be -1 The parasitic capacitance C between the first and second word lines 20 is wl Keep it small.

[0094] It can be understood that the embodiment of the present disclosure forms a novel semiconductor structure, in which active area pillars 10 arranged in an array are provided, and then the 2i-1th and 2ith word lines 20 are provided in the first trench between the 2i-1th and 2ith rows of active area pillars 10, and an air gap 30 is provided between the 2i-1th and 2ith word lines 20. In this way, the 2i-1th and 2ith word lines 20 with a smaller spacing are electrically isolated by using the air gap 30 with better insulation and lower dielectric constant, and at the same time, the spacing between the 2ith and 2i+1th word lines 20 is enlarged, so that the parasitic capacitance C between each two adjacent word lines is wl All are kept in a small range.

[0095] That is to say, the embodiment of the present disclosure does not need to increase the spacing between adjacent active region pillars 10, so that the overall occupied area of ​​the semiconductor structure is small, and at the same time, the parasitic capacitance C between adjacent word lines is guaranteed. wl That is, the embodiment of the present disclosure forms a semiconductor structure with high integration and good electrical performance.

[0096] In some embodiments of the present disclosure, Figure 7 After S105, the method for forming a semiconductor structure further includes Figure 8 S106 to S109 shown will be described in conjunction with each step.

[0097] S106 , forming a patterned mask on the dielectric layer.

[0098] S107 , etching the dielectric layer according to the mask to form a plurality of through holes in the dielectric layer; each through hole exposes the top of a corresponding active region column.

[0099] S108. Depositing a plurality of node contact structures in the plurality of through holes; each node contact structure is connected to a top end of a corresponding active region column.

[0100] In the embodiments of the present disclosure, reference Fig.13A and Fig. 13BThe node contact structure 12 is formed at the top of the active area pillar 10, and each node contact structure 12 is connected to the top of a corresponding active area pillar 10. The dielectric layer 41 covers the top of each active area pillar 10 and surrounds the sidewalls of each node contact structure 12 to electrically isolate different node contact structures 12.

[0101] S109, forming a plurality of capacitors; each capacitor is electrically connected to the top of a corresponding active region column through a node contact structure.

[0102] In the present disclosure, continue to refer to Fig.13A and Fig. 13B A plurality of capacitors 60 are formed above the dielectric layer 41. Each capacitor 60 is electrically connected to the top of a corresponding active region pillar 10 through a node contact structure 12.

[0103] In the disclosed embodiment, the capacitor 60 may be a sleeve capacitor. The lower plate in each capacitor 60 is electrically connected to the top of a corresponding active region column 10. In this way, the active region column 10 forms a transistor, and then one end of the source or drain of the transistor is connected to the lower plate in the capacitor 60, thereby forming a 1T1C storage unit.

[0104] In some embodiments of the present disclosure, reference Fig.13A , the angle between the first direction X and the second direction Y can be 60°. Accordingly, in a top view, the plurality of capacitors 60 can be arranged in a honeycomb shape. In this way, on the one hand, the cross-sectional size of each capacitor 60 can be increased, thereby increasing the capacity of each capacitor 60; on the other hand, the stability of the entire semiconductor structure is also made stronger.

[0105] In some embodiments of the present disclosure, Figure 8 After S109, the method for forming a semiconductor structure further includes Fig. 9 S110 to S112 shown will be described in conjunction with each step.

[0106] S110, performing a thinning process on the back side of the substrate.

[0107] S111, forming a plurality of bit line contact structures at the bottom ends of the plurality of active area pillars; the bottom ends of every two active area pillars are connected to a corresponding bit line contact structure.

[0108] S112, filling metal material into the substrate from the back side of the substrate to form n bit lines; each bit line is electrically connected to the bottom end of a corresponding column of active region pillars through a bit line contact structure.

[0109] In the embodiments of the present disclosure, reference Fig.14A and Fig. 14BOn the back side of the substrate, n bit lines 50 extending along the second direction Y are formed. In this way, in the manufacturing process, there is no need to set an array boundary, and the size of each unit can be designed to be smaller; thus, on the one hand, the integration can be improved, and on the other hand, it is easier to arrange various areas in chip design, reducing the design difficulty.

[0110] In the embodiments of the present disclosure, reference Fig. 14B , the bottom ends of every two active area pillars 10 are connected to a corresponding bit line contact structure 13. Each bit line 50 is electrically connected to the bottom ends of a corresponding column of active area pillars 10 through the bit line contact structure 13. Compared with each active area pillar corresponding to a bit line contact structure, the size of each bit line contact structure 13 can be made larger in the embodiment of the present disclosure; in this way, on the one hand, the resistance of the bit line contact structure 13 itself is lower, and on the other hand, the contact surface between the bit line contact structure 13 and the bit line is larger, and the contact resistance is lower. At the same time, the size of the bit line contact structure 13 is larger, which improves the sensing ability of the bit line to the device. In summary, the power consumption of the entire semiconductor structure is reduced.

[0111] It can be understood that, on the one hand, multiple node contact structures 12 and multiple bit line contact structures 13 are respectively arranged at the top and bottom ends of the active area column 10 (i.e., the front and back sides of the substrate), so that there is enough space to arrange the node contact structures 12 and the bit line contact structures 13, and the node contact structures 12 and the bit line contact structures 13 can be designed to be larger in size, thereby reducing the resistance of the node contact structures 12 and the bit line contact structures 13, and then reducing the power consumption of the entire semiconductor structure. On the other hand, since the node contact structures 12 and the bit line contact structures 13 are respectively arranged at the two ends of the active area column 10, in the manufacturing process, the node contact structures 12 and the bit line contact structures 13 can be processed from the two ends respectively without interfering with each other, thereby simplifying the manufacturing process.

[0112] In some embodiments of the present disclosure, Fig. 9 After S113 shown, the method for forming a semiconductor structure further includes S114, which will be described in combination with each step.

[0113] S114 , forming a pad structure on the back side of the substrate; the pad structure is electrically connected to the corresponding bit line.

[0114] In the embodiments of the present disclosure, reference Fig.15After the bit line 50 is formed on the back side of the substrate, a pad structure 70 may be formed on the back side of the substrate. The pad structure 70 is electrically connected to the corresponding bit line 50. The pad structure 70 may be bonded to the corresponding pad of other chips, for example, hybrid bonding of a memory chip and a logic chip, thereby realizing a 3D stacking structure.

[0115] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0116] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0117] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises: A substrate, comprising a plurality of discrete active region pillars; the plurality of active region pillars are located on the front side of the substrate and extend in a vertical direction; the plurality of active region pillars are arranged in a first direction and a second direction to form an array of m rows and n columns; wherein m and n are both greater than 1, and the first direction and the second direction intersect and are respectively perpendicular to the vertical direction; m word lines extend along the first direction and are arranged along the second direction; wherein the 2i-1th and 2ith word lines are located in the first groove between the 2i-1th and 2ith active area columns, and respectively cover the side walls of the corresponding active area columns; there is an air gap between the 2i-1th and 2ith word lines; wherein i is greater than or equal to 1 and less than m / 2.

2. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: A plurality of isolation structures extend along the first direction and are sequentially arranged along the second direction; the plurality of isolation structures are located in the second trench between the active area pillars in the 2i-th row and the 2i+1-th row.

3. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: A gate oxide layer is formed between each of the word lines and the sidewall of the corresponding active region column.

4. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: A plurality of node contact structures, each of the node contact structures being located at a top end of a corresponding active region column; A plurality of bit line contact structures, the bottom ends of every two active area pillars are connected to a corresponding one of the bit line contact structures.

5. The semiconductor structure according to claim 4, characterized in that: The semiconductor structure further includes: n bit lines extending along the second direction and located on the back side of the substrate; each of the bit lines is electrically connected to the bottom end of a corresponding column of active region pillars through the bit line contact structure.

6. The semiconductor structure according to claim 4, characterized in that: The semiconductor structure further includes: a plurality of capacitors; Each of the capacitors is electrically connected to the top of a corresponding active region column through a node contact structure.

7. The semiconductor structure according to claim 6, characterized in that: The angle between the first direction and the second direction is 60°; The plurality of capacitors are arranged in a honeycomb shape.

8. The semiconductor structure according to claim 4, characterized in that: The semiconductor structure further comprises: The dielectric layer covers the tops of the plurality of active region pillars and surrounds the side walls of the plurality of node contact structures.

9. The semiconductor structure according to claim 5, characterized in that: The semiconductor structure further comprises: The pad structure is located on the back side of the substrate and is electrically connected to the corresponding bit line.

10. A method for forming a semiconductor structure, characterized in that: The forming method comprises: A substrate is provided; a plurality of initial active region columns extending in a vertical direction are formed on the front side of the substrate; the plurality of initial active region columns form an array of m / 2 rows and n columns along a first direction and a second direction; a shallow trench isolation structure is formed between adjacent initial active region columns; wherein m and n are both greater than 1, and the first direction and the second direction are respectively perpendicular to the vertical direction; Etching the shallow trench isolation structure to form a first trench extending along the first direction between two adjacent rows of the initial active area pillars; wherein the remaining shallow trench isolation structure covers the sidewalls of the initial active area pillars to form a gate oxide layer; Forming m word lines extending along the first direction; wherein the 2i-1th and 2ith word lines are formed in corresponding first trenches and respectively cover the sidewalls of the corresponding initial active area pillars; wherein i is greater than or equal to 1 and less than m / 2; In the middle of each row of the initial active area columns, a second groove extending along the first direction is formed by etching to divide each row of the initial active area columns into two rows of active area columns; A dielectric layer is deposited to cover the top of the active area pillar and to form an air gap between the 2i-1th and 2ith word lines.

11. The method for forming a semiconductor structure according to claim 10, characterized in that: After depositing the dielectric layer to cover the top of the active area column, the method further includes: forming a patterned mask on the dielectric layer; According to the mask, the dielectric layer is etched to form a plurality of through holes in the dielectric layer; each of the through holes exposes a top end of a corresponding active region column; Depositing a plurality of node contact structures in the plurality of through holes; each of the node contact structures is connected to a top end of a corresponding active region column; A plurality of capacitors are formed; each of the capacitors is electrically connected to the top of a corresponding active region column through a node contact structure.

12. The method for forming a semiconductor structure according to claim 11, characterized in that: After forming a plurality of the capacitors, the method further comprises: Performing a thinning process on the back side of the substrate; A plurality of bit line contact structures are formed at the bottom ends of the plurality of active area pillars; the bottom ends of every two active area pillars are connected to a corresponding one of the bit line contact structures; Metal material is filled into the substrate from the back side of the substrate to form n bit lines; each of the bit lines is electrically connected to the bottom end of a corresponding column of active region pillars through the bit line contact structure.

13. The method for forming a semiconductor structure according to claim 12, wherein: After forming n bit lines and a plurality of bit line contact structures, the method further includes: A pad structure is formed on the back side of the substrate; the pad structure is electrically connected to the corresponding bit line.

14. The method for forming a semiconductor structure according to claim 10, wherein: Forming m word lines extending along the first direction, comprising: Filling the first trench with a word line conductive material; In each of the first trenches, the word line conductive material is etched to cut the word line conductive material into two parts to form two word lines.

15. The method for forming a semiconductor structure according to claim 10, wherein: After etching to form the second groove, the method further includes: A dielectric material is deposited in the second trench to form an isolation structure extending along the first direction.

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