Semiconductor structure and preparation method thereof, and three-dimensional memory and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a three-dimensional memory and a preparation method thereof, a memory system and electronic equipment, relates to the technical field of semiconductor chips, and aims to reduce the temperature in a bonding layer preparation process. The preparation method of the semiconductor structure comprises the following steps: forming a device layer on a substrate; depositing silicon nitride on one side, far away from the substrate, of the device layer to form an initial bonding layer; doping the initial bonding layer by adopting an ion implantation process to form a middle bonding layer; and carrying out dehydrogenation treatment on the middle bonding layer to form a bonding layer. The preparation method is used for preparing the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and a method for preparing the same, a three-dimensional memory and a method for preparing the same, a storage system and an electronic device. Background Art

[0002] As the feature size of the memory cell approaches the process limit, the planar process and manufacturing technology become challenging and costly, which causes the storage density of 2D or planar NAND flash memory to approach the upper limit. To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND). The storage density is increased by arranging the memory cells three-dimensionally on the substrate.

[0003] Among them, the three-dimensional memory with X-Tacking architecture prepares the memory array and the peripheral circuit on two wafers respectively, and forms bonding layers on the memory array and the peripheral circuit respectively, and then bonds the bonding layers of the memory array and the peripheral circuit through a bonding process to form an integral structure of the memory array and the peripheral circuit. Among them, how to prepare the bonding layer under low temperature conditions to reduce the adverse effects of high temperature on the memory array and the peripheral circuit is a problem that needs to be solved urgently. Summary of the invention

[0004] Embodiments of the present disclosure provide a semiconductor structure and a method for preparing the same, a three-dimensional memory and a method for preparing the same, a storage system, and an electronic device, aiming to reduce the temperature during the preparation of a bonding layer.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, a method for preparing a semiconductor structure is provided. The method comprises: forming a device layer on a substrate; depositing silicon nitride on a side of the device layer away from the substrate to form an initial bonding layer; doping the initial bonding layer using an ion implantation process to form an intermediate bonding layer; and performing a dehydrogenation treatment on the intermediate bonding layer to form a bonding layer.

[0007] The method for preparing a semiconductor structure provided by the above-mentioned embodiment of the present disclosure adopts silicon nitride to prepare a bonding layer. Among them, the initial bonding layer formed by depositing silicon nitride includes more hydrogen atoms (compared to the bonding layer). The initial bonding layer is doped by an ion implantation (ion bombardment) process, and a hydrogen escape channel can be formed in the initial bonding layer, which is conducive to accelerating the separation of hydrogen atoms from the intermediate bonding layer. Based on this, the temperature during the dehydrogenation treatment of the intermediate bonding layer can be reduced, thereby reducing the impact of the high temperature environment on the semiconductor structure.

[0008] In some embodiments, the dehydrogenation treatment of the intermediate bonding layer includes: degassing the intermediate bonding layer at 300° C. to 420° C.

[0009] In some embodiments, the dehydrogenation treatment of the intermediate bonding layer includes: subjecting the intermediate bonding layer to ultraviolet light irradiation treatment at 300° C. to 420° C.

[0010] In some embodiments, the doping the initial bonding layer by ion implantation includes: implanting nitrogen ions into the initial bonding layer.

[0011] In some embodiments, the step of doping the initial bonding layer by ion implantation further comprises: implanting arsenic ions and / or carbon ions into the initial bonding layer.

[0012] In some embodiments, the ratio of the number of nitrogen atoms to the number of silicon atoms in the bonding layer is 1.6 to 2.0.

[0013] In some embodiments, depositing silicon nitride on the side of the device layer away from the substrate includes: depositing silicon nitride by plasma enhanced chemical vapor deposition, wherein the reaction gas includes silane and ammonia. The concentration of hydrogen atoms in the bonding layer is (1E 19 ~1E 20 )atoms / cm 3 .

[0014] In some embodiments, the bonding layer includes a first sub-portion and a second sub-portion. The first sub-portion includes silicon nitride. The second sub-portion is farther from the substrate than the first sub-portion, and the second sub-portion includes silicon nitride and doping ions. The ratio of the size of the first sub-portion along the direction perpendicular to the substrate to the size of the second sub-portion along the direction perpendicular to the substrate is 1 / 4 to 1 / 3.

[0015] In some embodiments, the density of the first subsection is less than the density of the second subsection.

[0016] In some embodiments, after the bonding layer is formed, the method further includes: forming a mask layer on a side of the bonding layer away from the substrate; etching the bonding layer and a portion of the device layer using the mask layer as a mask to form a contact hole; preparing a conductive material in the contact hole to form a bonding contact; and removing the mask layer.

[0017] In some embodiments, the conductive material includes copper.

[0018] On the other hand, a method for preparing a three-dimensional memory is provided. The preparation method comprises: using the preparation method of the semiconductor structure described in any of the above embodiments to prepare a first semiconductor structure and a second semiconductor structure; bonding the first semiconductor structure and the second semiconductor structure in a face-to-face manner so that the first bonding layer and the second bonding layer are bonded. The first semiconductor structure comprises a first substrate and a first device layer and a first bonding layer sequentially arranged in a direction away from the first substrate, and the first device layer comprises a peripheral circuit. The second semiconductor structure comprises a second substrate and a second device layer and a second bonding layer sequentially arranged in a direction away from the second substrate, and the second device layer comprises a storage array.

[0019] In another aspect, a semiconductor structure is provided. The semiconductor structure comprises a device layer and a bonding layer disposed on the device layer. The bonding layer comprises doped silicon nitride, and the concentration of hydrogen atoms in the doped silicon nitride is (1E 19 ~1E 20 )atoms / cm 3 .

[0020] In some embodiments, the doping ions for doping the silicon nitride include nitrogen ions.

[0021] In some embodiments, the doping ions for doping the silicon nitride further include arsenic ions and / or carbon ions.

[0022] In some embodiments, the ratio of the number of nitrogen atoms to the number of silicon atoms in the bonding layer is 1.6 to 2.0.

[0023] In some embodiments, the bonding layer includes a first sub-portion and a second sub-portion. The first sub-portion includes silicon nitride. The second sub-portion is farther from the device layer than the first sub-portion, and the second sub-portion includes silicon nitride and doping ions. The ratio of the size of the first sub-portion along the direction perpendicular to the substrate to the size of the second sub-portion along the direction perpendicular to the substrate is 1 / 4 to 1 / 3.

[0024] In some embodiments, the density of the first subsection is less than the density of the second subsection.

[0025] In another aspect, a three-dimensional memory is provided. The three-dimensional memory includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes the semiconductor structure described in any of the above embodiments. The first semiconductor structure includes a first device layer and a first bonding layer disposed on the first device layer; the first device layer includes a peripheral circuit. The second semiconductor structure includes the semiconductor structure described in any of the above embodiments. The second semiconductor structure includes a second device layer and a second bonding layer disposed on the second device layer, and the second device layer includes a memory array.

[0026] In another aspect, a storage system is provided, comprising the above three-dimensional memory and a controller, wherein the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0027] In another aspect, an electronic device is provided, wherein the electronic device comprises the above storage system.

[0028] It can be understood that the beneficial effects that can be achieved by the semiconductor structure, three-dimensional memory and its preparation method, storage system and electronic device provided by the above-mentioned embodiments of the present disclosure can refer to the beneficial effects of the preparation method of the semiconductor structure above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0030] Figure 1 is a flow chart for preparing a semiconductor structure according to some embodiments;

[0031] Figure 2 to Figure 10 is a process step diagram of a semiconductor structure according to some embodiments;

[0032] Fig.11 is a structural diagram of a second semiconductor structure according to some embodiments;

[0033] Fig.12 is a structural diagram of a three-dimensional memory according to some embodiments;

[0034] Fig.13 is a block diagram of a storage system according to some embodiments;

[0035] Fig.14 is another block diagram of a storage system according to some embodiments. DETAILED DESCRIPTION

[0036] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0037] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0038] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "some embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0039] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0040] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0041] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0042] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0043] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0044] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0045] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0046] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0047] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0048] The term "three-dimensional memory" refers to a semiconductor device formed by a string of memory cell transistors (referred to herein as a "memory cell string", such as a NAND memory cell string) arranged in an array on the main surface of a substrate or a source layer and extending in a direction perpendicular to the substrate or the source layer.

[0049] See also Figure 1 , Figure 1 The embodiment of the present disclosure provides a method for preparing a semiconductor structure, including S110 to S180.

[0050] S110, see Figure 2, a device layer 20 is formed on the substrate 10.

[0051] In the embodiments of the present disclosure, the substrate refers to a material on which subsequent material layers can be added. The substrate itself can be patterned. The material added to the substrate can be patterned or can remain unpatterned. In addition, the material of the substrate can include a variety of semiconductor materials such as silicon (e.g., single crystal silicon, polycrystalline silicon, doped polycrystalline silicon), germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0052] The device layer 20 may be any functional device layer formed on the substrate 10. For example, the device layer 20 may include a memory array and a peripheral circuit.

[0053] In some embodiments, the above-mentioned S110 of forming the device layer 20 on the substrate 10 includes S111 and S112 .

[0054] S111, such as Figure 2 As shown, a first device layer 21 is formed on a first substrate 11 .

[0055] Exemplarily, the first device layer may include a peripheral circuit, which may include a plurality of driving devices composed of a plurality of PMOS transistors or NMOS transistors for driving the memory array to work, and a peripheral interconnect layer disposed on a side of the driving device away from the substrate. After the plurality of driving devices are connected through the peripheral interconnect layer, a plurality of circuit function modules are formed to drive the memory array to work normally.

[0056] Exemplarily, step S111 is used to form a first semiconductor structure.

[0057] S112, forming a second device layer on the second substrate.

[0058] Exemplarily, the second device layer may include a memory array. The memory array includes a plurality of memory cell strings arranged in an array, and an array interconnect layer arranged on a side of the memory cell string away from the second substrate. The array interconnect layer is used to be electrically connected to the peripheral interconnect layer, so that the peripheral circuit can drive the memory cell string to work normally through the peripheral interconnect layer and the array interconnect layer.

[0059] Exemplarily, step S112 is used to form a second semiconductor structure.

[0060] It is understandable that the order of the above steps S111 and S112 can be exchanged, that is, the first device layer can be formed on the first substrate first, and then the second device layer can be formed on the second substrate. Alternatively, the second device layer can be formed on the second substrate first, and then the first device layer can be formed on the first substrate. Of course, the first device layer can also be formed on the first substrate and the second device layer can be formed on the second substrate simultaneously at different preparation sites.

[0061] In the following embodiments of the present disclosure, “S110, forming a device layer on a substrate” includes “S111, forming a first device layer on a first substrate” as an example to exemplify the present application.

[0062] S120, see Figure 3 , silicon nitride is deposited on the side of the device layer 20 away from the substrate 10 to form an initial bonding layer 31.

[0063] In the related technology, silicon carbonitride (SiCN), silicon dioxide (SiO 2 ) or silicon oxynitride (SiON) to form a bonding layer. During the bonding process of the bonding layer, the bonding contacts (Via) of the two semiconductor structures may be incompletely aligned, resulting in contact between the bonding contacts and the bonding interface. In the case where the material of the bonding layer is silicon carbonitride or oxide, the material of the bonding contact will diffuse to the bonding interface, and the electromigration (EM) of the bonding contact is high. In the case where the material of the bonding layer is silicon oxynitride, the bonding strength of the bonding layer is low, which may cause dicing or bonding failure between the peripheral interconnect layer and the array interconnect layer.

[0064] In order to solve the above technical problems, in the embodiments of the present disclosure, the material of the bonding layer is silicon nitride. Compared with other materials, the temperature of the silicon nitride material to form the bonding layer and the temperature of the bonding layer during the bonding process are relatively low (for example, lower than 420°C), which can reduce the adverse effects of the high temperature environment on the device layer (MOS transistor). Moreover, the bonding strength of the bonding layer formed by silicon nitride is greater than the bonding strength of the bonding layer formed by silicon oxynitride, so that the risk of slicing or bonding failure of the bonding structure can be reduced. In addition, the density of silicon nitride material is relatively large. During the bonding process, the degree of diffusion of the bonding contact (copper) in the silicon nitride material is less than that of the bonding contact in silicon carbonitride and oxide, which is beneficial to reduce the electromigration (EM) of the bonding interface.

[0065] In some embodiments, silicon nitride may be deposited by plasma enhanced chemical vapor deposition (PECVD), which is a method of forming a thin film by chemically reacting one or more gas phase compounds or single substances containing a thin film element (silicon nitride) on the surface of a substrate.

[0066] The reaction gas may include silane (such as monosilane SiH 4 and / or disilane Si 2 H 6 ) and ammonia (NH 3 ) In addition to producing silicon nitride (Si 3 N 4 ) will also generate a small amount of silane derivatives (such as SH 2 and SH 3 ). For example, in the initial bonding layer 31 formed by PECVD, the concentration of hydrogen atoms is (1E 22 ~1E 23 )atoms / cm 3 .

[0067] Silane derivatives will decompose to form hydrogen during the bonding process, which will then form bubbles in the bonding structure (the structure formed after the two bonding layers are bonded together), affecting the reliability of the bonding structure. How to dehydrogenate silicon nitride in a low-temperature environment is a key issue facing the application of silicon nitride in the bonding layer.

[0068] S130, see Figure 4 The initial bonding layer is doped using an ion implantation process to form an intermediate bonding layer 32 .

[0069] The ion implantation process is also known as ion bombardment. Figure 5 After the initial bonding layer is doped by ion implantation, multiple hydrogen escape channels 40 can be bombarded in the initial bonding layer. The hydrogen escape channels 40 are conducive to accelerating the separation of hydrogen atoms from the intermediate bonding layer 32, thereby reducing the temperature of the intermediate bonding layer during the dehydrogenation process, thereby reducing the impact of the high temperature environment on the semiconductor structure.

[0070] In some embodiments, the above-mentioned “doping the initial bonding layer by ion implantation” includes ion implantation of nitrogen ions into the initial bonding layer. In the process of ion implantation of nitrogen ions into the initial bonding layer, it is beneficial for the intermediate bonding layer 32 to form a nitrogen-rich structure, and it is beneficial for nitrogen atoms to replace hydrogen atoms, that is, it is beneficial for the silicon-hydrogen bond to break and form a silicon-nitrogen bond, which in turn helps the hydrogen atoms to separate from the intermediate bonding layer 32.

[0071] In some embodiments, after the initial bonding layer is ion-implanted with nitrogen ions, the ratio of the number of nitrogen atoms to the number of silicon atoms in the intermediate bonding layer 32 is 1.6 to 2.0. For example, the ratio of the number of nitrogen atoms to the number of silicon atoms can be 1.6, 1.65, 1.8, 1.9 or 2.0, etc., which are not listed here one by one.

[0072] It is understandable that the silicon nitride molecule (chemical formula: Si 3 N 4 ) is 4 / 3, which is about 1.3. After the nitrogen ions are implanted into the initial bonding layer, the ratio of the number of nitrogen atoms to the number of silicon atoms in the intermediate bonding layer 32 increases, and the intermediate bonding layer 32 forms a nitrogen-rich structure, which is conducive to the replacement of hydrogen atoms by nitrogen atoms, that is, it is conducive to the breaking of silicon-hydrogen bonds, and the formation of silicon-nitrogen bonds, which is conducive to the separation of hydrogen atoms from the intermediate bonding layer 32.

[0073] Nitrogen-rich silicon nitride (Si 4 N 4 ) can form a hexagonal spatial network structure as shown in the figure below, and form a covalent bond with copper (bonding contact), which is beneficial to reduce the diffusion of copper in silicon nitride and improve the electromigration (EM) life of the bonding interface.

[0074]

[0075] In some embodiments, the above-mentioned “doping the initial bonding layer by ion implantation” also includes “ion implantation of the initial bonding layer by arsenic ions and / or carbon ions”. The molecular weights of arsenic ions and carbon ions are greater than the molecular weight of nitrogen ions. Ion implantation of the initial bonding layer by arsenic ions and / or carbon ions is beneficial to the formation of the hydrogen escape channel 40 and increases the size of the hydrogen escape channel 40, which is beneficial to the separation of hydrogen atoms from the intermediate bonding layer 32 during the subsequent dehydrogenation process.

[0076] It can be understood that the hydrogen escape channel 40 is a visual display of ion implantation into the initial bonding layer, or in other words, the hydrogen escape channel 40 is a molecular-level microstructure that will not form grooves or holes on the surface of the bonding layer. Therefore, in the subsequent process of preparing a mask layer on the surface of the bonding layer, the material of the mask layer will not be filled into the above-mentioned hydrogen escape channel 40, nor will it affect the bonding ability and bonding effect of the bonding layer.

[0077] Exemplarily, the above-mentioned “doping the initial bonding layer using an ion implantation process” may include implanting nitrogen ions and arsenic ions into the initial bonding layer; or, may include implanting nitrogen ions and carbon ions into the initial bonding layer; or, may include implanting nitrogen ions, arsenic ions and carbon ions into the initial bonding layer.

[0078] In some embodiments, see Figure 4 The doping depth of the initial bonding layer can be 2 / 3 to 3 / 4 of the thickness of the initial bonding layer. In this way, it is possible to avoid the doping ions from being implanted into the device layer, thereby reducing the influence of the doping ions on the device layer.

[0079] S140, see Figure 6 , the intermediate bonding layer 32 is dehydrogenated to form a bonding layer 33.

[0080] The intermediate bonding layer 32 is subjected to a dehydrogenation treatment to reduce the concentration of hydrogen atoms in the bonding layer 33 and reduce the risk of bubbles being formed in the formed bonding layer 33 during the bonding process.

[0081] In some embodiments, S140 may include S141 or S142.

[0082] S141, degassing the intermediate bonding layer 32 at 300°C to 420°C.

[0083] S142, performing ultraviolet light irradiation treatment on the intermediate bonding layer 32 at 300°C to 420°C.

[0084] The intermediate bonding layer 32 includes a plurality of hydrogen escape channels 40, based on which the intermediate bonding layer 32 can be dehydrogenated at 300°C to 420°C, which can avoid the adverse effects of the high temperature environment on the device layer. Exemplarily, the intermediate bonding layer 32 can be degassed at 300°C, 350°C, 380°C, 405°C or 420°C. It is understandable that if the temperature is too low (for example, below 300°C), the hydrogen atoms in the intermediate bonding layer 32 will leave at a very low rate, and the amount of hydrogen atoms leaving is small. If the temperature is too high (for example, greater than 420°C), it may have an adverse effect on the device layer.

[0085] In some embodiments, the concentration of hydrogen atoms in the bonding layer 33 formed by dehydrogenation treatment is (1E 19 ~1E 20 )atoms / cm 3 Compared with the initial bonding layer 31 , the concentration of hydrogen atoms in the bonding layer 33 is reduced by more than 99%, which can greatly reduce the risk of bubbles being generated in the bonding layer 33 during the subsequent bonding process.

[0086] In some embodiments, the above-mentioned "dehydrogenation treatment of the intermediate bonding layer" will not affect the number of nitrogen atoms and the number of silicon atoms in the bonding layer. Based on this, the ratio of the number of nitrogen atoms to the number of silicon atoms in the bonding layer 33 is 1.6 to 2.0. Exemplarily, the ratio of the number of nitrogen atoms to the number of silicon atoms in the bonding layer 33 can be 1.6, 1.65, 1.8, 1.9 or 2.0, etc., which are not listed here one by one. The formation of a covalent bond between the silicon nitride with a nitrogen-rich structure and copper (bonding contact) is beneficial to reduce the diffusion of copper in silicon nitride and reduce the electromigration (EM) of the bonding interface.

[0087] In some embodiments, see Figure 6 , the bonding layer 33 includes a first sub-portion 331 and a second sub-portion 332. The first sub-portion 331 includes silicon nitride. The second sub-portion 332 is farther away from the substrate 10 than the first sub-portion 331, and the second sub-portion 332 includes silicon nitride and doping ions. In other words, when the initial bonding layer is ion-implanted, the upper portion of the initial bonding layer is ion-implanted, which can avoid the doping ions from being implanted into the device layer, thereby reducing the influence of the doping ions on the device layer.

[0088] Exemplarily, the ratio of the dimension D1 of the first sub-portion 331 along the direction Z perpendicular to the substrate to the dimension D2 of the second sub-portion 332 along the direction perpendicular to the substrate is 1 / 4 to 1 / 3. In other words, the depth of doping the initial bonding layer can be 2 / 3 to 3 / 4 of the thickness of the initial bonding layer.

[0089] In some embodiments, when arsenic ions and / or carbon ions are used to perform ion implantation on the initial bonding layer, arsenic ions and / or carbon ions with a larger molecular weight are added to the second sub-portion 332. Based on this, the density of the first sub-portion 331 is less than the density of the second sub-portion 332. The increased density of the second sub-portion is also beneficial to reducing the diffusion of copper in the bonding interface and reducing the electromigration (EM) of the bonding interface.

[0090] S150, see Figure 7 , a mask layer 50 is formed on a side of the bonding layer 33 away from the substrate 10 .

[0091] For example, a whole initial mask layer can be formed by using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any other thin film deposition process. Then, the initial mask layer is patterned by an etching process to form a plurality of openings 51 on the initial mask layer, thereby forming a mask layer 50. The openings 51 of the mask layer 50 expose a portion of the bonding layer 33.

[0092] By way of example, the material of the mask layer 50 may be silicon dioxide.

[0093] S160, see Figure 8 , using the mask layer 50 as a mask, the bonding layer 33 and a portion of the device layer 20 are etched to form a contact hole 61 .

[0094] Illustratively, the contact hole 61 may be formed by a wet etching process or a dry etching process.

[0095] S170, see Fig. 9 , a conductive material is prepared in the contact hole 61 to form a bonding contact 62 .

[0096] In some embodiments, the conductive material includes copper. As mentioned above, the material of the bonding layer 33 includes silicon nitride doped with nitrogen ions, so that the bonding layer 33 forms a nitrogen-rich structure, and a covalent bond can be formed between the silicon nitride and copper to reduce the electromigration (EM) of copper in the bonding layer.

[0097] In some other embodiments, the conductive material may also include one or more combinations of tungsten, cobalt, aluminum, and metal silicide.

[0098] S180, see Fig.10 , and remove the mask layer 50.

[0099] For example, the mask layer 50 may be removed by using a chemical mechanical polishing (CMP) process.

[0100] Some other embodiments of the present disclosure further provide a method for preparing a three-dimensional memory, which includes using the method for preparing a semiconductor structure described in S110 to S180 to form a first semiconductor structure 110 and a second semiconductor structure 120 .

[0101] See also Fig.10 The first semiconductor structure 110 includes a first substrate 11 and a first device layer 21 and a first bonding layer 33A sequentially arranged in a direction away from the first substrate 11. The first device layer 21 includes a peripheral circuit.

[0102] See also Fig.11 The second semiconductor structure 120 includes a second substrate 12 and a second device layer 22 and a second bonding layer 33B sequentially arranged in a direction away from the second substrate 12. The second device layer 22 includes a memory array. The memory array may include a plurality of memory cell strings 221 arranged in an array.

[0103] In some embodiments, the method for preparing a three-dimensional memory further includes S200.

[0104] S200, see Fig.12 The first semiconductor structure 110 and the second semiconductor structure 120 are bonded face to face, and the first bonding layer 33A and the second bonding layer 33B are bonded to form a three-dimensional memory 200 .

[0105] For example, the first bonding layer 33A and the second bonding layer 33B may be bonded using a surface activated bonding process.

[0106] Some other embodiments of the present disclosure also provide some semiconductor structures 100. In the following embodiments of the present disclosure, the semiconductor structure 100 including the first semiconductor structure 110 is taken as an example for description.

[0107] like Fig.10 As shown, the semiconductor structure 100 includes a device layer 20 and a bonding layer 33 disposed on the device layer 20. The material of the bonding layer 33 includes doped silicon nitride, and the concentration of hydrogen atoms in the doped silicon nitride is (1E 19 ~1E 20 )atoms / cm 3 , while the concentration of hydrogen atoms in undoped silicon nitride is (1E 22 ~1E 23 )atoms / cm 3 It can be seen that the concentration of hydrogen atoms in the doped silicon nitride is relatively small, so the risk of bubbles forming in the bonding layer 33 during the bonding process can be reduced.

[0108] In some embodiments, the doping ions of the doped silicon nitride include nitrogen ions, which is beneficial for the bonding layer 33 to form a nitrogen-rich structure and reduce the concentration of hydrogen atoms in the doped silicon nitride.

[0109] The ratio of the number of nitrogen atoms to the number of silicon atoms in the bonding layer is 1.6 to 2.0. For example, the ratio of the number of nitrogen atoms to the number of silicon atoms in the bonding layer 33 can be 1.6, 1.65, 1.8, 1.9 or 2.0, etc., which are not listed here. The nitrogen-rich silicon nitride forms a covalent bond with the copper (bonding contact), which is beneficial to reduce the diffusion of copper in the silicon nitride and reduce the electromigration (EM) of the bonding interface.

[0110] In some other embodiments, the doping ions doped with silicon nitride also include arsenic ions and / or carbon ions. Exemplarily, the doping ions doped with silicon nitride also include arsenic ions; or, the doping ions doped with silicon nitride also include carbon ions; or, the doping ions doped with silicon nitride also include arsenic ions and carbon ions. The molecular weights of arsenic ions and carbon ions are both greater than the molecular weight of nitrogen ions. Ion implantation of the initial bonding layer with arsenic ions and / or carbon ions is beneficial to the formation of hydrogen escape channels, and increases the size of the hydrogen escape channels, which is beneficial to the detachment of hydrogen atoms from the intermediate bonding layer during the subsequent dehydrogenation treatment.

[0111] like Fig.10 As shown, in some embodiments, the bonding layer 33 includes a first sub-portion 331 and a second sub-portion 332. The first sub-portion 331 includes silicon nitride. The second sub-portion 332 is farther away from the substrate 10 than the first sub-portion 331, and the second sub-portion 332 includes silicon nitride and doping ions. In other words, when the initial bonding layer is ion-implanted, the upper portion of the initial bonding layer is ion-implanted, which can avoid the doping ions from being implanted into the device layer, thereby reducing the influence of the doping ions on the device layer.

[0112] When arsenic ions and / or carbon ions are used for ion implantation into the initial bonding layer, arsenic ions and / or carbon ions with a larger molecular weight are added to the first sub-portion 331 , and therefore, the density of the first sub-portion 331 is less than that of the second sub-portion 332 .

[0113] Continue reading Fig.10 The ratio of the dimension D1 of the first sub-portion 331 along the direction Z perpendicular to the substrate 10 to the dimension D2 of the second sub-portion 332 along the direction perpendicular to the substrate is 1 / 4 to 1 / 3. In other words, the depth of doping the initial bonding layer can be 2 / 3 to 3 / 4 of the thickness of the initial bonding layer.

[0114] See also Fig.12 Some other embodiments of the present disclosure further provide a three-dimensional memory 200. The three-dimensional memory 200 includes the first semiconductor structure 110 and the second semiconductor structure 120 described above.

[0115] The first semiconductor structure 110 includes a first substrate 11 and a first device layer 21 and a first bonding layer 33A sequentially arranged in a direction away from the first substrate 11. The first device layer 21 includes a peripheral circuit. The second semiconductor structure 120 includes a second substrate 12 and a second device layer 22 and a second bonding layer 33B sequentially arranged in a direction away from the second substrate 12. The second device layer 22 includes a memory array. The memory array may include a plurality of memory cell strings 221 arranged in an array.

[0116] like Fig.13 and Fig.14As shown, some embodiments of the present disclosure further provide a storage system 400. The storage system includes the above-mentioned three-dimensional memory 200 and a controller 300. The controller 300 is coupled to the three-dimensional memory 200 to control the three-dimensional memory 200 to store data.

[0117] The storage system 400 may be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) or Embedded Multi Media Card (eMMC) package). That is, the storage system 400 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., mobile phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0118] In some embodiments, see Fig.13 , the storage system 400 includes a controller 300 and a three-dimensional memory 200, and the storage system 400 can be integrated into a memory card.

[0119] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0120] In other embodiments, see Fig.14 The storage system 400 includes a controller 300 and a plurality of three-dimensional memories 200 (not shown in the figure), and the storage system 400 is integrated into a solid state drive (SSD).

[0121] In the storage system 400, in some embodiments, the controller 300 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0122] In other embodiments, the controller 300 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0123] In some embodiments, the controller 300 may be configured to manage data stored in the three-dimensional memory 200 and communicate with an external device (e.g., a host). In some embodiments, the controller 300 may also be configured to control operations of the three-dimensional memory 200, such as read, erase, and program operations. In some embodiments, the controller 300 may also be configured to manage various functions regarding data stored or to be stored in the three-dimensional memory 200, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 300 is also configured to process error correction codes regarding data read from or written to the three-dimensional memory 200.

[0124] Of course, the controller 300 may also perform any other suitable functions, such as formatting the three-dimensional memory 200; for example, the controller 300 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0125] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0126] Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0127] The electronic device may include the storage system 400 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0128] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: forming a device layer on a substrate; Depositing silicon nitride on a side of the device layer away from the substrate to form an initial bonding layer; Doping the initial bonding layer by ion implantation to form an intermediate bonding layer; The intermediate bonding layer is subjected to a dehydrogenation treatment to form a bonding layer.

2. The preparation method according to claim 1, characterized in that: The dehydrogenation treatment of the intermediate bonding layer comprises: The intermediate bonding layer is subjected to a degassing treatment at a temperature of 300° C. to 420° C.

3. The preparation method according to claim 1, characterized in that: The dehydrogenation treatment of the intermediate bonding layer comprises: The intermediate bonding layer is subjected to ultraviolet light irradiation treatment at 300° C. to 420° C.

4. The preparation method according to any one of claims 1 to 3, characterized in that The step of doping the initial bonding layer by ion implantation comprises: The initial bonding layer is ion implanted with nitrogen ions.

5. The preparation method according to claim 4, characterized in that: The step of doping the initial bonding layer by ion implantation further comprises: Arsenic ions and / or carbon ions are used to perform ion implantation into the initial bonding layer.

6. The preparation method according to claim 4, characterized in that: The ratio of the number of nitrogen atoms to the number of silicon atoms in the bonding layer is 1.6 to 2.

0.

7. The preparation method according to any one of claims 1 to 3, characterized in that Depositing silicon nitride on a side of the device layer away from the substrate comprises: Silicon nitride is deposited by plasma enhanced chemical vapor deposition, and the reaction gases include silane and ammonia; Wherein, the concentration of hydrogen atoms in the bonding layer is (1E 19 ~1E 20 )atoms / cm 3 .

8. The preparation method according to claim 1, characterized in that: The bonding layer comprises: a first subsection, the first subsection comprising silicon nitride; A second sub-portion, which is farther from the substrate than the first sub-portion, and includes silicon nitride and doping ions; The ratio of the size of the first sub-portion along the direction perpendicular to the substrate to the size of the second sub-portion along the direction perpendicular to the substrate is 1 / 4 to 1 / 3.

9. The preparation method according to claim 8, characterized in that: The density of the first sub-portion is lower than the density of the second sub-portion.

10. The preparation method according to claim 1, characterized in that: After forming the bonding layer, the method further comprises: forming a mask layer on a side of the bonding layer away from the substrate; Using the mask layer as a mask, etching the bonding layer and a portion of the device layer to form a contact hole; Preparing a conductive material in the contact hole to form a bonding contact; The mask layer is removed.

11. The preparation method according to claim 10, characterized in that: The conductive material includes copper.

12. A method for preparing a three-dimensional memory, characterized in that: include: A first semiconductor structure and a second semiconductor structure are formed by using the preparation method according to any one of claims 1 to 11; the first semiconductor structure comprises a first substrate and a first device layer and a first bonding layer sequentially arranged in a direction away from the first substrate; the second semiconductor structure comprises a second substrate and a second device layer and a second bonding layer sequentially arranged in a direction away from the second substrate; wherein the first device layer comprises a peripheral circuit, and the second device layer comprises a memory array; The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, so that the first bonding layer and the second bonding layer are bonded.

13. A semiconductor structure, characterized in that: The semiconductor structure comprises a device layer and a bonding layer disposed on the device layer; the material of the bonding layer comprises doped silicon nitride, and the concentration of hydrogen atoms in the doped silicon nitride is (1E 19 ~1E 20 )atoms / cm 3 .

14. The semiconductor structure according to claim 13, characterized in that: The doping ions for doping the silicon nitride include nitrogen ions.

15. The semiconductor structure according to claim 14, characterized in that: The doping ions for doping silicon nitride further include arsenic ions and / or carbon ions.

16. The semiconductor structure according to claim 14, characterized in that The ratio of the number of nitrogen atoms to the number of silicon atoms in the bonding layer is 1.6 to 2.

0.

17. The semiconductor structure according to any one of claims 13 to 16, characterized in that: The bonding layer comprises: a first subsection, the first subsection comprising silicon nitride; A second sub-portion, which is farther away from the device layer than the first sub-portion, and includes silicon nitride and doping ions; The ratio of the size of the first sub-portion along the direction perpendicular to the substrate to the size of the second sub-portion along the direction perpendicular to the substrate is 1 / 4 to 1 / 3.

18. The semiconductor structure according to claim 17, characterized in that: The density of the first sub-portion is lower than the density of the second sub-portion.

19. A three-dimensional memory, characterized in that: include: A first semiconductor structure, the first semiconductor structure comprising the semiconductor structure according to any one of claims 13 to 18; the first semiconductor structure comprising a first device layer and a first bonding layer disposed on the first device layer; the first device layer comprising a peripheral circuit; A second semiconductor structure, the second semiconductor structure comprising the semiconductor structure according to any one of claims 13 to 18; the second semiconductor structure comprising a second device layer and a second bonding layer disposed on the second device layer, the second device layer comprising a memory array; Wherein, the first bonding layer is bonded to the second bonding layer.

20. A storage system, characterized in that: include: A three-dimensional memory, the three-dimensional memory comprising the three-dimensional memory according to claim 19; The controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

21. An electronic device, characterized in that: Comprising the storage system as claimed in claim 20.

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