Ferroelectric memory device based on multi-layer hafnium zirconium oxide film and manufacturing method thereof

Abstract

The invention provides a ferroelectric memory device based on a multi-layer hafnium zirconium oxide thin film and a manufacturing method of the ferroelectric memory device. The ferroelectric memory device comprises a dielectric layer (100), the dielectric layer (100) comprises ferroelectric films (200) and anti-ferroelectric films (300) which are alternately arranged, and the relationship between the thickness d1 of the adjacent ferroelectric films (200) and the thickness d2 of the anti-ferroelectric films (300) meets the following conditions: d1-d2 < = d1 / 2, and d1-d2 < = d2 / 2. The manufacturing method is used for manufacturing the ferroelectric memory device based on the multilayer hafnium zirconium oxide film. According to the invention, the thickness of the adjacent ferroelectric film and anti-ferroelectric film is reasonably set, so that the ferroelectric memory device has more excellent ferroelectricity.

Description

Technical Field

[0001] The present application relates to a memory, and in particular to a ferroelectric memory device based on a multi-layer hafnium zirconium oxide film and a manufacturing method thereof. Background Art

[0002] In this era of rapid information growth, personal computers, IoT devices, and artificial intelligence computing are generating large amounts of data all the time. Under the traditional von Neumann architecture, the separation of storage and computing directly leads to inefficient data transmission between memory and the central processing unit (CPU), resulting in problems such as memory wall and power consumption wall. Although dynamic random access memory (DRAM) and flash memory (NAND Flash) have developed rapidly in the past few decades, compared with digital computing chips such as CPUs, the process of memory chips is slower to shrink, and it is very difficult to improve device performance, and its shortcomings are becoming more and more obvious. Although DRAM has fast read and write speeds and low costs, it is a volatile memory that cannot save data after power failure, and because it needs to be refreshed all the time, the power consumption is relatively high, which limits its application in some low-power fields. For flash memory, the emergence of three-dimensional structure increases its density and significantly improves its performance. However, the problems of slow read and write speeds and poor durability still need to be improved.

[0003] Ferroelectric random access memory (FeRAM) has the advantages of low power consumption (<100fJ / bit), fast write speed (~10ns), long data retention time (more than 10 years) and good endurance (>10 14 The first generation of ferroelectric memory is based on perovskite-structured composite oxide ferroelectric films, such as PbZr x Ti 1- x O3 (PZT), BaTiO3 (BTO) and SrBi2Ta2O9 (SBT). However, due to the rapid decline of ferroelectricity of perovskite materials below 100nm process, the difficulty of realizing 3D structure and the poor compatibility with complementary metal oxide semiconductor (CMOS) process, the commercialization of ferroelectric memory is limited to the niche market with a technology node of 130nm. The second-generation ferroelectric memory is a ferroelectric film based on hafnium oxide (HfO2) film. The most common type of film is hafnium zirconium oxide (i.e., 50% zirconium oxide doped in hafnium oxide). Compared with the first-generation ferroelectric memory, the ferroelectric memory based on hafnium zirconium oxide can still show significant ferroelectricity when the thickness is less than 5nm, and it has good compatibility with CMOS process.

[0004] Although hafnium zirconium oxide-based ferroelectric memory has these advantages, it still faces some challenges in commercialization at 130nm or even more advanced processes. The biggest challenge at present is how to make the memory have good ferroelectricity at low voltage (below 1.8V) while having a good cycle life (durability). However, the improvement of memory durability under conventional processes is often accompanied by a decrease in residual polarization strength, which leads to a further decrease in the performance of the device at low voltage. This problem seriously limits the commercialization of hafnium oxide-based ferroelectric memory.

[0005] In the prior art, the thickness of the hafnium zirconium oxide film is generally reduced to improve its ferroelectricity and cycle life at low voltage. For example, the journal Acs Applied Materials & Interfaces, 2022, 14, 51137-51148 lists a method that uses a 4nm hafnium zirconium oxide film to prepare a film with certain ferroelectricity at low voltage (2Pr is about 23μC / cm 2 ) of ferroelectric capacitors, and the cycle life can reach 10 10 (The general cycle life is 10 cycles at 1.8V. 9 However, the ferroelectricity of the capacitor is still relatively small (2Pr of ferroelectric memory is less than 30μC / cm at 1.8V operating voltage). 2 ), the leakage current is large (the leakage current is about 10 at 1.2V working voltage). -5 A), the wake-up behavior is also more prominent, and it needs to be cycled at an additional high voltage to achieve early wake-up (about 2V), so it is still difficult to apply in the commercial field. Summary of the invention

[0006] The present application provides a ferroelectric memory device based on a multi-layer hafnium zirconium oxide film and a manufacturing method thereof.

[0007] The present application provides a ferroelectric memory device based on a multilayer hafnium zirconium oxide film, wherein the ferroelectric memory device includes a dielectric layer, wherein the dielectric layer includes alternating ferroelectric films and antiferroelectric films, and the relationship between the thickness d1 of the adjacent ferroelectric films and the thickness d2 of the antiferroelectric films satisfies: |d1-d2|≤d1 / 2, |d1-d2|≤d2 / 2.

[0008] In at least one embodiment, the dielectric layer includes a first ferroelectric film, a first antiferroelectric film, and a second ferroelectric film that are alternately arranged, and the thickness of the first antiferroelectric film is greater than the thickness of the first ferroelectric film and the thickness of the second ferroelectric film.

[0009] In at least one embodiment, the thickness of the first ferroelectric film and the second ferroelectric film is 2 nm, and the thickness of the first antiferroelectric film is 4 nm.

[0010] In at least one embodiment, the thickness of the ferroelectric thin film and the antiferroelectric thin film is no less than 1 nm.

[0011] In at least one embodiment, the thickness d of the dielectric layer satisfies: 3nm≤d≤20nm.

[0012] In at least one embodiment, the total number of layers of the ferroelectric thin film and the antiferroelectric thin film is no less than 3 layers.

[0013] In at least one embodiment, the ferroelectric memory device further includes metal electrodes disposed on both sides of the dielectric layer.

[0014] The method for manufacturing a ferroelectric memory device based on a multilayer hafnium zirconium oxide thin film provided in the present application is used to manufacture the aforementioned ferroelectric memory device based on a multilayer hafnium zirconium oxide thin film.

[0015] In at least one embodiment, the manufacturing method includes alternately disposing the ferroelectric thin film and the antiferroelectric thin film by deposition.

[0016] In at least one embodiment, the manufacturing method comprises:

[0017] Disposing a first metal electrode;

[0018] Setting the dielectric layer;

[0019] A second metal electrode is disposed on the dielectric layer.

[0020] The present application reasonably sets the thickness of adjacent ferroelectric films and antiferroelectric films, so that the ferroelectric memory device has better ferroelectricity. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of a ferroelectric memory device based on a multilayer hafnium zirconium oxide thin film according to an embodiment of the present application is shown.

[0022] Figure 2 An isometric view of a ferroelectric memory device based on a multilayer hafnium zirconium oxide thin film according to an embodiment of the present application is shown.

[0023] Figure 3 A comparison chart of test results of three examples of ferroelectric memory devices based on a multilayer hafnium zirconium oxide thin film according to an embodiment of the present application is shown.

[0024] Description of Reference Numerals

[0025] 100 dielectric layer; 200 ferroelectric film; 210 first ferroelectric film; 220 second ferroelectric film; 300 antiferroelectric film; 310 first antiferroelectric film; 410 first metal electrode; 420 second metal electrode. DETAILED DESCRIPTION

[0026] The exemplary embodiments of the present application are described below with reference to the accompanying drawings. It should be understood that these specific descriptions are only used to teach those skilled in the art how to implement the present application, and are not intended to exhaust all possible methods of the present application, nor to limit the scope of the present application.

[0027] The present application provides a ferroelectric memory device based on a multi-layer hafnium zirconium oxide thin film (hereinafter, sometimes simply referred to as a "ferroelectric memory device") and a method for manufacturing the same.

[0028] See also Figure 1 and Figure 2 The ferroelectric memory device may include a dielectric layer 100, wherein the dielectric layer includes a hafnium zirconium oxide film doped with hafnium (Hf) and zirconium (Zr). The hafnium zirconium oxide film may include a ferroelectric film 200 and an antiferroelectric film 300 that are alternately arranged, wherein the ferroelectric film 200 exhibits ferroelectricity, and the antiferroelectric film 300 exhibits antiferroelectricity.

[0029] For example, the hafnium zirconium oxide film can be controlled to have ferroelectricity or antiferroelectricity by controlling the doping ratio of hafnium and zirconium or the doping ratio of other elements (such as lanthanum (La) and cerium (Ce)) to form alternating ferroelectric films 200 and antiferroelectric films 300.

[0030] Compared with the prior art mentioned in the background technology, the ferroelectric memory of the present application can achieve better ferroelectricity (higher residual polarization strength, for example, 2Pr>30μC / cm at 1.8V) at an operating voltage of 1.8V or even lower. 2 ), excellent cycle life (10 cycles at 1.8V) 10 Above), strong data retention capability (10 5 After a few seconds, Pr only decays by 8%), small leakage current (the leakage current at 1.8V is about 10 -9 A), and the device does not require additional high voltage to wake up (only 1.8V voltage cycle 10 5 to wake up).

[0031] The reason why this solution can achieve good ferroelectricity includes the alternating arrangement of the ferroelectric film 200 and the antiferroelectric film 300. The interaction between the ferroelectric film 200 and the antiferroelectric film 300 will weaken the flipping barrier of the dipole in the ferroelectric film 200, thereby achieving the effect of reducing the coercive field (Ec). At the same time, the thickness of the ferroelectric film 200 in the dielectric layer 200 is reduced (compared to the existing solution in which the dielectric layer 100 has only the ferroelectric film), which will reduce the proportion of the non-ferroelectric m-phase (monoclinic phase) in the dielectric layer 100 and increase the proportion of the ferroelectric o-phase (orthogonal phase), so the ferroelectricity of the hafnium zirconium oxide film is improved, and high voltage awakening is not required.

[0032] Compared with the existing solution of reducing the overall thickness of the dielectric layer 100 (for example, the film thickness reaches 4nm), the present application does not seek to reduce the film thickness (for example, the film thickness can be maintained at 10nm). Therefore, the electric field strength of the present application at low voltage is not large, so the leakage current under the corresponding working state is extremely small.

[0033] Compared with conventional devices, the antiferroelectric film 300 introduced into the ferroelectric memory device of the present application is beneficial to reducing charge capture and electrostatic potential accumulation in the film, thereby optimizing the data retention capability of the ferroelectric device and enhancing its cycle life.

[0034] Furthermore, the relationship between the thickness d1 of the adjacent ferroelectric thin film 200 and the thickness d2 of the antiferroelectric thin film 300 satisfies: |d1-d2|≤d1 / 2, |d1-d2|≤d2 / 2. That is, the absolute value of the difference in thickness is not greater than 1 / 2 of any thickness, so that the difference in thickness between the ferroelectric thin film 200 and the antiferroelectric thin film 300 is kept within a certain range, so that the ferroelectric memory device has better ferroelectricity.

[0035] Furthermore, the dielectric layer 100 may include a first ferroelectric film 210 , a first antiferroelectric film 310 , and a second ferroelectric film 220 that are alternately arranged. The thickness of the first antiferroelectric film 310 may be greater than the thickness of the first ferroelectric film 210 and the thickness of the second ferroelectric film 220 .

[0036] In one example, the thickness of the first ferroelectric film 210 and the second ferroelectric film 220 may be 2 nm, and the thickness of the first antiferroelectric film 310 may be 4 nm. Under the condition that the dielectric layer 100 is formed into 3 layers and the total thickness of the dielectric layer 100 is 8 nm, the present application provides three groups of embodiments, which are tested respectively, and the results are as follows: Figure 3 shown.

[0037] Example 1

[0038] Number: x21. The first ferroelectric film 210 has a thickness of 1 nm, the first antiferroelectric film 310 has a thickness of 6 nm, and the second ferroelectric film 220 has a thickness of 1 nm.

[0039] Example 2

[0040] Number: x22. The first ferroelectric film 210 has a thickness of 2 nm, the first antiferroelectric film 310 has a thickness of 4 nm, and the second ferroelectric film 220 has a thickness of 2 nm.

[0041] Example 3

[0042] Number: x23. The first ferroelectric film 210 has a thickness of 3 nm, the first antiferroelectric film 310 has a thickness of 2 nm, and the second ferroelectric film 220 has a thickness of 3 nm.

[0043] Figure 3 (a) is a schematic diagram of the thickness combinations of the three groups of embodiments. The material of the metal electrodes (described later) on both sides of the dielectric layer 100 can be titanium nitride (TiN). FE-HZO represents a ferroelectric film 200 based on a hafnium zirconium oxide film, and AFE-HZO represents an antiferroelectric film 300 based on a hafnium zirconium oxide film.

[0044] Figure 3 (b) is the GIXRD (high energy X-ray diffraction) and Gaussian fitting results of the three groups of embodiments.

[0045] Figure 3 (c) is the phase component combination of three groups of embodiments.

[0046] Figure 3 (d) is the PV (polarization-voltage) curve of the initial state of the three groups of embodiments under 3V voltage (maximum voltage is 3V, the same below). The vertical axis Polarization represents the polarization intensity, and the horizontal axis Voltage represents the voltage. The vertical axis value corresponding to V=0 represents the residual polarization intensity Pr, which is used to evaluate ferroelectricity.

[0047] Figure 3 (e) is the PV curve of the three groups of embodiments after wake-up at a voltage of 3V.

[0048] Figure 3 (f) is the CV (dielectric capacitance-voltage) curve of the three groups of embodiments after awakening at a voltage of 3V.

[0049] Figure 3 (g) is the PV curve of Example 1 at 1.8V, 2.4V, and 3V (the maximum voltage is 1.8V, 2.4V, and 3V, the same below). The darkest line represents 3V, the second darkest line represents 2.4V, and the lightest line represents 1.8V (the same below).

[0050] Figure 3 (h) is the PV curve of Example 2 at voltages of 1.8V, 2.4V, and 3V.

[0051] Figure 3 (i) is the PV curve of Example 3 at voltages of 1.8V, 2.4V, and 3V.

[0052] In Example 1, |d1-d2| / d2=5 / 6, in Example 2, |d1-d2| / d2=1 / 2, and in Example 3, |d1-d2| / d1=1 / 3. Figure 3It can be seen from (g), (h), and (i) that the ferroelectricity of Examples 2 and 3, which are limited by the film thickness satisfying |d1-d2| / d1≤1 / 2 and |d1-d2| / d2≤1 / 2, is significantly greater than that of Example 1.

[0053] Furthermore, the ferroelectricity of the second embodiment, in which the thickness of the first antiferroelectric film 310 is greater than the thickness of the first ferroelectric film 210 and the thickness of the second ferroelectric film 220 , is superior to that of the third embodiment.

[0054] Therefore, it can be considered that the thickness distribution of each layer has an important influence on the ferroelectricity, and the ferroelectricity of the embodiments that meet the thickness limitation conditions provided in this application is stronger.

[0055] Furthermore, the thickness of the ferroelectric thin film 200 and the antiferroelectric thin film 300 may not be less than 1 nm.

[0056] Furthermore, the thickness d of the dielectric layer 100 may satisfy: 3 nm ≤ d ≤ 20 nm.

[0057] Furthermore, the total number of layers of the ferroelectric thin film 200 and the antiferroelectric thin film 300 is not less than 3 layers.

[0058] The inventors found that when the thickness of a single layer is less than 1 nm, the thickness of the single layer film will be less than 1 nm, and it is difficult to obtain such a thin and uniform film by, for example, ALD (atomic layer deposition). At the same time, as the number of layers inside the dielectric increases, the number of interfaces between the layers increases, and additional defects such as vacancies and stacking faults are introduced during the growth of the multilayer interface, which may have an adverse effect on the overall performance of the capacitor. The comprehensive limitation of the number of layers and thickness in this application can avoid these adverse effects.

[0059] In one embodiment of the present application, see Figure 2 The ferroelectric memory device may be a capacitor, and the ferroelectric memory device may further include metal electrodes disposed on both sides of the dielectric layer 100. Exemplarily, the metal electrodes may include a first metal electrode 410 located at the bottom of the dielectric layer 100 and a second metal electrode 420 located at the top of the dielectric layer 100. The first metal electrode 410 may be prepared by directly preparing a complete common electrode, or may be obtained by photolithography patterning to obtain a discrete electrode. Figure 2 The second metal electrode 420 can be obtained by photolithography patterning. Figure 2 The four rectangular blocks shown are only examples, and the present application does not limit the specific shape of the metal electrodes.

[0060] The manufacturing method of the ferroelectric memory device based on the multilayer hafnium zirconium oxide film provided in the present application may include sequentially disposing the first metal electrode 410, the dielectric layer 100, and the second metal electrode 420 by deposition. The ferroelectric film 200 and the antiferroelectric film 300 may be sequentially deposited.

[0061] When the second metal electrode 420 is disposed on the dielectric layer 100, a top electrode pattern may be formed by photolithography, and then a top electrode metal may be deposited, and then the photoresist may be removed to obtain a patterned second metal electrode 420. Alternatively, an electrode metal may be deposited first, and then a patterned second metal electrode 420 may be obtained by photolithography and etching.

[0062] The above is a preferred embodiment of the present application. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A ferroelectric memory device based on a multilayer hafnium zirconium oxide thin film, characterized in that: The ferroelectric memory device comprises a dielectric layer (100), wherein the dielectric layer (100) comprises ferroelectric films (200) and antiferroelectric films (300) arranged alternately, and the relationship between the thickness d1 of the adjacent ferroelectric films (200) and the thickness d2 of the antiferroelectric films (300) satisfies: |d1-d2|≤d1 / 2, |d1-d2|≤d2 / 2.

2. The ferroelectric memory device based on a multilayer hafnium zirconium oxide thin film according to claim 1, characterized in that: The dielectric layer (100) comprises a first ferroelectric film (210), a first antiferroelectric film (310) and a second ferroelectric film (220) which are alternately arranged, and the thickness of the first antiferroelectric film (310) is greater than the thickness of the first ferroelectric film (210) and the thickness of the second ferroelectric film (220).

3. The ferroelectric memory device based on a multilayer hafnium zirconium oxide thin film according to claim 2, characterized in that: The thickness of the first ferroelectric film (210) and the second ferroelectric film (220) is 2 nm, and the thickness of the first antiferroelectric film (310) is 4 nm.

4. The ferroelectric memory device based on a multilayer hafnium zirconium oxide thin film according to claim 1, characterized in that: The thickness of the ferroelectric film (200) and the antiferroelectric film (300) is no less than 1 nm.

5. The ferroelectric memory device based on a multilayer hafnium zirconium oxide thin film according to claim 1, characterized in that: The thickness d of the dielectric layer (100) satisfies: 3nm≤d≤20nm.

6. The ferroelectric memory device based on a multilayer hafnium zirconium oxide thin film according to claim 1, characterized in that: The total number of layers of the ferroelectric film (200) and the antiferroelectric film (300) is no less than 3 layers.

7. The ferroelectric memory device based on a multilayer hafnium zirconium oxide thin film according to claim 1, characterized in that: The ferroelectric memory device also includes metal electrodes arranged on both sides of the dielectric layer (100).

8. A method for manufacturing a ferroelectric memory device based on a multilayer hafnium zirconium oxide thin film, characterized in that: Used to manufacture a ferroelectric memory device based on a multilayer hafnium zirconium oxide thin film according to any one of claims 1 to 7.

9. The method for manufacturing a ferroelectric memory device based on a multilayer hafnium zirconium oxide thin film according to claim 8, characterized in that: The manufacturing method comprises alternately arranging the ferroelectric thin film (200) and the antiferroelectric thin film (300) by deposition.

10. The method for manufacturing a ferroelectric memory device based on a multilayer hafnium zirconium oxide thin film according to claim 8, characterized in that: The manufacturing method comprises: Disposing a first metal electrode (410); Providing the dielectric layer (100); A second metal electrode (420) is disposed on the dielectric layer (100).

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