Capacitor structure, method of controlling the same, and semiconductor device

Abstract

The application provides a capacitor structure, a control method thereof and a semiconductor device. The capacitor structure comprises a substrate, a second body region formed in the substrate, a capacitor comprising a third source / drain region and a fourth source / drain region formed in the second body region at intervals, and a depletion layer formed between the third source / drain region and the fourth source / drain region and the second body region. The third source / drain region and the fourth source / drain region have a doping type opposite to that of the second body region. The technical scheme of the application can meet different design requirements of a device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor integrated circuit manufacturing, and particularly relates to a capacitor structure, a control method thereof and a semiconductor device. BACKGROUND

[0002] To improve the uneven distribution of radio frequency signal voltage, a feedforward capacitor technology is generally used, that is, a feedforward capacitor is externally connected between the gate and the source / drain to perform voltage regulation. How to make the feedforward capacitor meet different design requirements of the device is a problem to be solved at present. SUMMARY

[0003] The present application aims to provide a capacitor structure, a control method thereof and a semiconductor device, so that the capacitor structure meets different design requirements of the device.

[0004] To achieve the above-mentioned purpose, the present application provides a capacitor structure, comprising:

[0005] a substrate, wherein a second body region is formed in the substrate;

[0006] a capacitor, comprising a third source / drain region, a fourth source / drain region and a depletion layer, the third source / drain region and the fourth source / drain region are formed in the second body region at intervals, and the doping type of the third source / drain region and the fourth source / drain region is opposite to the doping type of the second body region, so that the depletion layer is formed between the third source / drain region and the fourth source / drain region and the second body region.

[0007] Optionally, the capacitor structure further comprises a second gate structure formed on the second body region between the third source / drain region and the fourth source / drain region; the width of the depletion layer changes with the change of the potential difference applied on the second body region and the second gate structure, so that the capacitance value of the capacitor changes.

[0008] Optionally, the shape of the second gate structure is T-shaped or H-shaped, and the third source / drain region and the fourth source / drain region are located in the second body region on both sides of the “|” part of the T-shaped structure or the “―” part of the H-shaped structure.

[0009] Optionally, the capacitor structure further comprises:

[0010] a second body contact region formed in the second body region on the side of the “―” part of the T-shaped structure away from the third source / drain region and the fourth source / drain region, or formed in the second body region on the side of the “|” part of the H-shaped structure away from the third source / drain region and the fourth source / drain region.

[0011] The present application further provides a control method of the capacitor structure, comprising:

[0012] providing the capacitor structure;

[0013] applying a potential difference to the capacitor structure so that the capacitor in the capacitor structure has an adjustable capacitance value.

[0014] Optionally, the capacitor structure further comprises a second gate structure formed on the second body region between the third source / drain region and the fourth source / drain region; and applying a potential difference to the capacitor structure comprises:

[0015] applying a potential difference to the second body region and the second gate structure so that the width of the depletion layer changes, thereby changing the capacitance value of the capacitor.

[0016] The application further provides a semiconductor device comprising:

[0017] a transistor comprising a first source / drain region, a second source / drain region and a first gate structure;

[0018] a capacitor having an adjustable capacitance value, the capacitor being connected between the first source / drain region and the first gate structure.

[0019] Optionally, the semiconductor device further comprises a substrate, the first gate structure being formed on the substrate, and the first source / drain region and the second source / drain region being formed in the substrate on both sides of the first gate structure.

[0020] Optionally, the semiconductor device further comprises a substrate, the substrate having a second body region formed therein; and the capacitor comprises a third source / drain region, a fourth source / drain region and a depletion layer, the third source / drain region and the fourth source / drain region being formed in the second body region with a spacing therebetween, the third source / drain region and the fourth source / drain region having a doping type opposite to that of the second body region, so that the depletion layer is formed between the third source / drain region and the fourth source / drain region and the second body region.

[0021] wherein the third source / drain region is electrically connected to the first gate structure, and the fourth source / drain region is electrically connected to the first source / drain region.

[0022] Optionally, the semiconductor device further comprises a second gate structure formed on the second body region between the third source / drain region and the fourth source / drain region.

[0023] Optionally, the width of the depletion layer changes with a change in the potential difference applied to the second body region and the second gate structure, so that the capacitance value of the capacitor changes.

[0024] Optionally, the first source / drain region is a source region, and the second source / drain region is a drain region.

[0025] Optionally, the semiconductor device further comprises:

[0026] a first resistance, electrically connected with the first gate structure; and / or,

[0027] a second resistance, electrically connected between the first source / drain region and the second source / drain region.

[0028] Optionally, the doping type of the first source / drain region and the second source / drain region is the same as the doping type of the third source / drain region and the fourth source / drain region.

[0029] Optionally, the first gate structure and the second gate structure are in T shape or H shape, the first source / drain region and the second source / drain region are located in the substrate on both sides of the “|” part of the T shape or the “―” part of the H shape, and the third source / drain region and the fourth source / drain region are located in the second body region on both sides of the “|” part of the T shape or the “―” part of the H shape.

[0030] Optionally, the semiconductor device further comprises:

[0031] a first body region formed in the substrate, the first gate structure is formed on the first body region, and the first source / drain region and the second source / drain region are formed in the first body region on both sides of the “|” part of the T shape or the “―” part of the H shape;

[0032] a first body contact region formed in the first body region on the side of the “―” part of the T shape away from the first source / drain region and the second source / drain region, or formed in the first body region on the side of the “|” part of the H shape away from the first source / drain region and the second source / drain region;

[0033] a second body contact region formed in the second body region on the side of the “―” part of the T shape away from the third source / drain region and the fourth source / drain region, or formed in the second body region on the side of the “|” part of the H shape away from the third source / drain region and the fourth source / drain region. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a layout of a semiconductor device according to an embodiment of the present application;

[0035] Figure 2 is Figure 1 is a schematic cross-sectional view of the semiconductor device shown in FIG. 1 along the direction of AA’;

[0036] Figure 3is a circuit diagram of a semiconductor device according to an embodiment of the present application.

[0037] wherein the Figures 1-3 The reference signs in the drawings are explained as follows:

[0038] 10 - substrate; 101 - lower substrate; 102 - insulating buried layer; 103 - semiconductor layer; 11 - first gate structure; 12 - first source / drain region; 13 - second source / drain region; 14 - first body contact region; 21 - second gate structure; 211 - second gate dielectric layer; 22 - third source / drain region; 23 - fourth source / drain region; 24 - second body contact region; 241 - second body region; 25 - depletion layer; 31 - first conductive structure; 32 - second conductive structure; 33 - conductive plug; 34 - conductive interconnect structure. DETAILED DESCRIPTION

[0039] In order to make the objects, advantages and features of the present application clearer, the capacitor structure and its control method and semiconductor device according to the present application are further described in detail below with reference to the drawings. It should be noted that the drawings are all very simplified and use non-precise proportions, and are only used to facilitate and clearly assist the purpose of describing the embodiments of the present application.

[0040] An embodiment of the present application provides a semiconductor device, comprising: a substrate, a second body region being formed in the substrate; a capacitor, comprising a third source / drain region, a fourth source / drain region and a depletion layer, the third source / drain region and the fourth source / drain region being formed in the second body region at intervals, the doping type of the third source / drain region and the fourth source / drain region being opposite to the doping type of the second body region, so that the depletion layer is formed between the third source / drain region and the second body region and between the fourth source / drain region and the second body region.

[0041] Reference will be made to Figures 1-2 The capacitor structure provided by the embodiment is described in more detail.

[0042] The second body region 241 is formed in the substrate 10.

[0043] The capacitor comprises the third source / drain region 22, the fourth source / drain region 23 and the depletion layer 25, the third source / drain region 22 and the fourth source / drain region 23 being formed in the second body region 241 at intervals, the doping type of the third source / drain region 22 and the fourth source / drain region 23 being opposite to the doping type of the second body region 241, so that the depletion layer 25 is formed between the third source / drain region 22 and the second body region 241 and between the fourth source / drain region 23 and the second body region 241.

[0044] The second body region 241 is a well region formed by ion implantation into the substrate 10, and is used to separate the third source / drain region 22 and the fourth source / drain region 23.

[0045] The third source / drain region 22 is a source region, and the fourth source / drain region 23 is a drain region; or, the fourth source / drain region 23 is a source region, and the third source / drain region 22 is a drain region.

[0046] The capacitor structure further comprises a second gate structure 21 formed on the second body region 241 between the third source / drain region 22 and the fourth source / drain region 23; the width of the depletion layer 25 changes with the change of the potential difference applied on the second body region 241 and the second gate structure 21, so that the capacitance of the capacitor changes, i.e., the capacitor has an adjustable capacitance.

[0047] The depletion layer 25 is formed by applying a potential difference between the second body region 241 and the second gate structure 21.

[0048] The third source / drain region 22 and the fourth source / drain region 23 serve as two plates of the capacitor, the dielectric layer between the two plates comprises the depletion layer 25, the width W of the depletion layer 25 changes, i.e., the thickness of the dielectric layer changes, the thickness of the dielectric layer changes with the change of the potential difference applied on the second body region 241 and the second gate structure 21, therefore, the capacitance of the capacitor can change with the change of the potential difference applied on the second body region 241 and the second gate structure 21. In an embodiment, the greater the potential difference, the greater the width W of the depletion layer 25.

[0049] Applying the required potential difference to the second body region 241 and the second gate structure 21 can include applying a voltage to one of the second body region 241 and the second gate structure 21 and grounding or floating the other, or applying a voltage to both the second body region 241 and the second gate structure 21.

[0050] The substrate 10 can be made of any suitable material known to those skilled in the art.

[0051] The substrate 10 can be a bulk substrate or an SOI (Semiconductor On Insulator) substrate, the bulk substrate can be a semiconductor substrate commonly used in the semiconductor field, such as silicon, germanium, GaN, etc., and the SOI substrate can be a silicon-on-insulator or germanium-on-insulator substrate. The SOI substrate comprises a lower substrate 101, an insulating buried layer 102, and a semiconductor layer 103 from bottom to top.

[0052] In one embodiment, when the substrate 10 is a bulk substrate, if the second body region 241 is of the same doping type as the substrate 10 at its periphery, a doped region (not shown) is further formed at the periphery of the second body region 241 (i.e. the lower surface and the side surface of the second body region 241) to enclose the second body region 241, the doped region being of the opposite doping type to the second body region 241, and the doped region is used to isolate the second body region 241 from the substrate 10 at its periphery, so that a voltage can be applied to the second body region 241 independently.

[0053] When the substrate 10 is an SOI substrate, the third source / drain region 22 and the fourth source / drain region 23 can be formed in the semiconductor layer 103 of partial thickness (as shown) or full thickness, so that the lower surface of the third source / drain region 22 and the fourth source / drain region 23 corresponds to no contact or contact with the buried insulating layer 102. Figure 2

[0054] A second gate dielectric layer 211 is formed between the second gate structure 21 and the second body region 241.

[0055] The second gate dielectric layer 211 can be a single layer structure or a structure of at least two layers stacked. The material of the second gate dielectric layer 211 can include at least one of silicon oxide and high-K (relative dielectric constant) dielectric, and the high-K dielectric refers to a material with a relative dielectric constant greater than that of silicon oxide. The inclusion of high-K dielectric in the second gate dielectric layer 211 can reduce the risk of leakage.

[0056] In one embodiment, the second gate dielectric layer 211 includes a silicon oxide layer and a high-K dielectric layer stacked from bottom to top.

[0057] The material of the second gate structure 21 can be metal or polysilicon.

[0058] In one embodiment, the material of the second gate structure 21 is polysilicon, and when the second gate dielectric layer 211 includes high-K dielectric, a cap layer (not shown) is further formed between the second gate structure 21 and the second gate dielectric layer 211, and the cap layer is used to isolate polysilicon from high-K dielectric to prevent performance from being affected, for example, to prevent the occurrence of Fermi Level Pinning effect, which leads to an increase in operating voltage.

[0059] The shape of the second gate structure 21 is T-shaped or H-shaped, and the third source / drain region 22 and the fourth source / drain region 23 are located in the second body region 241 at the “|” part of the T-shaped or at the two sides of the “―” part of the H-shaped.

[0060] ​The capacitor structure further comprises a second body contact region 24 formed in the second body region 241 at a position away from the third source / drain region 22 and the fourth source / drain region 23 in a T-shaped "―" part, or formed in the second body region 241 at a position away from the third source / drain region 22 and the fourth source / drain region 23 in a H-shaped "|".

[0061] In the second gate structure 21, the T-shaped "|", or the H-shaped "―" part functions as a gate, and the T-shaped "―", or the H-shaped "|", functions to isolate the third source / drain region 22 and the fourth source / drain region 23 from the second body contact region 24.

[0062] The capacitor structure further comprises a conductive structure comprising a conductive interconnection structure 34 and a conductive plug 33, the conductive plug 33 being formed on the third source / drain region 22, the fourth source / drain region 23, the second gate structure 21 and the second body contact region 24, the conductive plug 33 on the third source / drain region 22 being electrically connected to other structures through the conductive interconnection structure 34, the conductive plug 33 on the fourth source / drain region 23 being electrically connected to other structures through the conductive interconnection structure 34, and the conductive plug 33 on the second gate structure 21 and the second body contact region 24 being electrically connected to other structures through the conductive interconnection structure 34.

[0063] As can be seen from the above, the capacitor structure provided by the application has the third source / drain region 22 and the fourth source / drain region 23 both forming a depletion layer 25 with the second body region 241, the width of the depletion layer 25 changing with the change of the potential difference applied on the second body region 241 and the second gate structure 21, so that the capacitor composed of the third source / drain region 22, the fourth source / drain region 23 and the depletion layer 25 has an adjustable capacitance value, and the capacitor can meet different design requirements of a device, without the need to set multiple capacitors to meet different design requirements of a device, thus avoiding the large area occupied by the capacitor and saving the research and development cost.

[0064] An embodiment of the application provides a control method of a capacitor structure, comprising:

[0065] The capacitor structure is provided, and the composition of the capacitor structure is described above and will not be repeated here.

[0066] A potential difference is applied to the capacitor structure, so that the capacitor in the capacitor structure has an adjustable capacitance value.

[0067] The applying of the potential difference to the capacitor structure includes applying a potential difference to the second body region and the second gate structure to change the width of the depletion layer, and then change the capacitance value of the capacitor, i.e. the capacitor has an adjustable capacitance value, so that the capacitor can meet different design requirements of the device, without setting multiple capacitors to meet different design requirements of the device, avoiding the large area occupation of the capacitor, saving the research and development cost.

[0068] The applying of the potential difference to the second body region and the second gate structure can include applying a voltage to one of the second body region and the second gate structure and grounding or floating the other, or applying a voltage to both the second body region and the second gate structure.

[0069] An embodiment of the present application provides a semiconductor device, comprising: a transistor comprising a first source / drain region, a second source / drain region and a first gate structure; a capacitor having an adjustable capacitance value, the capacitor being connected between the first source / drain region and the first gate structure.

[0070] The semiconductor device provided by the embodiment will be described in detail below. Figures 1-3 The semiconductor device provided by the embodiment will be described in detail below.

[0071] The transistor M1 comprises a first source / drain region 12 (such as S in the figure), a second source / drain region 13 (such as D in the figure) and a first gate structure 11 (such as G in the figure), the first gate structure 11 is formed on the substrate 10, and the first source / drain region 12 and the second source / drain region 13 are formed in the substrate 10 on both sides of the first gate structure 11. Figure 3 Figure 3 The transistor M1 comprises a first source / drain region 12 (such as S in the figure), a second source / drain region 13 (such as D in the figure) and a first gate structure 11 (such as G in the figure), the first gate structure 11 is formed on the substrate 10, and the first source / drain region 12 and the second source / drain region 13 are formed in the substrate 10 on both sides of the first gate structure 11. Figure 3

[0072] The semiconductor device further comprises a first body region (not shown) formed in the substrate 10, the first gate structure 11 is formed on the first body region, and the first source / drain region 12 and the second source / drain region 13 are formed in the first body region on both sides of the first gate structure 11. The first body region is a well region formed by ion implantation in the substrate 10, and the first body region is used to separate the first source / drain region 12 and the second source / drain region 13.

[0073] ​​The first source / drain region 12 and the second source / drain region 13 are oppositely doped to the first body region. When the first source / drain region 12 and the second source / drain region 13 are N-type, the first body region is P-type, the transistor M1 is an NMOS transistor; when the first source / drain region 12 and the second source / drain region 13 are P-type, the first body region is N-type, the transistor M1 is a PMOS transistor.

[0074] The capacitor C1 has an adjustable capacitance value, and is connected between the first source / drain region 12 and the first gate structure 11.

[0075] The semiconductor device further comprises a second body region 241 formed in the substrate 10 and a second gate structure 21 formed on the second body region 241. The second body region 241 is a well region formed by ion implantation into the substrate 10, and is used to isolate a third source / drain region 22 and a fourth source / drain region 23.

[0076] The capacitor C1 comprises the third source / drain region 22, the fourth source / drain region 23 and a depletion layer 25. The third source / drain region 22 and the fourth source / drain region 23 are formed in the second body region 241 on both sides of the second gate structure 21. The third source / drain region 22 and the fourth source / drain region 23 are oppositely doped to the second body region 241, so that the third source / drain region 22 and the fourth source / drain region 23 each form the depletion layer 25 with the second body region 241.

[0077] The depletion layer 25 is formed by applying a potential difference between the second body region 241 and the second gate structure 21.

[0078] The substrate 10 can be made of any suitable material known to those skilled in the art.

[0079] The substrate 10 can be a bulk substrate or an SOI (Semiconductor On Insulator) substrate. The bulk substrate can be a semiconductor substrate commonly used in the semiconductor field, such as silicon, germanium, GaN, etc. The SOI substrate can be a silicon-on-insulator or germanium-on-insulator substrate. The SOI substrate comprises a lower substrate 101, an insulating buried layer 102 and a semiconductor layer 103 from bottom to top.

[0080] In one embodiment, when the substrate 10 is a bulk substrate, if the second bulk region 241 has the same doping type as the surrounding substrate 10, a doped region (not shown) is also formed around the second bulk region 241 (i.e., the lower surface and side surface of the second bulk region 241) to surround the second bulk region 241. The doped region has the opposite doping type to the second bulk region 241. The doped region is used to separate the second bulk region 241 from the surrounding substrate 10, so that a voltage can be applied to the second bulk region 241 separately.

[0081] When the substrate 10 is an SOI substrate, the first source / drain region 12 and the second source / drain region 13 can be formed in a semiconductor layer 103 of a partial or full thickness, such that the lower surfaces of the first source / drain region 12 and the second source / drain region 13 are either not in contact with or in contact with the buried insulating layer 102; the third source / drain region 22 and the fourth source / drain region 23 can be formed in a portion of the thickness (e.g., Figure 2 In the semiconductor layer 103 (shown) or of its full thickness, the lower surfaces of the third source / drain region 22 and the fourth source / drain region 23 are either not in contact with or in contact with the insulating buried layer 102.

[0082] The doping type of the first source / drain region 12 and the second source / drain region 13 is the same as that of the third source / drain region 22 and the fourth source / drain region 23, and the doping type of the first body region is the same as that of the second body region 241.

[0083] A first gate dielectric layer (not shown) is formed between the first gate structure 11 and the first body region, and a second gate dielectric layer 211 is formed between the second gate structure 21 and the second body region 241.

[0084] In one embodiment, the first gate dielectric layer and the second gate dielectric layer 211 are located on the same layer, and the first gate structure 11 and the second gate structure 21 are located on the same layer.

[0085] The first gate dielectric layer and / or the second gate dielectric layer 211 can be a single-layer structure or a structure of at least two stacked layers. The material of the first gate dielectric layer and / or the second gate dielectric layer 211 can include at least one insulating material such as silicon oxide and a high-k (relative permittivity) dielectric, where a high-k dielectric is a material with a relative permittivity greater than that of silicon oxide. The inclusion of a high-k dielectric in the first gate dielectric layer and / or the second gate dielectric layer 211 can reduce the risk of leakage current.

[0086] In one embodiment, the first gate dielectric layer and / or the second gate dielectric layer 211 comprise a silicon oxide layer and a high-k dielectric layer stacked from bottom to top.

[0087] The material of the first gate structure 11 can include metal or polysilicon, and the material of the second gate structure 21 can include metal or polysilicon.

[0088] In an embodiment, the material of the first gate structure 11 and / or the second gate structure 21 is polysilicon, and when the first gate dielectric layer and / or the second gate dielectric layer 211 contains high-K dielectric, a cap layer (not shown) is further formed between the first gate structure 11 and the first gate dielectric layer and / or between the second gate structure 21 and the second gate dielectric layer 211, which is used to separate polysilicon and high-K dielectric to prevent affecting performance, for example, to prevent the Fermi Level Pinning effect from causing the operating voltage to rise.

[0089] The shapes of the first gate structure 11 and the second gate structure 21 are T-shaped or H-shaped, the first source / drain region 12 and the second source / drain region 13 are located in the first body region on both sides of the “|” part of the T-shaped or the “―” part of the H-shaped, and the third source / drain region 22 and the fourth source / drain region 23 are located in the second body region 241 on both sides of the “|” part of the T-shaped or the “―” part of the H-shaped.

[0090] The semiconductor device further comprises:

[0091] The first body contact region 14 is formed in the first body region on the side away from the “―” part of the T-shaped or the “|” part of the H-shaped, or is formed in the first body region on the side away from the first source / drain region 12 and the second source / drain region 13.

[0092] The second body contact region 24 is formed in the second body region 241 on the side away from the “―” part of the T-shaped or the “|” part of the H-shaped, or is formed in the second body region 241 on the side away from the third source / drain region 22 and the fourth source / drain region 23.

[0093] In the first gate structure 11 and the second gate structure 21, the “|” part of the T-shaped or the “―” part of the H-shaped functions as the gate of the semiconductor device; in the first gate structure 11, the “―” part of the T-shaped or the “|” part of the H-shaped functions to isolate the first source / drain region 12 and the second source / drain region 13 from the first body contact region 14, respectively; in the second gate structure 21, the “―” part of the T-shaped or the “|” part of the H-shaped functions to isolate the third source / drain region 22 and the fourth source / drain region 23 from the second body contact region 24, respectively.

[0094] The capacitor structure includes the capacitor C1, the second body region 241, the second gate structure 21, the second gate dielectric layer 211 and the second body contact region 24.

[0095] The semiconductor device further includes a shallow trench isolation structure (not shown) formed in the substrate 10, which is used to isolate the transistor M1 from the capacitor structure.

[0096] The third source / drain region 22 is electrically connected to the first gate structure 11, and the fourth source / drain region 23 is electrically connected to the first source / drain region 12; since the doping type of the third source / drain region 22 and the fourth source / drain region 23 is opposite to that of the second body region 241, a depletion layer 25 is formed between the third source / drain region 22 and the second body region 241, and between the fourth source / drain region 23 and the second body region 241; the width W of the depletion layer 25 changes with the change of the potential difference applied on the second body region 241 and the second gate structure 21, thereby changing the capacitance value of the capacitor C1 composed of the third source / drain region 22, the fourth source / drain region 23 and the depletion layer 25.

[0097] The third source / drain region 22 and the fourth source / drain region 23 serve as two plates of the capacitor C1, the dielectric layer between the two plates includes the depletion layer 25, the change of the width W of the depletion layer 25 is the change of the thickness of the dielectric layer, the thickness of the dielectric layer changes with the change of the potential difference applied on the second body region 241 and the second gate structure 21, thus the capacitance value of the capacitor C1 can change with the change of the potential difference applied on the second body region 241 and the second gate structure 21. In an embodiment, the greater the potential difference, the greater the width W of the depletion layer 25.

[0098] During the operation of the semiconductor device, in addition to applying a required voltage to the transistor M1 to make the transistor M1 work, a required potential difference is applied to the second body region 241 and the second gate structure 21 in the capacitor structure to make the capacitor C1 in the capacitor structure have a required capacitance value.

[0099] Applying a voltage to the transistor Ml can include applying a voltage to the first gate structure 11, the first body region (the first body contact region 14), the first source / drain region 12, and the second source / drain region 13, and / or grounding. For example, a positive voltage or a negative voltage can be applied to the first gate structure 11, the first body region (the first body contact region 14) can be grounded, and the first source / drain region 12 and the second source / drain region 13 can be used as input and output of an electrical signal. In an embodiment, when the semiconductor device is a radio frequency device, the first source / drain region 12 and the second source / drain region 13 can be used as input and output of a radio frequency signal.

[0100] Applying a desired potential difference between the second body region 241 and the second gate structure 21 of the capacitor structure can include applying a voltage to one of the second body region 241 and the second gate structure 21 and grounding or floating the other, or applying a voltage to both the second body region 241 and the second gate structure 21.

[0101] It should be noted that since the third source / drain region 22 is electrically connected with the first gate structure 11 and the fourth source / drain region 23 is electrically connected with the first source / drain region 12, when a voltage is applied to or grounded to the first gate structure 11 and the first source / drain region 12 in the transistor M1, it is equivalent to apply a voltage to or ground to the third source / drain region 22 and the fourth source / drain region 23 respectively. Therefore, when a voltage is applied to the second body region 241, it is necessary to prevent the positive bias phenomenon from occurring between the third source / drain region 22 and the fourth source / drain region 23 and the second body region 241, i.e. to prevent the PN junction formed by the third source / drain region 22, the fourth source / drain region 23 and the second body region 241 from being turned on, and to prevent the capacitor structure from becoming a resistor structure, so as to prevent the first source / drain region 12 and the first gate structure 11 in the transistor M1 from being turned on. For example, when the doping type of the third source / drain region 22 and the fourth source / drain region 23 is P type and the doping type of the second body region 241 is N type, a positive voltage cannot be applied to the third source / drain region 22 and the fourth source / drain region 23 and a negative voltage must be applied to the second body region 241, i.e. a forward bias cannot be applied; instead, a negative voltage must be applied to the third source / drain region 22 and the fourth source / drain region 23 and a positive voltage or ground must be applied to the second body region 241, or the third source / drain region 22 and the fourth source / drain region 23 are grounded and a positive voltage is applied to the second body region 241, i.e. a reverse bias is applied to the third source / drain region 22, the fourth source / drain region 23 and the second body region 241. Therefore, when the doping type of the third source / drain region 22 and the fourth source / drain region 23 is P type, only a positive voltage or ground can be applied to the second body region 241; when the doping type of the third source / drain region 22 and the fourth source / drain region 23 is N type, only a negative voltage or ground can be applied to the second body region 241.

[0102] In an embodiment, the first source / drain region 12 is a source region and the second source / drain region 13 is a drain region. In this case, the third source / drain region 22 is a source region and the fourth source / drain region 23 is a drain region, or the fourth source / drain region 23 is a source region and the third source / drain region 22 is a drain region.

[0103] In an embodiment, the semiconductor device further comprises:

[0104] a first resistor R G , which is electrically connected with the first gate structure 11; and / or,

[0105] a second resistor R SD , which is electrically connected between the first source / drain region 12 and the second source / drain region 13.

[0106] The first resistance R G comprising a first insulating layer (not shown) and a first conductive structure 31 formed on the substrate 10 from bottom to top, the second resistance R SD comprising a second insulating layer (not shown) and a second conductive structure 32 formed on the substrate 10 from bottom to top.

[0107] In an embodiment, the first insulating layer and the second insulating layer are in the same layer, and the first conductive structure 31 and the second conductive structure 32 are in the same layer.

[0108] The material of the first conductive structure 31 can be metal or polysilicon, and the material of the second conductive structure 32 can be metal or polysilicon.

[0109] The first resistance R G and the second resistance R SD as a load for voltage stabilization. In other embodiments, the semiconductor device can also not include the first resistance R G and the second resistance R SD .

[0110] The semiconductor device further comprises:

[0111] A conductive structure comprising a conductive interconnection structure 34 and a conductive plug 33, the conductive plug 33 being formed on the first source / drain region 12, the second source / drain region 13, the first gate structure 11, the third source / drain region 22, the fourth source / drain region 23 and the second gate structure 21, the conductive plug 33 on the third source / drain region 22 being electrically connected to the conductive plug 33 on the first gate structure 11 through the conductive interconnection structure 34, the conductive plug 33 on the fourth source / drain region 23 being electrically connected to the conductive plug 33 on the first source / drain region 12 through the conductive interconnection structure 34, and the conductive plug 33 on the second gate structure 21 being electrically led out through the conductive interconnection structure 34.

[0112] The conductive plug 33 is also formed on the first body contact region 14 and the second body contact region 24, so that the conductive plug 33 on the first body contact region 14 and the second body contact region 24 can be electrically led out through the conductive interconnection structure 34, respectively.

[0113] The conductive plug 33 is also formed on both ends of the first conductive structure 31, so that the conductive plug 33 on one end of the first conductive structure 31 can be electrically connected to the conductive plug 33 on the first gate structure 11 through the conductive interconnection structure 34, and the conductive plug 33 on the other end of the first conductive structure 31 can be electrically led out through the conductive interconnection structure 34; the conductive plug 33 is also formed on both ends of the second conductive structure 32, so that the conductive plugs 33 on both ends of the second conductive structure 32 can be electrically connected to the conductive plugs 33 on the first source / drain region 12 and the second source / drain region 13 respectively through the conductive interconnection structure 34.

[0114] From the above, the semiconductor device provided by the application has the capacitor C1 with adjustable capacitance value between the first source / drain region 12 and the first gate structure 11 in the transistor M1, so that the capacitor C1 can meet different design requirements of the transistor M1, without the need to set multiple capacitors to meet different design requirements of the device, avoiding large occupation area of the capacitor and saving research and development cost.

[0115] In an embodiment, the third source / drain region 22 and the fourth source / drain region 23 in the capacitor C1 are both doped with a type opposite to that of the second body region 241, so that a depletion layer 25 is formed between the third source / drain region 22 and the fourth source / drain region 23 and the second body region 241, the width of the depletion layer 25 changes with the change of the potential difference applied on the second body region 241 and the second gate structure 21, and then the capacitance value of the capacitor C1 composed of the third source / drain region 22, the fourth source / drain region 23 and the depletion layer 25 changes, so that the capacitor C1 has multiple different capacitance values by adjusting the size of the potential difference applied on the second body region 241 and the second gate structure 21, that is, the capacitor C1 set between the first source / drain region 12 and the first gate structure 11 in the transistor M1 has adjustable capacitance value.

[0116] When the semiconductor device is a radio frequency switch device, the capacitor C1 has adjustable capacitance value, so that the voltage regulation of the radio frequency switch device is more flexible.

[0117] The above description is only a description of the preferred embodiments of the application, and does not limit the scope of the application in any way, and any modification or modification of the application by a person skilled in the art based on the above disclosure is within the protection scope of the claims.

Claims

1. A capacitive structure, characterized by, The semiconductor device comprises: a substrate having a second body region formed therein; a capacitor comprising a third source / drain region and a fourth source / drain region formed in the second body region with a spacing therebetween, and a depletion layer formed between the third source / drain region and the fourth source / drain region and the second body region, the third source / drain region and the fourth source / drain region having a doping type opposite to that of the second body region, the third source / drain region and the fourth source / drain region serving as two plates of the capacitor, and a dielectric layer between the two plates comprising the depletion layer; a second gate structure formed on the second body region between the third source / drain region and the fourth source / drain region, the width of the depletion layer varying with a potential difference applied to the second body region and the second gate structure, so that the capacitance of the capacitor varies.

2. The capacitance structure of claim 1, wherein, The second gate structure has a T-shape or an H-shape, and the third source / drain region and the fourth source / drain region are located in the second body region on both sides of the "―" part of the T-shape or the "―" part of the H-shape.

3. The capacitance structure of claim 2, wherein, The capacitor structure further comprises: a second body contact region formed in the second body region on a side of the "―" part of the T-shape or the "―" part of the H-shape away from the third source / drain region and the fourth source / drain region.

4. A control method of a capacitor structure, characterized by, The semiconductor device comprises: providing a capacitor structure as claimed in any one of claims 1 to 3; applying a potential difference to the capacitor structure, so that the capacitor in the capacitor structure has an adjustable capacitance; wherein the applying of the potential difference to the capacitor structure comprises: applying a potential difference to the second body region and the second gate structure, so that the width of the depletion layer varies, and in turn the capacitance of the capacitor varies.

5. A semiconductor device, characterized by, The semiconductor device comprises: a transistor comprising a first source / drain region, a second source / drain region, and a first gate structure; a capacitor having an adjustable capacitance, the capacitor being connected between the first source / drain region and the first gate structure; the semiconductor device further comprises a substrate having a second body region formed therein; the capacitor comprises a third source / drain region and a fourth source / drain region formed in the second body region with a spacing therebetween, and a depletion layer formed between the third source / drain region and the fourth source / drain region and the second body region, the third source / drain region and the fourth source / drain region having a doping type opposite to that of the second body region, the third source / drain region and the fourth source / drain region serving as two plates of the capacitor, and a dielectric layer between the two plates comprising the depletion layer; a second gate structure formed on the second body region between the third source / drain region and the fourth source / drain region; a width of the depletion layer changes with a change of a potential difference applied on the second body region and the second gate structure, so that a capacitance value of the capacitor changes; wherein the third source / drain region is electrically connected with the first gate structure, and the fourth source / drain region is electrically connected with the first source / drain region.

6. The semiconductor device of claim 5, wherein, The first gate structure is formed on the substrate, and the first source / drain region and the second source / drain region are formed in the substrate on two sides of the first gate structure.

7. The semiconductor device of claim 5, wherein the first and second semiconductor layers are formed of a same material. The first source / drain region is a source region, and the second source / drain region is a drain region.

8. The semiconductor device of claim 5, wherein, The semiconductor device further comprises: a first resistance electrically connected with the first gate structure; and / or a second resistance electrically connected between the first source / drain region and the second source / drain region.

9. The semiconductor device of claim 5, wherein, The doping type of the first source / drain region and the second source / drain region is the same as the doping type of the third source / drain region and the fourth source / drain region.

10. The semiconductor device of claim 5, wherein, The first gate structure and the second gate structure are in a T shape or an H shape, the first source / drain region and the second source / drain region are located in the substrate on two sides of a “|” part of the T shape or a “―” part of the H shape, and the third source / drain region and the fourth source / drain region are located in the second body region on two sides of the “|” part of the T shape or the “―” part of the H shape.

11. The semiconductor device of claim 10, wherein, The semiconductor device further comprises: a first body region formed in the substrate, the first gate structure is formed on the first body region, and the first source / drain region and the second source / drain region are formed in the first body region on two sides of a “|” part of the T shape or a “―” part of the H shape; a first body contact region formed in the first body region on a side of a “―” part of the T shape away from the first source / drain region and the second source / drain region, or formed in the first body region on a side of a “|” part of the H shape away from the first source / drain region and the second source / drain region; a second body contact region formed in the second body region on a side of a “―” part of the T shape away from the third source / drain region and the fourth source / drain region, or formed in the second body region on a side of a “|” part of the H shape away from the third source / drain region and the fourth source / drain region.

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