IGBT device

Abstract

The application discloses an IGBT device, comprising: a plurality of parallel arranged gate trench structures and emitter trench structures through a well region. A gate conductive material layer is connected to the gate. An emitter conductive material layer is connected to the emitter. A drift region is formed at the bottom of the well region, and a collector region is formed at the bottom of the drift region. An emitter region is formed in the surface region of the selected area of the well region. The emitter region is located on both sides of each gate trench structure and is self-aligned with the side surface of the gate trench structure; the emitter region does not contact the side surface of the emitter trench structure. The top of the emitter region is connected to the emitter through a first contact hole, and a contact implantation region is formed at the bottom of the first contact hole. The width of the emitter trench is smaller than the width of the gate trench, so as to increase the width of the mesa region between the trench structures and thereby increase the distance from the first contact hole to the conductive channel, so as to reduce the influence of the contact implantation region on the threshold voltage of the device. The application can improve the uniformity of the threshold voltage of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor power device, in particular to an IGBT device. BACKGROUND

[0002] Compared with the planar gate structure, the trench gate technology has the characteristics of compact cell and small on-state voltage drop due to the elimination of the junction gate field-effect transistor (JFET) region, and can realize greater current density, so it is widely used in electric vehicle chip field.

[0003] The carrier concentration of the traditional IGBT chip decreases from the back collector to the front emitter, and the low carrier concentration of the front emitter limits the reduction of the on-state voltage drop. Therefore, the improvement of the current density and the reduction of the power loss of the IGBT chip also need to combine the carrier storage technology to make the carrier distribution in the IGBT chip closer to the optimal state.

[0004] As shown in FIG. 1, it is a structural schematic diagram of the existing IGBT device; taking an N-type device as an example, the existing IGBT device includes: Figure 1

[0005] A plurality of parallelly arranged trench gates, the trench gate includes a gate trench, a gate dielectric layer 110 formed on the inner side surface of the gate trench, and a gate conductive material layer 111 filled in the gate trench.

[0006] The gate conductive material layer 111 is connected to the gate electrode composed of the front metal layer 109.

[0007] Each trench gate passes through the P-type doped well region 105.

[0008] The N-type doped drift region 103 is formed at the bottom of the well region 105.

[0009] The P-type heavily doped collector region 101 is formed at the bottom of the drift region 103. The back surface of the collector region 101 forms a back metal layer and the back metal layer constitutes a collector electrode.

[0010] In the existing technology, the N-type heavily doped buffer layer 102 is further included between the drift region 103 and the collector region 1011.

[0011] The N-type heavily doped emitter region 106 is formed in the surface region of the well region 105 of the platform region on both sides of the trench gate, and the emitter region 106 and the side surface of the corresponding trench gate are self-aligned.

[0012] The N-type heavily doped carrier storage (CS) layer 104 is further formed in the top region of the drift region 103.

[0013] ​Each gate trench passes through the carrier storage layer 104.

[0014] Figure 1 The shown IGBT device is based on the improvement of IGBT chip current density by using a fine trench technology, and by adding a carrier storage layer to prevent holes from entering the P-base region, i.e., the well region 105, to increase the hole concentration near the emitter, and to reduce the on-state voltage by at least 20%.

[0015] The IGBT is a bipolar device, and there are electron current and hole current when it is turned on and off. Usually, B or BF2 is ion implanted (imp) through the contact hole (CT) after etching the CT, so that the bottom of the CT is connected to the P-type well region to collect the hole current, and the anti-latch-up capability of the IGBT can also be effectively improved. However, as the cell pitch of the IGBT, i.e., the pitch, becomes smaller and smaller, the distance between the CT and the channel becomes smaller and smaller, and the influence of the CT imp on the channel cannot be ignored. At the pitch of 1.6 microns / 1.2 microns node, the CT imp will cause the threshold voltage (VTH) of the device to rise and the distribution to be discrete, and due to the stress problem, the VTH difference between the center and the edge of the wafer will also be more obvious, which is obviously not conducive to the promotion and application of the IGBT. SUMMARY

[0016] The technical problem to be solved by the present application is to provide an IGBT device that can improve the uniformity of the threshold voltage of the device.

[0017] To solve the above technical problems, the IGBT device provided by the present application comprises: a plurality of parallelly arranged trench structures; a part of the trench structures as gate trench structures and another part of the trench structures as emitter trench structures.

[0018] The gate trench structure comprises a gate trench, a gate dielectric layer formed on the inner side surface of the gate trench, and a gate conductive material layer filled in the gate trench.

[0019] The emitter trench structure comprises an emitter trench, an emitter dielectric layer formed on the inner side surface of the emitter trench, and an emitter conductive material layer filled in the emitter trench.

[0020] The gate conductive material layer is connected to a gate composed of a front metal layer.

[0021] The emitter conductive material layer is connected to an emitter composed of a front metal layer.

[0022] Each of the gate trench structures and each of the emitter trench structures passes through a well region of a second conductivity type; a surface of the well region which is laterally covered by the gate conductive material layer is used to form a conductive channel of a first conductivity type.

[0023] A drift region of a first conductivity type is formed at a bottom of the well region.

[0024] A collector region of a second conductivity type heavily doped is formed at a bottom of the drift region.

[0025] An emitter region of a first conductivity type heavily doped is formed in a surface region of a selected region of the well region.

[0026] The emitter region is located at both sides of each of the gate trench structures and is self-aligned with the side surface of the corresponding gate trench structure; the emitter region does not contact the side surface of the emitter trench structure.

[0027] The top of the emitter region at both sides of each of the gate trench structures is connected to the emitter through a first contact hole, a bottom of the first contact hole is formed with a contact implant region, and the contact implant region realizes the connection between the first contact hole and the well region.

[0028] The width of the emitter trench is smaller than the width of the gate trench, so as to increase the width of the mesa region between the trench structures and thereby increase the distance from the first contact hole to the conductive channel, so as to reduce the influence of the contact implant region on the threshold voltage of the device.

[0029] A further improvement is that a carrier storage layer of a first conductivity type heavily doped is further formed in a top region of the drift region.

[0030] A further improvement is that the gate trench passes through the carrier storage layer.

[0031] A further improvement is that the depth of the emitter trench is smaller than the depth of the gate trench, so as to reduce the in-plane stress; the emitter trench and the gate trench are simultaneously formed by using the same etching process, and the smaller the width of the emitter trench is, the shallower the depth of the emitter trench is.

[0032] A further improvement is that the bottom surface of the carrier storage layer is located below the bottom surface of the emitter trench, so as to increase the carrier injection effect.

[0033] A further improvement is that the top of the well region at both sides of each of the emitter trench structures is connected to the emitter through a second contact hole; or the top of the well region at both sides of each of the emitter trench structures is not provided with a contact hole and is in a floating structure.

[0034] Further improvement is that the gate trench structure and the emitter trench structure are periodically arranged in m:n number ratio, m is the number of the gate trench structure in the arrangement period, n is the number of the emitter trench structure in the arrangement period, m is greater than or equal to 1, and n is greater than or equal to 1.

[0035] Further improvement is that the value of m:n includes:

[0036] 1:1, 1:2, 1:3, 2:2, 3:3.

[0037] Further improvement is that a first conductive type heavily doped buffer layer is further included between the drift region and the collector region.

[0038] Further improvement is that the width of the emitter trench is 0.05-0.2 μm smaller than the width of the gate trench.

[0039] Further improvement is that the gate dielectric layer and the emitter dielectric layer are formed of the same material at the same time.

[0040] The gate conductive material layer and the emitter conductive material layer are formed of the same material at the same time.

[0041] Further improvement is that the material of the gate dielectric layer includes an oxide layer, and the material of the gate conductive material layer includes polysilicon.

[0042] Further improvement is that the step of the parallelly arranged trench structure is 1.6 μm or below 1.2 μm.

[0043] Further improvement is that the IGBT device is an N-type device, the first conductive type is N-type, and the second conductive type is P-type; or, the IGBT device is a P-type device, the first conductive type is P-type, and the second conductive type is N-type.

[0044] Further improvement is that when the IGBT device is an N-type device, the implanted impurity of the contact implantation region includes boron or boron fluoride.

[0045] The present application sets up the emitter trench structure parallel to the gate trench structure, by reducing the width of the emitter trench, i.e. the critical dimension (CD), the width of the mesa between the trench structures can be increased while keeping the average step of the parallel trench structure unchanged. Thus, the distance between the first contact hole set on both sides of the gate trench structure and the corresponding conductive channel on the side of the gate trench is increased, and the distance between the contact implantation region self-aligned at the bottom of the first contact hole and the conductive channel is also increased. Thus, the influence of the impurities of the heavily doped contact implantation region on the doping concentration and distribution of the well region at the conductive channel can be reduced or prevented, so that the influence of the contact implantation region on the threshold voltage of the device can be reduced, and finally the uniformity of the threshold voltage and the uniformity of the in-plane distribution of the device can be improved.

[0046] The gate trench and the emitter trench of the present application can be formed simultaneously by using the same etching process. By using the etching effect, the width of the emitter trench is reduced while the depth of the emitter trench is also reduced. The reduction of the depth of the emitter trench can reduce the stress in the wafer plane, and the reduction of the stress can also reduce the difference in threshold voltage between different regions of the wafer, such as the center part and the edge part, thereby further improving the uniformity of the threshold voltage of the device.

[0047] In addition, the present application can further reduce the depth of the emitter trench to the bottom surface of the carrier storage layer, so that the area of the carrier storage layer is increased, thereby reducing the leakage of minority carriers in the drift region into the well region, thereby enhancing the carrier injection effect, so that the on-state loss of the device can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0048] The present application will be further described in detail below in conjunction with the drawings and specific embodiments:

[0049] Figure 1 is a schematic diagram of the structure of a conventional IGBT device;

[0050] Figure 2 is a schematic diagram of the structure of an IGBT device according to the first embodiment of the present application;

[0051] Figure 3 is a schematic diagram of the structure of an IGBT device according to the second embodiment of the present application;

[0052] Figure 4 is a schematic diagram of the structure of an IGBT device according to the third embodiment of the present application. DETAILED DESCRIPTION

[0053] As shown in Figure 2 is a schematic diagram of the structure of an IGBT device according to the first embodiment of the present application; the IGBT device according to the first embodiment of the present application comprises:

[0054] a plurality of parallelly arranged trench structures; a part of the trench structures as gate trench structures 201 and another part of the trench structures as emitter trench structures 202.

[0055] The gate trench structures 201 include gate trenches 203 (Gate TCH), gate dielectric layers 10a formed on inner side surfaces of the gate trenches 203, and gate conductive material layers 11a filled in the gate trenches 203.

[0056] The emitter trench structures 202 include emitter trenches 204 (Emitter TCH), emitter dielectric layers 10b formed on inner side surfaces of the emitter trenches 204, and emitter conductive material layers 11b filled in the emitter trenches 204.

[0057] In the first embodiment of the present application, the gate dielectric layers 10a and the emitter dielectric layers 10b are formed of the same material at the same time.

[0058] The gate conductive material layers 11a and the emitter conductive material layers 11b are formed of the same material at the same time.

[0059] In some embodiments, the material of the gate dielectric layers 10a includes an oxide layer, and the material of the gate conductive material layers 11a includes polysilicon.

[0060] The gate conductive material layers 11a are connected to gates composed of the front metal layer 9. Figure 2 In the corresponding cross section, the gate conductive material layers 11a are also denoted as G.

[0061] The emitter conductive material layers 11b are connected to emitters composed of the front metal layer 9. Figure 2 In the corresponding cross section, the gate is not shown, and the corresponding front metal layer 9 is the emitter. The emitter conductive material layers 11b are also denoted as E.

[0062] Each of the gate trench structures 201 and each of the emitter trench structures 202 passes through a well region 5 doped with a second conductive type; a surface of the well region 5 covered by the side of the gate conductive material layers 11a is used to form a conductive channel of a first conductive type.

[0063] A drift region 3 doped with a first conductive type is formed at the bottom of the well region 5.

[0064] A collector region 1 heavily doped with a second conductive type is formed at the bottom of the drift region 3. A back surface of the collector region 1 is formed with a back metal layer and the collector is composed of the back metal layer. Figure 2 In the corresponding cross section, the collector is also denoted as Collector.

[0065] In the first embodiment of the present application, a buffer layer 2 heavily doped with the first conductive type is further included between the drift region 3 and the collector region 11.

[0066] A first-conductivity-type heavily doped emitter region 6 is formed in the surface region of the selected region of the well region 5.

[0067] The emitter region 6 is located on both sides of each gate trench structure 201 and is self-aligned with the side surface of the corresponding gate trench structure 201; the emitter region 6 does not contact the side surface of the emitter trench structure 202.

[0068] The top of the emitter region 6 on both sides of each gate trench structure 201 is connected to the emitter through a first contact hole 7a, the bottom of the first contact hole 7a is formed with a contact implant region (not shown) which realizes the connection between the first contact hole 7a and the well region 5.

[0069] The width of the emitter trench 204 is smaller than the width of the gate trench 203, which is used to increase the width of the mesa region between the trench structures and thus increase the distance from the first contact hole 7a to the conductive channel, thereby reducing the influence of the contact implant region on the threshold voltage of the device.

[0070] In the first embodiment of the present application, a first-conductivity-type heavily doped carrier storage layer 4 is also formed in the top region of the drift region 3.

[0071] The gate trench 203 passes through the carrier storage layer 4.

[0072] The depth of the emitter trench 204 is smaller than the depth of the gate trench 203 to reduce the in-plane stress; the emitter trench 204 and the gate trench 203 are formed simultaneously using the same etching process, and the smaller the width of the emitter trench 204, the shallower the depth of the emitter trench 204.

[0073] In some embodiments, the width of the emitter trench 204 is 0.05-0.2 μm smaller than the width of the gate trench 203. The width of the emitter trench 204 can be fine-tuned according to the actual size of the product pitch, i.e. the step.

[0074] In some embodiments, the pitch of the parallelly arranged trench structures is 1.6 μm or less than 1.2 μm. The pitch of the parallelly arranged trench structures is the sum of the width of the trench structure and the width of the platform region between the trench structures.

[0075] The bottom surface of the carrier storage layer 4 is located below the bottom surface of the emitter trench 204, so that the area of the carrier storage layer 4 is increased, which enhances the blocking effect of the minority carrier in the drift region 3 and thus increases the carrier injection effect.

[0076] In the first embodiment of the present application, the top of the well region 5 on both sides of each emitter trench structure 202 is connected to the emitter through a second contact hole 7b.

[0077] In the first embodiment of the present application, the gate trench structure 201 and the emitter trench structure 202 are arranged periodically in a ratio of m:n, m is the number of the gate trench structure 201 in the arrangement period, n is the number of the emitter trench structure 202 in the arrangement period, m is greater than or equal to 1, n is greater than or equal to 1, and further in the first embodiment of the present application, the value of m:n is 1:3.

[0078] In the first embodiment of the present application, the IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. The implanted impurities of the contact implant region include boron or boron fluoride.

[0079] In other embodiments, the IGBT device can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0080] In the first embodiment of the present application, the emitter trench structure 202 is arranged in parallel with the gate trench structure 201, by reducing the width of the emitter trench 204, i.e. the critical dimension (CD), the width of the mesa between the trench structures can be increased while keeping the average step of the entire parallel arrangement of the trench structures unchanged. In this way, the distance between the first contact hole 7a arranged on both sides of the gate trench structure 201 and the corresponding conductive channel on the side of the gate trench 203 is increased, and the distance between the contact implant region formed in the bottom of the first contact hole 7a and the conductive channel is also increased. This can reduce or prevent the impurities of the heavily doped contact implant region from affecting the doping concentration and distribution of the well region 5 at the conductive channel, thereby reducing the influence of the contact implant region on the threshold voltage of the device, and finally improving the uniformity of the threshold voltage and the uniformity of the in-plane distribution of the device.

[0081] The gate trench 203 and the emitter trench 204 in the first embodiment of the present application can be formed simultaneously using the same etching process. By utilizing the etching effect, the depth of the emitter trench 204 can be reduced while reducing the width of the emitter trench 204. The reduction of the depth of the emitter trench 204 can reduce the stress in the wafer plane, and the reduction of the stress can also reduce the difference in threshold voltage between different regions of the wafer, such as the center and the edge, thereby further improving the uniformity of the threshold voltage of the device.

[0082] In addition, the depth of the emitter trench 204 in the first embodiment of the present application can be further reduced to the bottom surface of the emitter trench 204 being above the bottom surface of the carrier storage layer 4. In this way, the area of the carrier storage layer 4 is increased, thereby reducing the leakage of minority carriers in the drift region 3 into the well region 5, thereby enhancing the carrier injection effect, and thus reducing the on-state loss of the device.

[0083] The first embodiment of the present application can effectively improve the threshold voltage uniformity of IGBT while keeping the CT imp. Mainly, by reducing the CD of Emitter TCH, i.e. the emitter trench 204, the depth of Emitter TCH will be shallower than that of Gate TCH under the same etching condition, thus increasing the width of mesa, i.e. the platform area, and reducing the stress in the wafer plane. Under the same condition, the distance between CT and the channel is increased, weakening the influence of CT imp on the channel, improving the uniformity of IGBT device VTH and the uniformity of the in-plane distribution. As shown in Figure 2 Gate TCH and Emitter TCH are arranged periodically in a ratio of 1:3, the size of Emitter TCH is about 0.05-0.2 μm smaller than that of Gate TCH, and the size is adjusted according to the product pitch. Under the same etching condition, the small CD of Emitter TCH will result in a reduced TCH depth, thus increasing the width of mesa and the alignment window of CT. Meanwhile, under the condition of increased CS injection energy, the area of CS layer is increased, enhancing the carrier injection effect and reducing the on-state loss of the device.

[0084] As shown in Figure 3 , it is a structure schematic diagram of the IGBT device of the second embodiment of the present application; and the difference between the IGBT device of the second embodiment of the present application and the IGBT device of the first embodiment of the present application is that, in the IGBT device of the second embodiment of the present application, the contact hole 7 is not arranged on the top of the well region 5 on both sides of each emitter trench structure 202, forming a floating structure.

[0085] As shown in Figure 4 , it is a structure schematic diagram of the IGBT device of the third embodiment of the present application; and the difference between the IGBT device of the third embodiment of the present application and the IGBT device of the first embodiment of the present application is that, in the IGBT device of the third embodiment of the present application, the value of m:n is 1:1.

[0086] Other embodiments can be obtained by changing the value of m:n. In some embodiments, the value of m:n can be 1:2, 2:2, 3:3.

[0087] The present application has been described in detail by specific embodiments, but these do not constitute a limitation on the present application. Those skilled in the art can make many modifications and improvements without departing from the principles of the present application, and these should also be considered as falling within the scope of protection of the present application.

Claims

1. An IGBT device, characterized in that, include: Multiple parallel groove structures; One portion of the trench structure serves as a gate trench structure and another portion of the trench structure serves as an emitter trench structure; The gate trench structure includes a gate trench, a gate dielectric layer formed on the inner surface of the gate trench, and a gate conductive material layer filled in the gate trench. The emitter trench structure includes an emitter trench, an emitter dielectric layer formed on the inner surface of the emitter trench, and an emitter conductive material layer filled in the emitter trench. The gate conductive material layer is connected to the gate, which is composed of a front metal layer; The emitter conductive material layer is connected to the emitter, which is composed of a front metal layer; Each of the gate trench structures and each of the emitter trench structures passes through a well region doped with a second conductivity type; The surface of the well region, which is covered by the side of the gate conductive material layer, is used to form a conductive channel of a first conductivity type; A drift region doped with a first conductivity type is formed at the bottom of the well region; A heavily doped collector region of a second conductivity type is formed at the bottom of the drift region; A heavily doped emitter region of a first conductivity type is formed in a selected area of ​​the surface region of the well region; The emitter region is located on both sides of each of the gate trench structures and is self-aligned with the side of the corresponding gate trench structure; the emitter region does not contact the side of the emitter trench structure; The top of the emitter region on both sides of each of the gate trench structures is connected to the emitter through a first contact hole. A contact injection region is formed at the bottom of the first contact hole, and the contact injection region connects the first contact hole and the well region. The width of the emitter trench is smaller than the width of the gate trench, which increases the width of the mesa region between the trench structures and thus increases the distance from the first contact hole to the conductive channel, thereby reducing the impact of the contact injection region on the threshold voltage of the device.

2. The IGBT device as described in claim 1, characterized in that: A carrier storage layer heavily doped with a first conductivity type is also formed in the top region of the drift region.

3. The IGBT device as described in claim 2, characterized in that: The gate trench extends through the carrier storage layer.

4. The IGBT device as described in claim 3, characterized in that: The depth of the emitter trench is less than the depth of the gate trench to reduce in-plane stress; the emitter trench and the gate trench are formed simultaneously using the same etching process; the smaller the width of the emitter trench, the shallower the depth of the emitter trench.

5. The IGBT device as described in claim 4, characterized in that: The bottom surface of the carrier storage layer is located below the bottom surface of the emitter trench to increase the carrier injection effect.

6. The IGBT device as described in claim 1, characterized in that: The top of the well region on both sides of each emitter trench structure is connected to the emitter through a second contact hole; or, no contact hole is provided on the top of the well region on both sides of each emitter trench structure to form a floating structure.

7. The IGBT device as described in claim 5, characterized in that: The gate trench structure and the emitter trench structure are arranged periodically in a ratio of m:n, where m is the number of gate trench structures in the arrangement period and n is the number of emitter trench structures in the arrangement period, and m is greater than or equal to 1 and n is greater than or equal to 1.

8. The IGBT device as described in claim 7, characterized in that: The values ​​of m:n include: 1：1，1：2，1：3，2：2，3：3。 9. The IGBT device as described in claim 1, characterized in that: A buffer layer heavily doped with a first conductivity type is also included between the drift region and the collector region.

10. The IGBT device as described in claim 4, characterized in that: The width of the emitter trench is 0.05 μm to 0.2 μm smaller than the width of the gate trench.

11. The IGBT device as described in claim 1, characterized in that: The gate dielectric layer and the emitter dielectric layer are made of the same material and are formed simultaneously. The gate conductive material layer and the emitter conductive material layer are made of the same material and are formed simultaneously.

12. The IGBT device as described in claim 11, characterized in that: The gate dielectric layer is made of an oxide layer, and the gate conductive material layer is made of polysilicon.

13. The IGBT device as described in claim 1, characterized in that: The step size of the parallel-arranged trench structures is 1.6 micrometers or less, or less than 1.2 micrometers.

14. The IGBT device according to any one of claims 1 to 13, characterized in that: IGBT devices are N-type devices, with N-type as the first conductivity type and P-type as the second conductivity type; Alternatively, the IGBT device is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

15. The IGBT device as described in claim 14, characterized in that: When the IGBT device is an N-type device, the implanted impurities in the contact injection region include boron or boron fluoride.

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