A carrier storage type trench gate field stop semi-super junction IGBT device and a preparation method thereof

Abstract

The application relates to power semiconductor technology, in particular to a carrier storage type trench gate field stop semi-super junction IGBT device and a preparation method thereof, which comprises a front cathode gate control MOS structure composed of a conductive region, an insulating layer, a conductive layer, a first type doped conductive region, a second type heavily doped conductive region and a first type heavily doped conductive region; an intermediate region drift region structure composed of a doped conductive region, a first type conductive region, a second type conductive region and a single impurity drift region; and a back anode field stop structure composed of a second type conductive layer, a first type conductive layer and a back conductive layer. The application introduces a carrier storage structure on the basis of a traditional trench gate field stop semi-super junction IGBT, enhances the conductance modulation level of the traditional semi-super junction IGBT and optimizes the compromise relationship of the device.

Description

Technical Field

[0001] This invention relates to power semiconductor technology, specifically to a carrier storage type trench gate field-stop semi-superjunction IGBT device and its fabrication method. Background Technology

[0002] Super-junction insulated-gate bipolar transistors (SJ-IGBTs) exhibit lower switching losses and better VL than conventional single-impurity drift-region IGBTs because the transverse electric field can be used for two-dimensional electric field modulation during device switching. on -E off A compromise. However, due to the limitations of the superjunction pillar's manufacturing process, it is difficult to realize high-voltage superjunction IGBT devices using a full superjunction structure. Semi-superjunction (SemiSJ) technology combines a superjunction pillar with a single impurity drift region. The resulting semi-superjunction structure can achieve a certain compromise between manufacturing difficulty and device performance while meeting the breakdown voltage requirements of high-voltage devices, thus reducing the manufacturing difficulty of high-voltage superjunction devices. Summary of the Invention

[0003] To address the aforementioned issues and optimize the trade-offs in high-voltage IGBTs, this invention provides a trench gate field-stop (Trench-FS) semi-superjunction IGBT device that combines carrier storage (CS) technology and its fabrication method. This device can utilize existing low-voltage full superjunction process platforms to achieve higher voltage levels of semi-superjunction IGBT devices.

[0004] In a first aspect, the present invention provides a carrier storage type trench gate field-stop semi-superjunction IGBT device, wherein the entire cell is symmetrical about the cell midline, and the cell includes a conductive region 1; two insulating layers 2 located on the bottom surface of the conductive region 1 and in contact with the conductive region 1; each insulating layer 2 encapsulates a conductive layer 3, and the conductive layer 3 is in contact with the insulating layer 2; each insulating layer 2 has a first type doped conductive region 4 on its bottom surface in contact with it; a first type doped conductive region 4 is also provided in the middle between the two insulating layers 2, and two second type doped conductive regions 4 are located on the front side of the first type doped conductive region 4. Two types of heavily doped conductive regions 5 and one type of heavily doped conductive region 6; the type of heavily doped conductive region 6 is located between the two types of heavily doped conductive regions 5 and is connected to conductive region 1, type of doped conductive region 4, and type of heavily doped conductive region 5; both types of heavily doped conductive regions 5 are connected to conductive region 1, insulating layer 2, and type of doped conductive region 4; conductive region 1, insulating layer 2, conductive layer 3, type of doped conductive region 4, type of heavily doped conductive region 5, and type of heavily doped conductive region 6 together form a front-side cathode gate-controlled MOS structure;

[0005] The device also includes a doped conductive region 7 located on the bottom surface of the conductive layer 3 and the bottom surface of the first type doped conductive region 4, the doped conductive region 7 being in contact with the first type doped conductive region 4; a first type conductive region 8 and a second type conductive region 9 located on the bottom surface of the doped conductive region 7 and in contact with the doped conductive region 7, the first type conductive region 8 and the second type conductive region 9 being arranged alternately; a single impurity drift region 10 located on the bottom surface of the first type conductive region 8 and the bottom surface of the second type conductive region 9; wherein, the doped conductive region 7 is a carrier storage layer; the doped conductive region 7, the first type conductive region 8, the second type conductive region 9, and the single impurity drift region 10 together form an intermediate region drift region structure;

[0006] The device also includes a second type conductive layer 11 located on and in contact with the bottom surface of the single impurity drift region 10, a first type conductive layer 12 located on and in contact with the bottom surface of the second type conductive layer 11, and a back conductive layer 13 located on and in contact with the bottom surface of the first type conductive layer 12; the second type conductive layer 11, the first type conductive layer 12, and the back conductive layer 13 together form a back anode field cutoff structure.

[0007] In a second aspect, regarding the device proposed in the first aspect, the present invention provides a method for fabricating a carrier storage type trench gate field-stop semi-superjunction IGBT device, comprising:

[0008] S1. Fabrication of intermediate region drift region structure: A single impurity drift region is formed on the substrate by epitaxial process; a superjunction pillar region is formed on the single impurity drift region by multilayer epitaxy or deep trench etching, wherein the superjunction pillar region is composed of alternating arrangement of first type conductive region and second type conductive region;

[0009] S2. Fabrication of a front-side cathode gate-controlled MOS structure: A doped conductive region is formed on the superjunction pillar region via epitaxy; then, the impurity type on the upper part of the doped conductive region is changed by ion implantation to form a first type of doped conductive region; longitudinal trenches are etched in the first type of doped conductive region, and a first insulating layer is formed on the surface of the first type of doped conductive region by thermal growth; a conductive layer is deposited on the first insulating layer portion corresponding to the longitudinal trench, and then a second insulating layer is deposited on the conductive layer and the first insulating layer; the first insulating layer and the second insulating layer together form an insulating layer; a second type of heavily doped conductive region and a first type of heavily doped conductive region are sequentially formed between the two longitudinal trenches by ion implantation; then a conductive region is formed by deposition.

[0010] S3. Preparation of back anode field cutoff structure: A second type of conductive layer and a first type of conductive layer are formed on the back side of a single impurity drift region by thinning, ion implantation, and thermal annealing in sequence; a back conductive layer is formed on the back side of the first type of conductive layer by deposition.

[0011] The beneficial effects of this invention are:

[0012] The device provided by this invention uses a first type of conductive region 8, a second type of conductive region 9, and a single impurity drift region 10 to form a semi-superjunction structure. It can realize high-voltage IGBT devices using a low-voltage superjunction process platform and can utilize the characteristics of superjunction pillars to a certain extent, thus reducing the requirements of high-voltage IGBT devices for superjunction pillars.

[0013] The semi-superjunction IGBT device formed by this invention has a wafer thickness and V on -E ts Compared to IGBTs with single-impurity drift regions of the same voltage level, the compromise relationship is significantly optimized, and the manufacturing process is significantly less difficult than that of fully superjunction IGBTs. It can provide a compromise between superjunction pillar thickness and device performance. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the structure of a carrier storage type trench gate field cutoff semi-superjunction IGBT device according to an embodiment of the present invention;

[0015] Figure 2 This is a schematic diagram of the main process flow of an embodiment of the present invention;

[0016] Figure 3 This is a schematic diagram of the superjunction process that can be used in this invention;

[0017] Figure 4 These are embodiments of the invention.

[0018] Wherein, 1-conductive region, 2-insulating layer, 3-conductive layer, 4-first type doped conductive region, 5-second type heavily doped conductive region, 6-first type heavily doped conductive region, 7-doped conductive region, 8-first type conductive region, 9-second type conductive region, 10-single impurity drift region, 11-second type conductive layer, 12-first type conductive layer, 13-back conductive layer. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] This invention provides a carrier storage type trench gate field-stop semi-superjunction IGBT device, such as... Figure 1 As shown, the entire cell is symmetrical about the cell centerline. The cell includes a conductive region 1; two insulating layers 2 located on the bottom surface of the conductive region 1 and connected to the conductive region 1; a conductive layer 3 enclosed inside each insulating layer 2, and the conductive layer 3 is connected to the insulating layer 2; a first-type doped conductive region 4 is provided on the bottom surface of each insulating layer 2 and connected to it; a first-type doped conductive region 4 is also provided between the two insulating layers 2 and connected to it; on the front of the first-type doped conductive region 4, there are two second-type heavily doped conductive regions 5 and one first-type heavily doped conductive region 6; the first-type heavily doped conductive region 6 is located between the two second-type heavily doped conductive regions 5 and is connected to the conductive region 1, the first-type doped conductive region 4, and the second-type heavily doped conductive region 5; both second-type heavily doped conductive regions 5 are connected to the conductive region 1, the insulating layer 2, and the first-type doped conductive region 4; the conductive region 1, the insulating layer 2, the conductive layer 3, the first-type doped conductive region 4, the second-type heavily doped conductive region 5, and the first-type heavily doped conductive region 6 together form a front-side cathode gate-controlled MOS structure.

[0021] The device also includes a doped conductive region 7 located on the bottom surface of the conductive layer 3 and the bottom surface of the first type doped conductive region 4, the doped conductive region 7 being in contact with the first type doped conductive region 4; a first type conductive region 8 and a second type conductive region 9 located on the bottom surface of the doped conductive region 7 and in contact with the doped conductive region 7, the first type conductive region 8 and the second type conductive region 9 being arranged alternately; a single impurity drift region 10 located on the bottom surface of the first type conductive region 8 and the bottom surface of the second type conductive region 9; wherein, the doped conductive region 7 is a carrier storage layer; the doped conductive region 7, the first type conductive region 8, the second type conductive region 9, and the single impurity drift region 10 together form an intermediate region drift region structure;

[0022] The device also includes a second type conductive layer 11 located on and in contact with the bottom surface of the single impurity drift region 10, a first type conductive layer 12 located on and in contact with the bottom surface of the second type conductive layer 11, and a back conductive layer 13 located on and in contact with the bottom surface of the first type conductive layer 12; the second type conductive layer 11, the first type conductive layer 12, and the back conductive layer 13 together form a back anode field cutoff structure.

[0023] Preferably, the insulating layer includes a transverse trench structure and a longitudinal trench structure, with the bottom of the longitudinal trench structure extending into the doped conductive region 7.

[0024] Preferably, the first type of conductive region 8 and the second type of conductive region 9 are arranged alternately to form a conductive region, and the period width of the conductive region is independent of the period width of the front cathode gate controlled MOS structure; however, the period width of the conductive region and the period width of the front cathode gate controlled MOS structure may be equal or unequal.

[0025] Preferably, the doping type of the first type conductive region 8 is different from that of the second type conductive region 9; the doping type of the doped conductive region 7 is the same as that of the first type conductive region 8, or the same as that of the second type conductive region 9. The first type doped conductive region 4 is structurally physically isolated from the first type conductive region 8 and the second type conductive region 9.

[0026] Preferably, the doping type of the doped conductive region 7 is opposite to the doping type of the first type of doped conductive region 4.

[0027] Preferably, the doping type of the single impurity drift region 10 is the same as the doping type of the first type conductive region 8, or the same as the doping type of the second type conductive region 9.

[0028] Preferably, the second type of conductive layer 11 is uniformly, non-uniformly, or multi-peak doped, and is achieved by epitaxial growth or ion implantation heating annealing process.

[0029] Preferably, the present invention has two doping types, a first type and a second type, and the first type and the second type of doping are interchangeable.

[0030] Unless otherwise specified, the conductive material involved in this invention is a semiconductor or a metal, and the semiconductor material type may be single-crystal silicon, polycrystalline silicon, silicon carbide or gallium nitride.

[0031] In one embodiment, the carrier storage type trench gate field-stop semi-superjunction IGBT device involved in this invention is as follows: Figure 4As shown, the main conductive impurity is single-crystal silicon, with the first doping type being P-type and the second doping type being N-type. Specifically, it includes a metal conductive region (Metal), two insulating oxide layers (Oxide) connected to the metal conductive region (Metal); a heavily doped semiconductor layer (Poly) connected to and encapsulated by the insulating oxide layers (Oxide); a P-type doped conductive region (P-body) connected to the insulating oxide layers (Oxide); an N-type heavily doped conductive region (N+) connected to Metal, Oxide, and P-body; and a P-type heavily doped conductive region (P+) connected to Metal, P-body, and N+. The above-mentioned Metal, Oxide, Poly, P-body, N+, and P+ together constitute the front-side MOS structure.

[0032] It also includes an N-type conductive region N-CS connected to the P-body, forming a carrier storage layer; P-type conductive regions P-pillar and N-type conductive regions N-pillar connected to the N-CS and arranged alternately, the P-type conductive regions P-pillar and N-type conductive regions N-pillar together forming a superjunction drift region; and N-type conductive regions N-drift (i.e., connected to the P-pillar and N-pillar) connected to the P-pillar and N-pillar. Figure 4 The N- in the diagram represents a lightly doped region, forming a single impurity drift region. The aforementioned N-CS, P-pillar, N-pillar, and N-drift conductive regions together constitute the semi-superjunction breakdown voltage drift region in the middle of the cell.

[0033] It also includes an N-type conductive region (N-buffer) connected to the N-drift, a P-type conductive region (P-collector) connected to the N-buffer, and a metal conductive layer (Metal) connected to the P-collector; the N-buffer, P-collector, and Metal together constitute the field-stop transparent collector structure on the back side. Specifically, the back transparent anode in this embodiment of the invention consists of an N-type field-stop layer (i.e., N-buffer) and a P-type collector region (i.e., P-collector), both of which are formed by ion implantation.

[0034] Specifically, the superjunction drift regions corresponding to N-pillar and P-pillar can be achieved using various processes, such as multiple epitaxy combined with ion implantation. Figure 3 (b) or deep trench etching combined with backfilling are both acceptable. Figure 3 (a)).

[0035] This invention provides a method for fabricating a carrier storage type trench gate field-stop semi-superjunction IGBT device, such as... Figure 2 As shown, it includes:

[0036] S1. Fabrication of intermediate region drift region structure: A single impurity drift region is formed on the substrate by epitaxial process; a superjunction pillar region is formed on the single impurity drift region by multilayer epitaxy or deep trench etching, wherein the superjunction pillar region is composed of alternating arrangement of first type conductive region and second type conductive region;

[0037] S2. Fabrication of a front-side cathode gate-controlled MOS structure: A doped conductive region is formed on the superjunction pillar region via epitaxy; then, the impurity type on the upper part of the doped conductive region is changed by ion implantation to form a first type of doped conductive region; longitudinal trenches are etched in the first type of doped conductive region, and a first insulating layer is formed on the surface of the first type of doped conductive region by thermal growth; a conductive layer is deposited on the first insulating layer portion corresponding to the longitudinal trench, and then a second insulating layer is deposited on the conductive layer and the first insulating layer; the first insulating layer and the second insulating layer together form an insulating layer; a second type of heavily doped conductive region and a first type of heavily doped conductive region are sequentially formed between the two longitudinal trenches by ion implantation; then a conductive region is formed by deposition.

[0038] S3. Preparation of back anode field cutoff structure: A second type of conductive layer and a first type of conductive layer are formed on the back side of a single impurity drift region by thinning, ion implantation, and thermal annealing in sequence; a back conductive layer is formed on the back side of the first type of conductive layer by deposition.

[0039] The principles of the present invention will be explained in detail below with reference to embodiments:

[0040] The basic principle of this invention is as follows: A semi-superjunction composite structure composed of multi-type impurity superjunction pillars and single-type impurity drift regions, combined with trench gate field cutoff and carrier storage technology, allows for the realization of high-performance high-voltage superjunction devices using a low-voltage superjunction process platform. This reduces the manufacturing difficulty of high-voltage superjunction IGBT devices on one hand, and optimizes the trade-off between high-voltage superjunction IGBTs by utilizing the characteristic of superjunctions to reduce IGBT switching losses on the other. The characteristics of the device application are: compared to classic single-impurity drift region IGBT devices, the key trade-offs are significantly optimized by introducing the semi-superjunction structure; compared to full superjunction IGBT devices, the manufacturing difficulty is reduced. The semi-superjunction IGBT device, combined with trench gate field cutoff and carrier storage technology, provides a performance-manufacturing difficulty trade-off solution between classic single-impurity drift region IGBTs and full superjunction IGBTs.

[0041] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "setting," "connection," "fixing," "rotation," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Unless otherwise explicitly limited, those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0042] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A carrier storage type trench gate field-stop semi-superjunction IGBT device, characterized in that, The entire cell is symmetrical about the cell centerline. The cell includes a conductive region (1) and two insulating layers (2) located on the bottom surface of the conductive region (1). Each insulating layer (2) is wrapped with a conductive layer (3), and each insulating layer (2) has a first type doped conductive region (4) on its bottom surface. A first type doped conductive region (4) is also provided between the two insulating layers (2). On the front of the first type doped conductive region (4), there are two second type heavily doped conductive regions (5) and one first type heavily doped conductive region (6). The first type heavily doped conductive region (6) is located between the two second type heavily doped conductive regions (5) and is connected to the conductive region (1). The two second type heavily doped conductive regions (5) are connected to the conductive region (1) and the insulating layer (2). The conductive region (1), the insulating layer (2), the conductive layer (3), the first type doped conductive region (4), the second type heavily doped conductive region (5), and the first type heavily doped conductive region (6) together form a front cathode gate controlled MOS structure. It also includes a doped conductive region (7) located on the bottom surface of the conductive layer (3) and the bottom surface of the first type doped conductive region (4); a first type conductive region (8) and a second type conductive region (9) located on the bottom surface of the doped conductive region (7), the first type conductive region (8) and the second type conductive region (9) are arranged alternately; a single impurity drift region (10) located on the bottom surface of the first type conductive region (8) and the bottom surface of the second type conductive region (9); the doped conductive region (7), the first type conductive region (8), the second type conductive region (9) and the single impurity drift region (10) together form the intermediate region drift region structure; It also includes a second type conductive layer (11) located on the bottom surface of the single impurity drift region (10), a first type conductive layer (12) located on the bottom surface of the second type conductive layer (11), and a back conductive layer (13) located on the bottom surface of the first type conductive layer (12); the second type conductive layer (11), the first type conductive layer (12), and the back conductive layer (13) together form a back anode field cutoff structure.

2. The carrier storage type trench gate field-stop semi-superjunction IGBT device according to claim 1, characterized in that, The insulating layer includes a transverse trench structure and a longitudinal trench structure, with the bottom of the longitudinal trench structure extending into the doped conductive region (7).

3. The carrier storage type trench gate field-stop semi-superjunction IGBT device according to claim 1, characterized in that, The first type of conductive region (8) and the second type of conductive region (9) are arranged alternately to form a conductive region. The period width of the conductive region is independent of the period width of the front cathode gate-controlled MOS structure.

4. The carrier storage type trench gate field-stop semi-superjunction IGBT device according to claim 1, characterized in that, The doping type of the first type conductive region (8) is different from that of the second type conductive region (9); the doping type of the doped conductive region (7) is the same as that of the first type conductive region (8) or the same as that of the second type conductive region (9).

5. A carrier storage type trench gate field-stop semi-superjunction IGBT device according to claim 1, characterized in that, The doping type of the doped conductive region (7) is opposite to that of the first type of doped conductive region (4).

6. The carrier storage type trench gate field-stop semi-superjunction IGBT device according to claim 1, characterized in that, The doping type of the single impurity drift region (10) is the same as that of the first type of conductive region (8) or the same as that of the second type of conductive region (9).

7. A carrier storage type trench gate field-stop semi-superjunction IGBT device according to claim 1, characterized in that, The second type of conductive layer (11) is uniform, non-uniform or multi-peak doped, and is achieved by epitaxial or ion implantation heating annealing process.

8. A method for fabricating a carrier storage type trench gate field-stop semi-superjunction IGBT device according to any one of claims 1-7, characterized in that, include: S1. Fabrication of intermediate region drift region structure: A single impurity drift region is formed on the substrate by epitaxial process; a superjunction pillar region is formed on the single impurity drift region by multilayer epitaxy or deep trench etching, wherein the superjunction pillar region is composed of alternating arrangement of first type conductive region and second type conductive region; S2. Fabrication of a front-side cathode gate-controlled MOS structure: A doped conductive region is formed on the superjunction pillar region via epitaxy; then, the impurity type on the upper part of the doped conductive region is changed by ion implantation to form a first-type doped conductive region; longitudinal trenches are etched in the first-type doped conductive region, and a first insulating layer is formed on the surface of the first-type doped conductive region by thermal growth; a conductive layer is deposited on the first insulating layer portion corresponding to the longitudinal trench, and a second insulating layer is deposited on the conductive layer and the first insulating layer; the first insulating layer and the second insulating layer together form an insulating layer; a second-type heavily doped conductive region and a first-type heavily doped conductive region are sequentially formed between the two longitudinal trenches by ion implantation; and then a conductive region is formed by deposition. S3. Preparation of back anode field cutoff structure: A second type of conductive layer and a first type of conductive layer are formed on the back side of a single impurity drift region by thinning, ion implantation, and thermal annealing in sequence; a back conductive layer is formed on the back side of the first type of conductive layer by deposition.

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