Insulated gate bipolar transistor manufacturing method and insulated gate bipolar transistor

Abstract

The invention belongs to the technical field of semiconductor transistors, and particularly relates to a manufacturing method of an insulated gate bipolar transistor and the insulated gate bipolar transistor. The manufacturing method comprises the steps of forming a semiconductor substrate layer doped with a first type of impurities and a supporting diffusion sheet doped with a second type of impurities, wherein the ratio of the doping concentration of the second type of impurities to the doping concentration of the first type of impurities meets a target diffusion condition; and after the support diffusion sheet is bonded on the back surface of the semiconductor substrate layer, the second type of impurities are diffused to the semiconductor substrate layer and a collector region with a first target thickness is formed in the semiconductor substrate layer. According to the insulated gate bipolar transistor, the second type of impurities of the supporting diffusion sheet are diffused into the semiconductor substrate layer to form the collector region, so that the preparation difficulty and the preparation cost of the semiconductor substrate layer are reduced, the formation process of the collector region can be simplified, and the manufacturing process of the insulated gate bipolar transistor is easier to implement.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of semiconductor transistors, and in particular relates to a method for manufacturing an insulated gate bipolar transistor and an insulated gate bipolar transistor. Background Art

[0002] Since insulated gate bipolar transistors are usually used in high-voltage applications, if an epitaxial wafer is grown on a semiconductor substrate layer, a thicker epitaxial wafer needs to be grown, which makes growth difficult and the manufacturing cost high. Summary of the invention

[0003] The purpose of the present disclosure is to provide a method for manufacturing an insulated gate bipolar transistor and an insulated gate bipolar transistor, by diffusing the second type impurities in the supporting diffusion sheet into the semiconductor base layer, so as to reduce the difficulty of preparing the semiconductor base layer and reduce the preparation cost of the semiconductor base layer.

[0004] The present disclosure provides a method for manufacturing an insulated gate bipolar transistor, the manufacturing method at least comprising:

[0005] forming a semiconductor base layer doped with first type impurities;

[0006] forming a supporting diffuser doped with second-type impurities, wherein one of the second-type impurities and the first-type impurities is an N-type impurity and the other is a P-type impurity, wherein the doping concentration of the second-type impurities in the supporting diffuser is greater than the doping concentration of the first-type impurities in the semiconductor base layer, and the ratio of the doping concentration of the second-type impurities to the doping concentration of the first-type impurities satisfies a target diffusion condition;

[0007] Bonding the supporting diffusion sheet to the back side of the semiconductor base layer, so that the second type impurities in the supporting diffusion sheet diffuse into the semiconductor base layer to form a collector region with a first target thickness in the semiconductor base layer, wherein the first target thickness is less than the thickness of the semiconductor base layer;

[0008] forming a metal oxide semiconductor field effect transistor on the front surface of the semiconductor base layer;

[0009] After forming the collector region with the first target thickness, removing the supporting diffusion sheet to expose the back side of the collector region;

[0010] A collector conductive layer is formed on the back side of the collector region to form an insulated gate bipolar transistor.

[0011] In an exemplary embodiment of the present disclosure, the step of bonding the supporting diffuser to the back side of the semiconductor base layer so that the second type impurities in the supporting diffuser diffuse to the semiconductor base layer includes:

[0012] forming an oxide layer with a second target thickness on the back side of the semiconductor base layer;

[0013] The supporting diffusion sheet is bonded to the back side of the oxide layer, so that the second type impurities in the supporting diffusion sheet diffuse into the semiconductor base layer through the oxide layer.

[0014] In an exemplary embodiment of the present disclosure, the step of forming an oxide layer with a second target thickness on the back side of the semiconductor base layer includes:

[0015] performing oxidation treatment on the back side of the semiconductor base layer so that a region of the back side of the semiconductor base layer with the second target thickness forms an oxide layer;

[0016] Wherein, the sum of the first target thickness and the second target thickness is less than the thickness of the semiconductor substrate layer.

[0017] In an exemplary embodiment of the present disclosure, the target diffusion condition includes: the ratio of the doping concentration of the second type impurity in the supporting diffuser to the doping concentration of the first type impurity in the semiconductor base layer is at least 10, and the concentration of the second type impurity in the semiconductor base layer is not less than 1*10 18 cm -3 .

[0018] In an exemplary embodiment of the present disclosure, the ratio of the first target thickness to the second target thickness ranges from 10 to 10. 3 .

[0019] In an exemplary embodiment of the present disclosure, after the step of bonding the supporting diffuser to the back side of the semiconductor base layer so that the second type impurities in the supporting diffuser diffuse to the semiconductor base layer, the metal oxide semiconductor field effect transistor is formed on the front side of the semiconductor base layer;

[0020] Wherein, during the process of forming the metal oxide semiconductor field effect transistor on the front side of the semiconductor base layer, the second type impurities in the supporting diffusion sheet can continue to diffuse toward the semiconductor base layer.

[0021] In an exemplary embodiment of the present disclosure, when the temperature reaches the target diffusion temperature, and the ratio of the preparation time of the metal oxide semiconductor field effect transistor to the bonding time of the supporting diffuser and the semiconductor base layer is in the range of 1-3, the ratio of the doping concentration of the second type impurity in the supporting diffuser to the doping concentration of the first type impurity in the semiconductor base layer is less than 5*10 2 Not less than 1*102 When , the value range of the second target thickness is:

[0022] In an exemplary embodiment of the present disclosure, when the temperature reaches the target diffusion temperature, and the ratio of the preparation time of the metal oxide semiconductor field effect transistor to the bonding time of the supporting diffuser and the semiconductor base layer is in the range of 1-3, the ratio of the doping concentration of the second type of impurities to the doping concentration of the first type of impurities is greater than or equal to 5*10 2 When , the value range of the second target thickness is:

[0023] In an exemplary embodiment of the present disclosure, after the step of forming a semiconductor base layer doped with first type impurities and before the step of bonding the supporting diffuser to the back side of the semiconductor base layer, the manufacturing method further includes:

[0024] Placing the semiconductor base layer under a target environment, and continuing to dope the first type of impurities in the back of the semiconductor base layer, so that the semiconductor base layer includes a first concentration region and a second concentration region, wherein the second concentration region is closer to the back of the semiconductor base layer than the first concentration region, and the doping concentration of the first type of impurities in the second concentration region is greater than the doping concentration of the first type of impurities in the first concentration region;

[0025] The collector region and the oxide layer are formed in the second concentration region, and the sum of the first target thickness and the second target thickness is less than the thickness of the second concentration region.

[0026] The present disclosure provides an insulated gate bipolar transistor, which is formed by any of the above-mentioned manufacturing methods.

[0027] The disclosed solution has the following beneficial effects:

[0028] The present invention first forms a semiconductor base layer doped with a first type of impurities and a supporting diffusion sheet doped with a second type of impurities, respectively. By making the doping concentration of the second type of impurities in the supporting diffusion sheet greater than the doping concentration of the first type of impurities in the semiconductor base layer, and the ratio of the doping concentration of the second type of impurities in the supporting diffusion sheet to the doping concentration of the first type of impurities in the semiconductor base layer meets the target diffusion conditions, when the supporting diffusion sheet is bonded to the back side of the semiconductor base layer, the second type of impurities in the supporting diffusion sheet can be diffused into the semiconductor base layer and form a collector region of a first target thickness. While reducing the difficulty of forming the semiconductor base layer and the manufacturing cost of the insulated gate bipolar transistor, the process of forming the collector region through steps such as high-energy ion implantation and annealing can also be reduced, thereby simplifying the formation process of the collector region, so that the manufacturing process of the insulated gate bipolar transistor is easier to implement.

[0029] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0030] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0032] Figure 1 It is a schematic flow chart of a method for manufacturing an insulated gate bipolar transistor in an embodiment of the present disclosure.

[0033] Figure 2 It is a schematic cross-sectional structure diagram of the back side bonding between the supporting diffusion sheet and the semiconductor base layer in the embodiment of the present disclosure.

[0034] Figure 3 For Figure 2 A schematic cross-sectional structure diagram of the second type of impurities diffused into the semiconductor base layer and formed a collector region based on the semiconductor base layer.

[0035] Figure 4 It is a schematic diagram of the cross-sectional structure of the semiconductor substrate layer forming the buffer zone and the drift zone in the embodiment of the present disclosure.

[0036] Figure 5 For Figure 4 Based on the cross-sectional structure diagram of the second type impurities diffusing into the buffer region and forming the collector region.

[0037] Figure 6 It is a schematic diagram of the process of bonding the supporting diffusion sheet to the semiconductor base layer in the embodiment of the present disclosure.

[0038] Figure 7 A schematic diagram of a cross-sectional structure of an oxide layer formed in an embodiment of the present disclosure.

[0039] Figure 8 Another schematic diagram of a cross-sectional structure of an oxide layer formed in an embodiment of the present disclosure is shown.

[0040] Fig. 9 FIG. 4 is a schematic diagram of a process of forming a buffer zone and an oxide layer in an embodiment of the present disclosure.

[0041] Fig.10 It is a schematic diagram of a cross-sectional structure of a metal oxide semiconductor field effect transistor in an embodiment of the present disclosure.

[0042] Fig.11 FIG. 4 is another schematic diagram of a cross-sectional structure of a metal oxide semiconductor field effect transistor in an embodiment of the present disclosure.

[0043] Fig.12 To remove Fig.10 Schematic diagram of the cross-sectional structure of the supporting diffusion sheet and the oxide layer.

[0044] Fig.13 For Fig.12 Schematic diagram of the cross-sectional structure of an insulated gate bipolar transistor formed after a conductive structure is deposited on the back side of the collector region.

[0045] Description of reference numerals:

[0046] 1. Insulated gate bipolar transistor;

[0047] 11. Support diffuser;

[0048] 12. Oxide layer;

[0049] 13. Collector area;

[0050] 14. semiconductor base layer; 141. buffer zone; 142. drift zone;

[0051] 15. Metal oxide semiconductor field effect transistor; 151. body region; 152. emitter region; 153. gate dielectric layer; 154. gate material layer; 155. emitter metal layer; 156. interlayer dielectric layer;

[0052] 16. Conductive structure. DETAILED DESCRIPTION

[0053] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more comprehensive and complete and will fully convey the concept of the example embodiments to those skilled in the art.

[0054] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the present disclosure.

[0055] The present disclosure is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present disclosure described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be understood as limiting the present disclosure.

[0056] The power semiconductor device IGBT (insulated gate bipolar transistor) is the core device for realizing power conversion. Its main uses include inversion and frequency conversion, and it is mainly used to change voltage and frequency, or convert DC to AC, AC to DC, etc. It can also accurately cycle the engine from low speed to high speed, or be used to transfer solar power to power stations, or provide stable power output for various home appliances, industrial equipment, etc., and at the same time it can have the effect of energy saving.

[0057] Insulated gate bipolar transistor is a new type of product that combines VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) technology with thyristor technology. The addition of VDMOS structure greatly improves the frequency characteristics of thyristors, and the drive changes from current drive to voltage drive; the addition of thyristor technology changes the voltage drop of VDMOS from single majority carrier conduction to dual carrier conduction, greatly reducing the conduction voltage drop, so that VDMOS devices can greatly increase the cut-off voltage, such as from less than 1000V to more than 3000V.

[0058] During the preparation process of the above-mentioned insulated gate bipolar transistor, it is necessary to form an epitaxial wafer by growing it on a supporting structure, and to prepare a metal oxide semiconductor field effect transistor on a side of the epitaxial wafer away from the supporting structure.

[0059] For example, during the preparation process of the above-mentioned insulated gate bipolar transistor, an epitaxial wafer doped with N-type impurities can be grown on a support structure doped with high concentrations of P-type impurities. Since the insulated gate bipolar transistor is usually used in high-voltage applications, the epitaxial wafer to be grown is relatively thick (e.g., 120um), which leads to the problem of difficulty in growing the epitaxial wafer and high production cost.

[0060] To solve the above technical problems, Figures 1 to 13 As shown, the embodiment of the present disclosure provides a method for manufacturing an insulated gate bipolar transistor 1, and the manufacturing method at least includes:

[0061] S1. Form a semiconductor base layer 14 doped with first type impurities.

[0062] S2. Form a supporting diffusion sheet 11 doped with second-type impurities, wherein one of the second-type impurities and the first-type impurities is an N-type impurity and the other is a P-type impurity, wherein the doping concentration of the second-type impurities in the supporting diffusion sheet 11 is greater than the doping concentration of the first-type impurities in the semiconductor base layer 14, and the ratio of the doping concentration of the second-type impurities to the doping concentration of the first-type impurities meets the target diffusion condition.

[0063] S3. Bond the supporting diffuser 11 to the back side of the semiconductor base layer 14 so that the second type impurities in the supporting diffuser 11 diffuse into the semiconductor base layer 14 to form a collector region 13 of a first target thickness in the semiconductor base layer 14, and the first target thickness is less than the thickness of the semiconductor base layer 14.

[0064] In the embodiment of the present disclosure, the semiconductor base layer 14 can be a high-purity, low-concentration single crystal silicon wafer. For example, the thickness of the semiconductor base layer 14 can be 200um-400um. For example, the thickness of the semiconductor base layer 14 can be 200um, 250um, 300um, 350um, 400um, etc. The concentration of the semiconductor base layer 14 can be 60Ω.cm-80Ω.cm. For example, the concentration of the semiconductor base layer 14 can be 60Ω.cm, 65Ω.cm, 70Ω.cm, 75Ω.cm, 80

[0065] Ω.cm and the like, but not limited thereto, the thickness and concentration of the semiconductor base layer 14 may be determined according to actual conditions.

[0066] In addition, the first type impurity implanted or diffused at the back side of the semiconductor base layer 14 according to the present disclosure may be phosphorus.

[0067] It should be noted that after the step of forming a semiconductor base layer 14 doped with the first type of impurities and before the step of bonding the supporting diffuser 11 to the back side of the semiconductor base layer 14, the method for manufacturing the insulated gate bipolar transistor 1 may include: placing the semiconductor base layer 14 in a target environment, and continuing to dope the first type of impurities on the back side of the semiconductor base layer 14, so that the semiconductor base layer 14 includes a first concentration region and a second concentration region, the second concentration region is closer to the back side of the semiconductor base layer 14 than the first concentration region, and the doping concentration of the first type of impurities in the second concentration region is greater than the doping concentration of the first type of impurities in the first concentration region.

[0068] Among them, Figures 4 to 5 As shown, the first concentration region may include a buffer region 141 , the second concentration region may include a drift region 142 , and the first type impurities may present a Gaussian distribution gradient in the buffer region 141 after diffusion.

[0069] It should be noted that the target environment mentioned above refers to placing the semiconductor base layer 14 in an environment filled with protective gas and performing a heating treatment.

[0070] Specifically, the protective gas may be an inert gas such as nitrogen (N2), argon (Ar), helium (He), etc., to protect the semiconductor base layer 14 from being oxidized. When the semiconductor base layer 14 forms the first concentration region and the second concentration region, the temperature of the heat treatment may be 1200°C, and the diffusion time of the first type of impurities on the back of the semiconductor base layer 14 may range from 3H to 5H. For example, the diffusion time of the first type of impurities on the back of the semiconductor base layer 14 may be 3 hours, 3.5 hours, 4 hours, 4.5 hours, 5 hours, etc., but not limited thereto, other temperatures and diffusion times of the heat treatment that may diffuse the first type of impurities into the semiconductor base layer 14 to form the first concentration region and the second concentration region may be included in the embodiments of the present disclosure.

[0071] In the embodiment of the present disclosure, the thickness of the formed second concentration region ranges from 10um to 30um. For example, the thickness of the second concentration region can be 10um, 15um, 20um, 25um,

[0072] 30um, etc., depending on the actual situation.

[0073] It should be understood that the thickness of the second concentration region is related to the reverse recovery time and voltage drop of the insulated gate bipolar transistor 1. The greater the thickness of the second concentration region, the longer the reverse recovery time of the insulated gate bipolar transistor 1; and the greater the thickness of the second concentration region, the lower the voltage drop of the insulated gate bipolar transistor 1. The present disclosure controls the thickness of the second concentration region, optimizes the power conversion efficiency of the insulated gate bipolar transistor 1 through the second concentration region to reduce the voltage drop, and can also alleviate or avoid the problem of a long reverse recovery time of the insulated gate bipolar transistor 1 caused by an overly thick second concentration region.

[0074] In the disclosed embodiment, the size of the support diffuser 11 may be the same as the size of the semiconductor substrate layer 14. The thickness of the support diffuser 11 may be 100um-400um, for example, the thickness of the support diffuser 11 may be 100um, 150um, 200um, 250um, 300um, 350um, 400um, etc., and may be specifically set according to factors such as the thickness of the collector region 13 and the supporting force required to be provided by the support diffuser 11 during the formation of the insulated gate bipolar transistor 1.

[0075] In addition, the embodiments of the present disclosure can form a support diffuser 11 doped with P-type impurities and a semiconductor base layer 14 doped with N-type impurities, or form a support diffuser 11 doped with N-type impurities and a semiconductor base layer 14 doped with P-type impurities, respectively. However, it is not limited thereto. Other types of impurities except N-type impurities and P-type impurities, if the ratio of the doping concentration of the impurities in the support diffuser 11 to the doping concentration of the impurities in the semiconductor base layer 14 meets the target diffusion condition, the impurities in the support diffuser 11 can diffuse into the semiconductor base layer 14 to form the collector region 13, can all be included in the scope of the embodiments of the present disclosure.

[0076] In the embodiment of the present disclosure, the target diffusion condition in step S2 is: the ratio of the doping concentration of the second type impurity in the supporting diffuser 11 to the doping concentration of the first type impurity in the semiconductor base layer 14 is at least 10, and the concentration of the second type impurity in the semiconductor base layer 14 is not less than 1*10 18 cm -3 , so that the second type impurities in the supporting diffusion sheet 11 can diffuse into the semiconductor base layer 14 and form a collector region 13 with a thickness not less than the first target thickness in the semiconductor base layer 14 .

[0077] Specifically, the concentration range of the second type of impurities in the supporting diffuser may be: 1*10 18 cm -3 -5*10 19 cm -3 The concentration of the first type of impurities in the semiconductor substrate layer 14 can range from 1 to 1017 cm -3 -5*10 17 cm -3 , but not limited to this, when the concentration of the first type impurity and the concentration of the second type impurity are in other value ranges, if the second type impurity in the semiconductor base layer 14 can be diffused into the semiconductor base layer 14, it can be included in the embodiments of the present disclosure.

[0078] In the disclosed embodiment, the collector region 13 refers to a region for forming a collector conductive layer in the insulated gate bipolar transistor 1. By ensuring that the thickness of the collector region 13 reaches the first target thickness, it can be ensured that the collector conductive layer has a sufficient thickness to provide a higher voltage blocking capability, so that the insulated gate bipolar transistor 1 can operate stably at a higher voltage.

[0079] Depending on the model and application field of the insulated gate bipolar transistor 1, the range of the operating voltage of the insulated gate bipolar transistor 1 is also different, and therefore, the range of the thickness of the collector conductive layer is also different. Generally speaking, the range of the operating voltage of the insulated gate bipolar transistor 1 can be: 600V-6500V, and accordingly, the range of the first target thickness in the embodiment of the present disclosure can be 1um-5um. Specifically, the value of the first target thickness can be: 1um, 1.5um, 2um, 2.5um, 3um, 3.5um, 4um, 4.5um, 5um, etc., which can be determined according to actual conditions.

[0080] The embodiment of the present disclosure can alleviate or avoid the problem of too long reverse recovery time of the insulated gate bipolar transistor 1 caused by too thick a collector region 13 by limiting the thickness of the collector region 13. In addition, by limiting the thickness of the collector region 13, the resistor can easily pass through the collector region 13, so that a transparent collector conductive layer is formed in the insulated gate bipolar transistor 1, and then the insulated gate bipolar transistor 1 can be quickly turned off, and the stability and reliability of the insulated gate bipolar transistor 1 can be improved.

[0081] In step S3 , “the first target thickness is smaller than the thickness of the semiconductor base layer 14 ” means that the thickness of the collector region 13 is smaller than the thickness of the semiconductor base layer 14 formed in step S1 .

[0082] It should be understood that the second type impurities in the supporting diffuser 11 are diffused into only a part of the semiconductor base layer 14, that is, a part of the semiconductor base layer 14 is diffused with the second type impurities and forms the collector region 13, while the part of the semiconductor base layer 14 that is not diffused with the second type impurities continues to be retained in the insulated gate bipolar transistor 1 as the semiconductor base layer 14. By retaining a part of the semiconductor base layer 14 as the current transmission region (for example, the buffer region 141 and the drift region 142) of the insulated gate bipolar transistor 1, it can then be used to carry current when the insulated gate bipolar transistor 1 is turned on.

[0083] Compared to the technical solution of growing an epitaxial wafer doped with the first type of impurities on a supporting diffuser 11 doped with the second type of impurities, the embodiment of the present disclosure can reduce the difficulty of forming the semiconductor base layer 14 and reduce the production cost of the semiconductor base layer 14 by separately forming a semiconductor base layer 14 of the first type of impurities and a supporting diffuser 11 doped with the second type of impurities.

[0084] In addition, the embodiment of the present disclosure makes the doping concentration of the second type impurities in the supporting diffuser 11 greater than the doping concentration of the first type impurities in the semiconductor base layer 14, and the ratio of the doping concentration of the second type impurities to the doping concentration of the first type impurities meets the target diffusion condition, so that when the supporting diffuser 11 is bonded to the back side of the semiconductor base layer 14, the second type impurities in the supporting diffuser 11 can diffuse into the semiconductor base layer 14 and form a collector region 13, thereby avoiding the need to perform high-energy ion implantation and annealing on the back side of the semiconductor base layer 14 when forming the collector region 13, thereby simplifying the manufacturing process of the insulated gate bipolar transistor 1, so that the manufacturing process of the insulated gate bipolar transistor 1 is easier to implement.

[0085] like Figures 6 to 9 As shown, in the embodiment of the present disclosure, the step of bonding the supporting diffuser 11 to the back side of the semiconductor base layer 14 so that the second type impurities in the supporting diffuser 11 diffuse into the semiconductor base layer 14 may include:

[0086] S31 , forming an oxide layer 12 with a second target thickness on the back side of the semiconductor base layer 14 .

[0087] S32 , bonding the supporting diffuser 11 to the back side of the oxide layer 12 , so that the second type impurities in the supporting diffuser 11 diffuse into the semiconductor base layer 14 through the oxide layer 12 .

[0088] In the embodiment of the present disclosure, the back side of the semiconductor base layer 14 can be oxidized so that the region of the second target thickness on the back side of the semiconductor base layer 14 is formed into an oxide layer 12. Specifically, the present disclosure can place the semiconductor base layer 14 in an oxygen-containing environment and perform a heat treatment so that the back side of the semiconductor base layer 14 is oxidized to form an oxide layer 12.

[0089] It should be noted that when the semiconductor base layer 14 in the embodiment of the present disclosure includes a first concentration region and a second concentration region, the collector region 13 and the oxide layer 12 can be formed in the second concentration region, and the sum of the first target thickness and the second target thickness is less than the thickness of the second concentration region. The process of forming the oxide layer 12 can be performed simultaneously with the process of forming the first concentration region and the second concentration region.

[0090] For example, Figures 8 to 9 As shown, the present disclosure can first place the semiconductor base layer 14 in a high-temperature environment filled with protective gas, and continue to dope the first type of impurities on the back of the semiconductor base layer 14. The protective gas here is an inert gas such as nitrogen, helium, argon, etc., and the high temperature refers to a temperature above 600°C. The temperature is gradually increased to 1200°C, and the temperature is maintained for 30 minutes to form a first concentration region and a second concentration region in the semiconductor base layer 14. Then the semiconductor base layer 14 is placed in an environment filled with oxygen (O2) to oxidize the side of the second concentration region away from the first concentration region to form an oxide layer 12. The oxidation temperature can be 1200°C and the oxidation time can be 30 minutes. After the oxide layer 12 is formed, the semiconductor base layer 14 is placed in an environment filled with protective gas again, and the semiconductor base layer 14 is reacted at a temperature of 1200°C for 180 minutes. It should be noted that when forming the oxide layer 12 and the first concentration region and the second concentration region in the insulated gate bipolar transistor 1, the protective gas introduced can play a role of cleaning, drying and protection to ensure the purity and dryness of the surface of the formed oxide layer 12 and the first concentration region and the second concentration region, thereby providing good conditions for the subsequent steps of production.

[0091] It should be understood that the thickness of the collector region 13 is related to the reverse recovery time of the insulated gate bipolar transistor 1. The greater the thickness of the collector region 13, the longer the reverse recovery time of the insulated gate bipolar transistor 1. The embodiment of the present disclosure can reduce the depth of the second type of impurities diffused into the semiconductor base layer 14 by setting the oxide layer 12, so as to reduce the thickness of the collector region 13, and further reduce the reverse recovery time of the insulated gate bipolar transistor 1. In addition, by forming the oxide layer 12, the bonding between the supporting diffusion sheet 11 and the semiconductor base layer 14 can be made more stable, and the possibility of corrosion to the collector region 13 during back thinning and corrosion can be reduced or avoided.

[0092] In the embodiment of the present disclosure, the sum of the first target thickness and the second target thickness is less than the thickness of the semiconductor substrate layer 14, and the ratio of the first target thickness to the second target thickness is in the range of 10-10. 3 Among them, the value range of the second target thickness can be: Specifically, the value of the second target thickness can be: And so on, the specific situation may depend on the actual situation.

[0093] By limiting the thickness of the oxide layer 12, the thickness of the collector region 13 can be limited to avoid the collector region 13 being too thick and causing the reverse recovery time of the insulated gate bipolar transistor 1 to be longer. At the same time, the problem that the second type of impurities cannot penetrate the oxide layer 12 due to the oxide layer 12 being too thick, thereby failing to form the collector region 13 in the semiconductor base layer 14, can also be avoided. However, the second target thickness in the embodiment of the present disclosure can also be The values ​​other than these can be specifically considered based on factors such as the concentration ratio of the first type impurities and the second type impurities, the thickness of the collector region 13, and the time and temperature of heating the semiconductor base layer 14 during the formation of the insulated gate bipolar transistor 1.

[0094] It should be noted that the back side of the oxide layer 12 mentioned above refers to the side of the oxide layer 12 facing away from the front side of the semiconductor base layer 14 .

[0095] The step of bonding the support diffuser 11 to the back of the oxide layer 12 may include: cleaning and pre-treating the oxide layer 12 and the support diffuser 11 to remove surface impurities and contaminants. The pre-treatment may include surface activation, adhesive coating and other processes. After the support diffuser 11 and the oxide layer 12 are precisely aligned, appropriate pressure may be applied to the support diffuser 11 and the oxide layer 12 to eliminate the gap between the support diffuser 11 and the oxide layer 12. The support diffuser 11 and the oxide layer 12 are heat-treated to promote the bonding of the support diffuser 11 and the oxide layer 12. The heating temperature during the bonding process of the support diffuser 11 and the oxide layer 12 may be 1200°C, and the high temperature of 1200°C may be maintained for 2 hours after bonding to diffuse the second type of impurities into the semiconductor base layer 14 to form the collector region 13.

[0096] The method for manufacturing the insulated gate bipolar transistor 1 in the embodiment of the present disclosure further includes: S4 , forming a metal oxide semiconductor field effect transistor 15 on the front surface of the semiconductor base layer 14 .

[0097] The MOSFET 15 can be formed after bonding the supporting diffuser 11 to the back side of the semiconductor base layer 14 so that the second type impurities in the supporting diffuser 11 diffuse into the semiconductor base layer 14 .

[0098] Specifically, the front side of the semiconductor base layer 14 may be thinned and polished first so that the thickness of the semiconductor base layer 14 is between 100um and 120um. The present disclosure can reduce the thickness of the semiconductor base layer 14 by thinning the semiconductor base layer 14 to reduce the voltage drop of the insulated gate bipolar transistor 1. By polishing the semiconductor base layer 14, the micro cracks and stress on the front side of the semiconductor base layer 14 can be removed, and the breakage rate of the semiconductor base layer 14 in subsequent processes can be reduced, thereby improving production efficiency. In addition, polishing the front side of the semiconductor base layer 14 can also reduce the roughness of the front side of the semiconductor base layer 14, so as to provide a better basis for subsequent process steps such as forming a metal oxide semiconductor field effect transistor 15 on the front side of the semiconductor base layer 14.

[0099] In the embodiment of the present disclosure, by providing a supporting diffusion sheet 11, a support can be formed for the semiconductor base layer 14. When the semiconductor base layer 14 is thinned and structures such as the metal oxide semiconductor field effect transistor 15 are formed on the front side of the semiconductor base layer 14, the overall thickness of the supporting diffusion sheet 11 and the semiconductor base layer 14 is relatively large, thereby improving or avoiding the fragmentation problem occurring during the manufacturing process of the insulated gate bipolar transistor 1 and facilitating the formation of the insulated gate bipolar transistor 1.

[0100] It should be noted that the insulated gate bipolar transistor 1 in the embodiment of the present disclosure may be a trench gate insulated gate bipolar transistor 1 or a planar gate insulated gate bipolar transistor 1, which may be specifically set according to actual conditions.

[0101] like Fig.10 As shown, when the insulated gate bipolar transistor 1 is a trench gate insulated gate bipolar transistor, the step of forming the metal oxide semiconductor field effect transistor 15 on the front surface of the semiconductor base layer 14 may include:

[0102] A body region 151 is formed on the front side of the semiconductor base layer 14. The body region 151 has a first groove. An emitter region 152 is formed in the first groove. The body region 151 is doped with second type impurities, and the emitter region 152 is doped with first type impurities. A groove is formed on the front side of the semiconductor base layer 14 by an etching process. The top of the groove is flush with the side of the emitter region 152 away from the semiconductor base layer 14, and the bottom of the groove is located in the semiconductor base layer 14. A gate dielectric layer 153 and a gate material layer 154 are formed in the groove. The gate dielectric layer 153 covers the inner wall of the groove, and the gate material layer 154 is located on the side of the gate dielectric layer 153 away from the semiconductor base layer 14. An emitter metal layer 155 is formed on the side of the emitter region 152 away from the semiconductor base layer 14, and the emitter metal layer 155 is in contact with the emitter region 152.

[0103] The groove can be formed by patterning and etching, the body region 151 and the emitter region 152 are formed on both sides of the groove, and the body region 151 and the emitter region 152 are both located on the front side of the semiconductor substrate layer 14, and the body region 151 surrounds the emitter region 152. The shape and size of the groove can be set according to actual conditions and are not specifically limited here.

[0104] It should be noted that the gate dielectric layer 153 and the gate material layer 154 form the gate of the insulated gate bipolar transistor 1. The gate dielectric layer 153 can be formed by oxidation growth, and the gate material layer 154 can be formed by filling polysilicon. The height of the gate material layer 154 can be slightly lower than the height of the gate dielectric layer, but is not limited thereto, and the height of the gate material layer 154 can also be flush with the height of the gate dielectric layer.

[0105] In the embodiment of the present disclosure, the emitter metal layer 155 may be formed of a metal material with a relatively high conductivity, wherein the emitter metal layer 155 may cover the entire gate. At this time, an interlayer dielectric layer 156 may be provided between the emitter metal layer 155 and the gate material layer 154 to achieve electrical isolation between the gate material layer 154 and the emitter metal layer 155. The interlayer dielectric layer 156 may be made of BPSG (boro-phospho-silicate-glass). Of course, the front structure of the planar gate insulated gate bipolar transistor is not limited to Fig.10 As shown, it may also have other forms not shown.

[0106] In addition, if Fig.11As shown, when the insulated gate bipolar transistor 1 is a planar gate insulated gate bipolar transistor, the step of forming a metal oxide semiconductor field effect transistor 15 on the side of the semiconductor base layer 14 away from the supporting diffuser 11 may include: forming a pit on the front of the semiconductor base layer 14, the pit is located on two opposite sides of the semiconductor base layer 14, forming a body region 151 in the pit, the body region 151 has a second groove, and an emitter region 152 is formed in the second groove, the body region 151 is doped with second type impurities, and the emitter region 152 is doped with first type impurities. A gate dielectric layer 153 and a gate material layer 154 are sequentially formed on the side of the emitter region 152 away from the supporting diffuser 11, and the gate dielectric layer 153 is in contact with the emitter region 152. An emitter metal layer 155 is formed on the side of the gate material layer 154 away from the semiconductor base layer 14, and the emitter metal layer 155 is in contact with the emitter region 152.

[0107] It should be noted that the body region 151 can be formed by performing doping of the second type of impurities on the front surface of the semiconductor substrate layer 14, and the gate dielectric layer 153 is formed on the front surface of the semiconductor substrate layer 14, which can be formed by oxidation growth. The gate dielectric layer 153 and the gate material layer 154 form the gate of the insulated gate bipolar transistor 1, and the emitter region 152 is located on both sides of the gate and is surrounded by the body region 151. For example, the emitter metal layer 155 can cover the entire gate, and the emitter metal layer 155 can be formed of a metal material with a higher conductivity. In this case, an interlayer dielectric layer 156 is provided between the gate material layer 154 and the emitter metal layer 155 to achieve electrical isolation between the gate material layer 154 and the emitter metal layer 155. Of course, the front structure of the planar gate insulated gate bipolar transistor is not limited to Fig.11 As shown, it may also have other forms not shown.

[0108] S5 . After forming the collector region 13 with the first target thickness, remove the supporting diffusion sheet 11 to expose the back side of the collector region 13 .

[0109] It should be noted that when the metal oxide semiconductor field effect transistor 15 is formed after the step of bonding the supporting diffuser 11 to the back side of the semiconductor base layer 14 so that the second type impurities in the supporting diffuser 11 diffuse into the semiconductor base layer 14, the second type impurities in the supporting diffuser 11 can continue to diffuse into the semiconductor base layer 14 during the process of forming the metal oxide semiconductor field effect transistor 15 on the front side of the semiconductor base layer 14. Therefore, the collector region 13 of the first target thickness may include the collector region 13 formed during the process of bonding the supporting diffuser 11 to the back side of the semiconductor base layer 14, and may also include the collector region 13 formed during the process of forming the metal oxide semiconductor field effect transistor 15 on the front side of the semiconductor base layer 14.

[0110] It should be understood that the metal oxide semiconductor field effect transistor 15 is formed after the supporting diffuser 11 is bonded to the semiconductor base layer 14 and the collector region 13 of a certain thickness is formed, and after the supporting diffuser 11 is bonded to the semiconductor base layer 14, a heating process may also be involved in the subsequent process of forming the metal oxide semiconductor field effect transistor 15. When the supporting diffuser 11 is bonded to the semiconductor base layer 14 and subjected to a heating treatment, as long as the ratio of the doping concentration of the second type impurities in the supporting diffuser 11 to the doping concentration of the first type impurities in the semiconductor base layer 14 meets the target diffusion condition and the temperature of the heating treatment reaches the target diffusion temperature, the second type impurities in the supporting diffuser 11 will continue to diffuse into the semiconductor base layer 14.

[0111] Therefore, in some embodiments of the present disclosure, when the support diffuser 11 and the semiconductor base layer 14 are bonded, the bonding temperature is made to reach the target diffusion temperature, and the target diffusion temperature is maintained for a certain time, so that after the second type impurities in the support diffuser 11 are diffused into the semiconductor base layer 14, the concentration of the second type impurities in the support diffuser 11 is reduced, and when the ratio of the doping concentration of the second type impurities to the doping concentration of the first type impurities cannot reach the target diffusion condition, in the subsequent manufacturing process of the insulated gate bipolar transistor 1, the second type impurities in the support diffuser 11 no longer diffuse into the semiconductor base layer 14. In order to ensure that the collector conductive layer of the target thickness can be formed in the collector region 13 later, the embodiment of the present disclosure needs to form the collector region 13 of the first target thickness before forming the metal oxide semiconductor field effect transistor 15, that is: when the support diffuser 11 and the semiconductor base layer 14 are placed at the target diffusion temperature and bonded for a certain time, the second type impurities in the support diffuser 11 diffuse into the semiconductor base layer 14, and the thickness of the formed collector region 13 should meet the first target thickness.

[0112] In other embodiments of the present disclosure, after the support diffuser 11 and the semiconductor base layer 14 are placed at the target diffusion temperature and bonded for a certain period of time, the concentration of the second type impurities in the support diffuser 11 decreases, and the ratio of the doping concentration of the second type impurities to the doping concentration of the first type impurities can still reach the target diffusion condition, in the subsequent manufacturing process of the insulated gate bipolar transistor 1, the second type impurities in the support diffuser 11 can continue to diffuse into the semiconductor base layer 14 to form a collector region 13 of a certain thickness. In order to alleviate or avoid the problem that the thickness of the collector region 13 is greater than the target thickness, resulting in an excessively large thickness of the collector conductive layer formed subsequently, and then resulting in a longer reverse recovery time of the insulated gate bipolar transistor 1, the embodiment of the present disclosure can make the thickness of the collector region 13 formed before forming the metal oxide semiconductor field effect transistor 15 less than the first target thickness, and the thickness of the collector region 13 formed in the process of forming the metal oxide semiconductor field effect transistor 15 is also less than the first target thickness.

[0113] It should be noted that the rated voltage of the insulated gate bipolar transistor 1 in the embodiment of the present disclosure may be 1200V, and the target diffusion temperature may be 1200°C.

[0114] Specifically, when the metal oxide semiconductor field effect transistor 15 is formed on the front surface of the semiconductor base layer 14, the second type impurities in the supporting diffuser 11 can continue to diffuse into the semiconductor base layer 14, and the temperature reaches the target diffusion temperature, and the ratio of the doping concentration of the second type impurities in the supporting diffuser 11 to the doping concentration of the first type impurities in the semiconductor base layer 14 is less than 5*10 2 Not less than 1*10 2 When the ratio of the preparation time of the metal oxide semiconductor field effect transistor 15 to the bonding time of the supporting diffuser 11 and the semiconductor base layer 14 is in the range of 1-3, the value range of the second target thickness is:

[0115] In addition, when the metal oxide semiconductor field effect transistor 15 is formed on the front surface of the semiconductor base layer 14, the second type impurities in the supporting diffuser 11 can continue to diffuse into the semiconductor base layer 14, and the temperature reaches the target diffusion temperature, and the ratio of the doping concentration of the second type impurities in the supporting diffuser 11 to the doping concentration of the first type impurities in the semiconductor base layer 14 is greater than or equal to 5*10 2 When the ratio of the preparation time of the metal oxide semiconductor field effect transistor 15 to the bonding time of the supporting diffuser 11 and the semiconductor base layer 14 is in the range of 1-3, the value range of the second target thickness is:

[0116] For example, the bonding time of the supporting diffuser 11 and the semiconductor base layer 14 can be 100 min to 150 min. For example, the specific value can be: 100 min, 110 min, 120 min, 130 min, 140 min, 150 min, etc., which can be determined according to the actual situation.

[0117] The preparation time of the metal oxide semiconductor field effect transistor 15 can be 120 minutes to 360 minutes. For example, the specific value can be: 120 minutes, 240 minutes, 360 minutes, etc., which can be determined according to actual conditions.

[0118] For example, as shown in the following Tables 1 and 2, Table 1 is a table showing the relationship between the thickness of the collector region 13 and the doping concentration of the second type of impurities in the supporting diffuser 11, the doping concentration of the first type of impurities in the semiconductor base layer 14, the thickness of the oxide layer 12, and the diffusion time when the semiconductor base layer 14 and the supporting diffuser 11 are bonded and diffused for 120 minutes at an ambient temperature of 1200°C. Table 2 is a table showing the relationship between the thickness of the collector region 13 formed in the process of preparing the metal oxide semiconductor field effect transistor 15 at the target diffusion temperature and the doping concentration of the second type of impurities in the supporting diffuser 11, the doping concentration of the first type of impurities in the semiconductor base layer 14, the thickness of the oxide layer 12, and the preparation time of the metal oxide semiconductor field effect transistor 15 at the target diffusion temperature:

[0119] Table 1

[0120]

[0121] Table 2

[0122]

[0123] Furthermore, the step of removing the supporting diffuser 11 may include: thinning the supporting diffuser 11, and completely etching and removing the supporting diffuser 11 by using hydrofluoric acid (HF) and nitric acid (HNO3), and removing the oxide layer 12 by using hydrofluoric acid etching to expose the back side of the collector region 13, for example Fig.12 shown.

[0124] It should be noted that the back side of the collector region 13 refers to the side of the collector region 13 that is away from the front side of the semiconductor base layer 14 .

[0125] S6 . Form a collector conductive layer on the back side of the collector region 13 to form an insulated gate bipolar transistor 1 .

[0126] Specifically, Fig.13 As shown, in the embodiment of the present disclosure, a conductive structure 16 such as metal can be deposited on the back side of the collector region 13 , and the conductive structure 16 can be connected to the collector region 13 to form a collector conductive layer, and then the insulated gate bipolar transistor 1 can be formed.

[0127] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0128] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and cannot be construed as limitations on the present disclosure. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and specification of the present disclosure shall fall within the scope covered by the patent of the present disclosure.

Claims

1. A method for manufacturing an insulated gate bipolar transistor, characterized in that: The production method at least comprises: forming a semiconductor base layer doped with first type impurities; forming a supporting diffuser doped with second-type impurities, wherein one of the second-type impurities and the first-type impurities is an N-type impurity and the other is a P-type impurity, wherein the doping concentration of the second-type impurities in the supporting diffuser is greater than the doping concentration of the first-type impurities in the semiconductor base layer, and the ratio of the doping concentration of the second-type impurities to the doping concentration of the first-type impurities satisfies a target diffusion condition; Bonding the supporting diffusion sheet to the back side of the semiconductor base layer, so that the second type impurities in the supporting diffusion sheet diffuse into the semiconductor base layer to form a collector region with a first target thickness in the semiconductor base layer, wherein the first target thickness is less than the thickness of the semiconductor base layer; forming a metal oxide semiconductor field effect transistor on the front surface of the semiconductor base layer; After forming the collector region with the first target thickness, removing the supporting diffusion sheet to expose the back side of the collector region; A collector conductive layer is formed on the back side of the collector region to form an insulated gate bipolar transistor.

2. The method according to claim 1, characterized in that: The step of bonding the supporting diffusion sheet to the back side of the semiconductor base layer so that the second type impurities in the supporting diffusion sheet diffuse into the semiconductor base layer comprises: forming an oxide layer with a second target thickness on the back side of the semiconductor base layer; The supporting diffusion sheet is bonded to the back side of the oxide layer, so that the second type impurities in the supporting diffusion sheet diffuse into the semiconductor base layer through the oxide layer.

3. The method according to claim 2, characterized in that: The step of forming an oxide layer of a second target thickness on the back side of the semiconductor base layer comprises: performing oxidation treatment on the back side of the semiconductor base layer so that a region of the back side of the semiconductor base layer with the second target thickness forms an oxide layer; Wherein, the sum of the first target thickness and the second target thickness is less than the thickness of the semiconductor substrate layer.

4. The method according to claim 2, characterized in that: The target diffusion conditions include: the ratio of the doping concentration of the second type impurity in the supporting diffuser to the doping concentration of the first type impurity in the semiconductor base layer is at least 10, and the concentration of the second type impurity in the semiconductor base layer is not less than 1*10 18 cm -3 .

5. The manufacturing method according to claim 4, characterized in that: The ratio of the first target thickness to the second target thickness is in the range of: 10-10 3 .

6. The method according to claim 5, characterized in that: After bonding the supporting diffusion sheet to the back side of the semiconductor base layer so that the second type impurities in the supporting diffusion sheet diffuse into the semiconductor base layer, the metal oxide semiconductor field effect transistor is formed on the front side of the semiconductor base layer; Wherein, during the process of forming the metal oxide semiconductor field effect transistor on the front side of the semiconductor base layer, the second type impurities in the supporting diffusion sheet can continue to diffuse toward the semiconductor base layer.

7. The manufacturing method according to claim 6, characterized in that: When the temperature reaches the target diffusion temperature, and the ratio of the preparation time of the metal oxide semiconductor field effect transistor to the bonding time of the supporting diffuser and the semiconductor base layer is in the range of 1-3, the ratio of the doping concentration of the second type impurity in the supporting diffuser to the doping concentration of the first type impurity in the semiconductor base layer is less than 5*10 2 Not less than 1*10 2 When , the value range of the second target thickness is:

8. The manufacturing method according to claim 6, characterized in that: When the temperature reaches the target diffusion temperature, and the ratio of the preparation time of the metal oxide semiconductor field effect transistor to the bonding time of the supporting diffuser and the semiconductor base layer is in the range of 1-3, the ratio of the doping concentration of the second type of impurities to the doping concentration of the first type of impurities is greater than or equal to 5*10 2 When , the value range of the second target thickness is:

9. The manufacturing method according to claim 2, characterized in that: After the step of forming a semiconductor base layer doped with first type impurities and before the step of bonding the supporting diffuser to the back side of the semiconductor base layer, the manufacturing method further includes: Placing the semiconductor base layer under a target environment, and continuing to dope the first type of impurities in the back of the semiconductor base layer, so that the semiconductor base layer includes a first concentration region and a second concentration region, wherein the second concentration region is closer to the back of the semiconductor base layer than the first concentration region, and the doping concentration of the first type of impurities in the second concentration region is greater than the doping concentration of the first type of impurities in the first concentration region; The collector region and the oxide layer are formed in the second concentration region, and the sum of the first target thickness and the second target thickness is less than the thickness of the second concentration region.

10. An insulated gate bipolar transistor, characterized in that: The method is formed by any one of claims 1 to 9.

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