Formation method of semiconductor structure
By adopting a method including forming a sacrificial layer, a stacked structure, a protective layer, a dummy gate structure and a doped layer in semiconductor manufacturing, the problem of short channel effect in semiconductor structures is solved, and the formation quality and performance of the structure are improved.
Patent Information
- Application Number
- CN202311260951.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-26
- Publication Date
- 2025-03-28
AI Technical Summary
In semiconductor manufacturing, as the device channel length shortens, the gate structure's control ability of the channel becomes worse, resulting in a short channel effect that is more likely to occur, affecting the formation quality and performance of the semiconductor structure.
A semiconductor structure formation method is adopted, including providing a substrate, forming a first sacrificial layer and a stacked structure, forming a first protective layer covering the side walls and top of the stacked structure, forming a dummy gate structure and removing the first sacrificial layer, forming an isolation layer and a source-drain doped layer to improve channel control capability and structure quality.
Through this method, the formation quality of the semiconductor structure can be improved, the gate control ability of the channel can be enhanced, the short channel effect can be reduced, and the performance of the semiconductor structure can be improved.
Smart Images
Figure CN119730279A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art
[0002] In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also shortened accordingly. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, so the control ability of the gate structure over the channel becomes worse, and the difficulty of pinching off the channel by the gate voltage becomes increasingly greater, making subthreshold leakage, the so-called short-channel effects (SCE), more likely to occur.
[0003] Therefore, in order to better adapt to the requirements of device size reduction, semiconductor processes have gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In a metal-all-around transistor, the gate surrounds the channel area from all sides. Compared with planar transistors, the gate of a metal-all-around transistor has a stronger control ability over the channel and can better suppress the short channel effect. Summary of the invention
[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to ensure the formation quality of the semiconductor structure.
[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, a first sacrificial layer is formed on the substrate, a stacked structure is formed on the first sacrificial layer, the stacked structure includes one or more stacked channel stacks, the channel stack includes a second sacrificial layer and a channel layer located on the second sacrificial layer, wherein the etching resistance of the second sacrificial layer is greater than that of the first sacrificial layer; forming a first protective layer covering the sidewalls and top of the stacked structure; forming a pseudo-gate structure spanning the stacked structure and the first sacrificial layer on the substrate, the pseudo-gate structure covering part of the sidewalls and part of the top of the stacked structure, the first protective layer, and part of the sidewalls of the first sacrificial layer; after forming the pseudo-gate structure, removing the first sacrificial layer to form a groove passing through the bottom of the stacked structure; forming an isolation layer in the groove; forming a source-drain doping layer on the isolation layer on both sides of the pseudo-gate structure, the source-drain doping layer is in contact with the channel stack below the pseudo-gate structure.
[0006] Optionally, in the step of providing the substrate, a second protective layer is formed between the first sacrificial layer and the stacked structure; and in the step of removing the first sacrificial layer, the second protective layer at the bottom of the stacked structure is exposed.
[0007] Optionally, in the step of providing a substrate, the thickness of the second protective layer is less than or equal to 10 nm.
[0008] Optionally, the material of the second protective layer includes silicon.
[0009] Optionally, in the step of providing a substrate, the substrate includes a substrate and a bottom fin protruding from the substrate, and a first sacrificial layer is located on the bottom fin; before forming a first protective layer covering the side walls and top of the stacked structure, the formation method also includes: forming an isolation structure covering the side walls of the bottom fin on the substrate, wherein the top of the isolation structure is lower than the bottom of the stacked structure and higher than the bottom of the first sacrificial layer; after forming the first protective layer covering the side walls and top of the stacked structure, before forming the pseudo gate structure, it also includes: removing a portion of the thickness of the isolation structure, wherein the top of the remaining isolation structure is lower than the bottom of the first sacrificial layer.
[0010] Optionally, in the step of forming an isolation structure covering the sidewall of the bottom fin on the substrate, a distance between a top of the isolation structure and a bottom of the stacked structure is 1 nm to 10 nm.
[0011] Optionally, in the step of removing a portion of the thickness of the isolation structure, a distance between a top of the remaining isolation structure and a bottom of the first sacrificial layer is 1 nm to 20 nm.
[0012] Optionally, after removing the first sacrificial layer and before forming the source-drain doping layer on the isolation layer at both sides of the dummy gate structure, the forming method further includes: forming a gate sidewall covering the sidewall of the dummy gate structure.
[0013] Optionally, the gate sidewall spacer and the isolation layer in the trench are formed in the same step.
[0014] Optionally, the step of forming an isolation layer in the trench includes: forming an isolation material layer filling the trench and covering the sidewalls of the dummy gate structure, wherein the isolation material layer in the trench is retained as the isolation layer, and the isolation material layer covering the sidewalls of the dummy gate structure is retained as the gate sidewall.
[0015] Optionally, in the step of forming the isolation material layer, an atomic layer deposition process is used to form the isolation material layer.
[0016] Optionally, the step of forming a source-drain doped layer on the isolation layer on both sides of the dummy gate structure includes: removing the stacked structure on both sides of the dummy gate structure and the first protective layer covering the stacked structure to expose the end of the remaining stacked structure under the dummy gate structure; and forming a source-drain doped layer in contact with the end of the remaining stacked structure.
[0017] Optionally, after removing the stacked structure on both sides of the pseudo gate structure and the first protective layer covering the stacked structure, and before forming a source-drain doped layer in contact with the end of the remaining stacked structure, the formation method also includes: removing a portion of the width of the second sacrificial layer in a direction perpendicular to the side wall of the pseudo gate structure to form a groove; forming an inner side wall in the groove; in the step of forming the source-drain doped layer in contact with the end of the remaining stacked structure, the source-drain doped layer and the second sacrificial layer are isolated from each other by the inner side wall.
[0018] Optionally, after forming the source and drain doping layers, the formation method also includes: forming an interlayer dielectric layer covering the side walls of the pseudo-gate structure and the source and drain doping layers, the interlayer dielectric layer exposing the top of the pseudo-gate structure; removing the pseudo-gate structure, forming a gate opening in the interlayer dielectric layer, the gate opening exposing the first protective layer; removing the first protective layer to expose the stacked structure; after removing the first protective layer, removing the second sacrificial layer through the gate opening; after removing the second sacrificial layer, forming a gate structure in the gate opening, the gate structure including a gate dielectric layer surrounding the channel layer along the extension direction of the gate structure, and a gate electrode layer located on the gate dielectric layer, and the bottom of the gate structure and the substrate are isolated by an isolation layer.
[0019] Optionally, in the step of removing the first sacrificial layer, an etching selectivity ratio between the first sacrificial layer and the second sacrificial layer is greater than 2, and an etching selectivity ratio between the first sacrificial layer and the first protective layer is greater than 5.
[0020] Optionally, in the step of providing a substrate, the material of the first sacrificial layer includes silicon germanium, the material of the second sacrificial layer includes silicon germanium, and the material of the channel layer includes silicon, wherein the molar concentration of the germanium element in the first sacrificial layer is greater than the molar concentration of the germanium element in the second sacrificial layer.
[0021] Optionally, the molar concentration of the germanium element in the first sacrificial layer is 15% to 80%, and the molar concentration of the germanium element in the second sacrificial layer is 5% to 50%.
[0022] Optionally, in the step of forming a first protection layer covering the sidewalls and the top of the stacked structure, the material of the first protection layer includes silicon.
[0023] Optionally, in the step of forming a first protective layer covering the sidewalls and the top of the stacked structure, the thickness of the first protective layer is 1 nm to 4 nm.
[0024] Optionally, in the step of providing a substrate, the thickness of the first sacrificial layer is 3 nm to 30 nm.
[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0026] In the formation method provided by the embodiment of the present invention, a first protective layer covering the sidewalls and the top of the stacked structure is formed, and a pseudo-gate structure spanning the stacked structure and the first sacrificial layer is also formed on the substrate, the pseudo-gate structure covers part of the sidewalls and part of the top of the stacked structure, and part of the sidewalls of the first sacrificial layer. After the pseudo-gate structure is formed, the first sacrificial layer is removed to form a groove penetrating the bottom of the stacked structure, an isolation layer is formed in the groove, and a source-drain doping layer is formed on the isolation layer on both sides of the pseudo-gate structure, and the source-drain doping layer is in contact with the channel stack below the pseudo-gate structure. In the embodiment of the present invention, the method of first forming a first sacrificial layer to occupy a spatial position for the isolation layer and then removing the first sacrificial layer to form an isolation layer is conducive to the growth of the stacked structure located on the first sacrificial layer, and The material of the first sacrificial layer can be flexibly selected according to process requirements to improve the process compatibility of the first sacrificial layer. Moreover, in an embodiment of the present invention, a first protective layer covering part of the side walls and part of the top of the stacked structure is first formed, and then the first sacrificial layer is removed. This is beneficial to protecting the stacked structure in the process of removing the first sacrificial layer and reducing damage to the stacked structure, which is beneficial to ensuring the formation quality of the semiconductor structure and further ensuring the performance of the semiconductor structure. In addition, after the second sacrificial layer is subsequently removed to form a gate structure, the gate structure is formed on the isolation layer, and the isolation layer effectively isolates the contact between the gate structure and the substrate, thereby reducing the probability of leakage current between the gate structure and the substrate. At the same time, when the channel layer is turned on, the parasitic capacitance of the substrate caused by being turned on is reduced or avoided. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figures 1 to 3 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;
[0028] Figures 4 to 22 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0029] At present, the formation quality of semiconductor structures needs to be improved. Now, the reasons why the formation quality needs to be improved are analyzed in combination with a formation method of a semiconductor structure.
[0030] Figures 1 to 3 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.
[0031] refer to Figure 1A substrate 10 is provided, a first sacrificial layer 24 is formed on the substrate 10, a stacked structure 20 is formed on the first sacrificial layer 24, the stacked structure 20 includes one or more channel stacks 21, the channel stack 21 includes a second sacrificial layer 22 and a channel layer 23 located on the second sacrificial layer 22, and a dummy gate structure (not shown) spanning the stacked structure 20 is also formed on the substrate 10, the dummy gate structure covers part of the sidewalls and part of the top of the stacked structure 20, and part of the sidewalls of the first sacrificial layer 24.
[0032] refer to Figure 2 , remove the first sacrificial layer 24 to form a groove 25 penetrating the bottom of the stacked structure 20.
[0033] refer to Figure 3 , an isolation layer 26 is formed in the trench 25 .
[0034] Since the stacked structure 20 located on both sides of the pseudo-gate structure is exposed to the environment of removing the first sacrificial layer 24, the stacked structure 20 is easily damaged during the process of removing the first sacrificial layer 24, making it difficult to ensure the formation quality of the semiconductor structure and further the performance of the semiconductor structure.
[0035] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, a first sacrificial layer is formed on the substrate, a stacked structure is formed on the first sacrificial layer, the stacked structure includes one or more stacked channel stacks, the channel stack includes a second sacrificial layer and a channel layer located on the second sacrificial layer, wherein the etching resistance of the second sacrificial layer is greater than that of the first sacrificial layer; forming a first protective layer covering the side walls and top of the stacked structure; forming a pseudo-gate structure spanning the stacked structure and the first sacrificial layer on the substrate, the pseudo-gate structure covering part of the side walls and part of the top of the stacked structure, and part of the side walls of the first sacrificial layer; after forming the pseudo-gate structure, removing the first sacrificial layer to form a groove passing through the bottom of the stacked structure; forming an isolation layer in the groove; forming a source-drain doping layer on the isolation layer on both sides of the pseudo-gate structure, the source-drain doping layer is in contact with the channel stack below the pseudo-gate structure.
[0036] In an embodiment of the present invention, a method of forming an isolation layer by first forming a first sacrificial layer to occupy a spatial position for the isolation layer and then removing the first sacrificial layer is beneficial to the growth of the stacked structure located on the first sacrificial layer, and the material of the first sacrificial layer can be flexibly selected according to process requirements to improve the process compatibility of the first sacrificial layer. Moreover, in an embodiment of the present invention, a first protective layer covering part of the sidewalls and part of the top of the stacked structure is first formed and then the first sacrificial layer is removed. This is beneficial to protecting the stacked structure during the removal of the first sacrificial layer and reducing damage to the stacked structure, thereby facilitating the formation quality of the semiconductor structure and further ensuring the performance of the semiconductor structure. In addition, after the second sacrificial layer is subsequently removed to form a gate structure, the gate structure is formed on the isolation layer, and the isolation layer effectively isolates the contact between the gate structure and the substrate, thereby reducing the probability of leakage current between the gate structure and the substrate. At the same time, when the channel layer is turned on, the situation in which the parasitic capacitance of the substrate increases due to being turned on is reduced or avoided.
[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0038] Figures 4 to 22 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0039] refer to Figure 4 , providing a substrate (not marked), a first sacrificial layer 240 is formed on the substrate, a stacked structure 200 is formed on the first sacrificial layer 240, the stacked structure 200 includes one or more stacked channel stacks 210, the channel stack 210 includes a second sacrificial layer 220 and a channel layer 230 located on the second sacrificial layer 220, wherein the etching resistance of the second sacrificial layer 220 is greater than the etching resistance of the first sacrificial layer 240.
[0040] The substrate provides a process operation basis for the formation process of the semiconductor structure, wherein the semiconductor structure includes a fully surrounded gate transistor and a forked gate transistor.
[0041] The base includes a substrate 100 and a bottom fin 120 protruding from the substrate 100 , and a first sacrificial layer 240 is located on the bottom fin 120 .
[0042] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy to integrate.
[0043] The channel layer 230 in the stacked structure 200 is used as a channel of the semiconductor structure, and the second sacrificial layer 220 is used to provide a process basis for the subsequent suspended arrangement of the channel layer 230, and is also used to occupy a space position for the gate structure formed subsequently. In the subsequent process, the second sacrificial layer 220 is removed, so that the channel layer 230 is suspended, and a gate structure is formed between the channel layer 230 and the substrate, and between adjacent channel layers 230.
[0044] The surface of the channel layer 230 covered by the gate structure is used as a channel. In this embodiment, the top, bottom and sidewalls of the channel layer 230 can all be used as channels, increasing the area of the channel layer 230 used as a channel, thereby increasing the operating current of the semiconductor structure.
[0045] In this embodiment, the material of the channel layer 230 includes silicon, germanium, silicon germanium or III-V semiconductor materials. As an example, the material of the channel layer 230 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.
[0046] It should be noted that, in this embodiment, the channel layer 230 and the substrate 100 are made of the same material. In other embodiments, the channel layer and the substrate may be made of different materials.
[0047] In this embodiment, the material of the second sacrificial layer 220 includes silicon germanium.
[0048] Silicon germanium and silicon can form a larger etching selectivity ratio, which is beneficial to the subsequent removal of the second sacrificial layer 220 and reduces damage to the channel layer 230 .
[0049] In other embodiments, the second sacrificial layer may be made of a suitable material having an etching selectivity ratio with the channel layer according to the material of the channel layer, so as to reduce damage to the channel layer when the second sacrificial layer is subsequently removed.
[0050] The first sacrificial layer 240 occupies a space for the isolation layer to be formed later.
[0051] In an embodiment of the present invention, a method of forming an isolation layer by first forming a first sacrificial layer 240 to occupy a spatial position for the isolation layer and then removing the first sacrificial layer 240 is beneficial to the growth of the stacked structure 200 located on the first sacrificial layer 240, and the material of the first sacrificial layer 240 can be flexibly selected according to process requirements, thereby improving the process compatibility of the first sacrificial layer 240.
[0052] In this embodiment, the etching resistance of the second sacrificial layer 220 is greater than that of the first sacrificial layer 240, which is beneficial to the subsequent removal of the first sacrificial layer 240 and reduces the damage to the second sacrificial layer 220 during the subsequent removal of the first sacrificial layer 240, or, only partially removes the second sacrificial layer 220 during the subsequent removal of the first sacrificial layer 240.
[0053] It should be noted that, in the step of providing a substrate in this embodiment, the thickness d0 of the first sacrificial layer 240 should not be too large or too small. If the thickness d0 of the first sacrificial layer 240 is too large, it is easy to cause unnecessary process waste. Moreover, the first sacrificial layer 240 occupies a space position for the subsequent formation of an isolation layer, and then the first sacrificial layer 240 is removed. After removing the first sacrificial layer 240, the isolation layer is formed again. Therefore, if the thickness d0 of the first sacrificial layer 240 is too large, the thickness of the isolation layer is also too large, which is also easy to cause unnecessary process waste and increase the process difficulty of removing the first sacrificial layer 240. Moreover, after removing the first sacrificial layer 240, it is necessary to fill the space occupied by the first sacrificial layer 240 to obtain the isolation layer. If the thickness d0 of the first sacrificial layer 240 is too large, the corresponding occupied space is too large, which is easy to cause incomplete filling, affecting the formation quality of the isolation layer, thereby affecting the isolation effect of the isolation layer; if the thickness d0 of the first sacrificial layer 240 is too small, the thickness of the isolation layer formed subsequently is too small, which is easy to affect the isolation performance of the isolation layer, making it difficult to completely isolate the gate structure and the substrate, affecting the performance of the semiconductor structure. To this end, in this embodiment, in the step of providing the substrate, the thickness d0 of the first sacrificial layer 240 is 3 nm to 30 nm.
[0054] In this embodiment, the material of the first sacrificial layer 240 includes silicon germanium, which is conducive to the epitaxial growth of the first sacrificial layer 240 on the substrate. At the same time, it is also conducive to the epitaxial growth of the stacked structure 200 on the first sacrificial layer 240, thereby improving the process compatibility of the first sacrificial layer 240, so that the first sacrificial layer 240 and the stacked structure 200 can be grown on the substrate in the same process using an epitaxial growth process.
[0055] In this embodiment, the molar concentration of germanium in the first sacrificial layer 240 is greater than the molar concentration of germanium in the second sacrificial layer 220 , so that the etching resistance of the first sacrificial layer 240 is greater than that of the second sacrificial layer 220 .
[0056] In this embodiment, the material of the first sacrificial layer 240 includes silicon germanium, and the material of the second sacrificial layer 220 includes silicon germanium, which is conducive to the epitaxial growth of the first sacrificial layer 240 on the substrate, and at the same time, is conducive to the epitaxial growth of the second sacrificial layer 220 on the first sacrificial layer 240, thereby forming a second sacrificial layer 220 with better quality.
[0057] It should be noted that, in this embodiment, the molar concentration of the germanium element in the first sacrificial layer 240 should not be too large or too small. If the molar concentration of the germanium element in the first sacrificial layer 240 is too large, it is easy to cause defects in the formation of the first sacrificial layer 240, affecting the film quality of the first sacrificial layer 240; if the molar concentration of the germanium element in the first sacrificial layer 240 is too small, it is easy to cause the etching resistance of the first sacrificial layer 240 to be too large, and the first sacrificial layer 240 is not easy to be etched, which makes it difficult to remove the first sacrificial layer 240 later. For this reason, in this embodiment, the molar concentration of the germanium element in the first sacrificial layer 240 is 15% to 80%.
[0058] It should also be noted that, in this embodiment, the molar concentration of the germanium element in the second sacrificial layer 220 should not be too large or too small. Since the channel layer 230 is obtained by epitaxial growth on the second sacrificial layer 220, if the molar concentration of the germanium element in the second sacrificial layer 220 is too large, when the channel layer 230 is formed, the transition layer required for the transition from the material of the second sacrificial layer 220 to the material of the channel layer 230 is too thick, resulting in the effective thickness of the formed channel layer 230 being too small, affecting the quality of the channel layer 230, thereby affecting the performance of the semiconductor structure; if the molar concentration of the germanium element in the second sacrificial layer 220 is too small, the etching resistance of the second sacrificial layer 220 is too large, the second sacrificial layer 220 is not easy to be etched, causing difficulties in the subsequent removal of the second sacrificial layer 220, and at the same time, it is easy to cause the etching selectivity ratio of the second sacrificial layer 220 and the channel layer 230 to be too small, thereby causing damage to the channel layer 230 in the process of removing the second sacrificial layer 220, affecting the performance of the semiconductor structure. To this end, in this embodiment, the molar concentration of germanium in the second sacrificial layer 220 is 5% to 50%.
[0059] In this embodiment, in the step of providing a substrate, a second protection layer 320 is formed between the first sacrificial layer 240 and the stacked structure 200 .
[0060] The second protection layer 320 is used to protect the bottom of the stacked structure 200 and reduce damage to the bottom of the stacked structure 200 in the subsequent step of removing the first sacrificial layer 240 .
[0061] It should be noted that, in the step of providing a substrate in this embodiment, the thickness d2 of the second protective layer 320 should not be too large. If the thickness d2 of the second protective layer 320 is too large, it is easy to cause the height of the stacked structure 200 to be too large, affecting the integration of the semiconductor structure, and it is also easy to cause too much remaining second protective layer 320 after the subsequent removal of the first sacrificial layer 240 and the second sacrificial layer 220, affecting the working performance of the semiconductor structure. For this reason, in the step of providing a substrate in this embodiment, the thickness d2 of the second protective layer 320 is less than or equal to 10nm.
[0062] In this embodiment, the material of the second protection layer 320 includes silicon.
[0063] The material of the second protective layer 320 is silicon, and the material of the first sacrificial layer 240 is silicon germanium. In the subsequent step of removing the first sacrificial layer 240, the etching selectivity of the first sacrificial layer 240 and the second protective layer 320 is relatively large, which can reduce the damage to the second protective layer 320 in the process of removing the first sacrificial layer 240, so that the protection effect of the second protective layer 320 is better.
[0064] Continue to refer Figure 4 Before subsequently forming a first protective layer covering the sidewalls and top of the channel stack 200, the formation method also includes: forming an isolation structure 110 covering the sidewalls of the bottom fin 120 on the substrate 100, and the top of the isolation structure 110 is lower than the bottom of the stack structure 200 and higher than the bottom of the first sacrificial layer 240.
[0065] The isolation structure 110 is used to achieve insulation between different devices. For example, in a CMOS manufacturing process, the isolation structure 110 is usually formed between an NMOS transistor and a PMOS transistor.
[0066] In the present embodiment, the top of the isolation structure 110 is lower than the bottom of the stacked structure 200, so that the first protective layer formed subsequently can completely cover the top and side walls of the stacked structure 200, and the top of the isolation structure 110 is higher than the bottom of the first sacrificial layer 240, so that the first protective layer formed subsequently will not completely cover the first sacrificial layer 240, thereby enabling the first sacrificial layer 240 exposed through the first protective layer to be removed subsequently.
[0067] In this embodiment, the material of the isolation structure 110 is an insulating material. As an example, in this embodiment, the material of the isolation structure 110 is silicon oxide.
[0068] It should be noted that, in the present embodiment, in the step of forming the isolation structure 110 covering the sidewall of the bottom fin 120 on the substrate 100, the spacing d1 between the top of the isolation structure 110 and the bottom of the stacked structure 200 should not be too large or too small. If the spacing d1 between the top of the isolation structure 110 and the bottom of the stacked structure 200 is too large, it is easy to cause too much of the first sacrificial layer 240 exposed by the isolation structure 110, and the first protective layer formed subsequently covers too much of the first sacrificial layer 240, which is easy to cause difficulties in the subsequent removal of the first sacrificial layer 240; if the spacing d1 between the top of the isolation structure 110 and the bottom of the stacked structure 200 is too small, it is easy to cause the first protective layer formed subsequently to not completely cover the stacked structure 200 due to process errors, so that in the process of removing the first sacrificial layer 240 later, the first protective layer has a poor protective effect on the stacked structure 200. To this end, in this embodiment, in the step of forming the isolation structure 110 covering the sidewalls of the bottom fin 120 on the substrate 100 , the distance d1 between the top of the isolation structure 110 and the bottom of the stacked structure 200 is 1 nm to 10 nm.
[0069] refer to Figure 5 , forming a first protection layer 310 covering the sidewalls and the top of the stacked structure 200 .
[0070] The first protection layer 310 is used to protect the sidewalls and the top of the stacked structure 200 during the subsequent removal of the first sacrificial layer 240 , thereby reducing damage to the stacked structure 200 .
[0071] In the present embodiment, a first protective layer 310 is first formed to cover part of the sidewalls and part of the top of the stacked structure 200, and then the first sacrificial layer 240 is removed. This is beneficial for protecting the stacked structure 200 during the removal of the first sacrificial layer 240 and reducing damage to the stacked structure 200, thereby facilitating the formation quality of the semiconductor structure and further ensuring the performance of the semiconductor structure.
[0072] It should be noted that, in the present embodiment, in the step of forming the first protective layer 310 covering the sidewalls and the top of the stacked structure 200, the thickness d3 of the first protective layer 310 should not be too large or too small. If the thickness d3 of the first protective layer 310 is too large, it is easy to cause unnecessary waste and difficulty in the subsequent removal of the first protective layer 310; if the thickness d3 of the first protective layer 310 is too small, it is easy to cause the first protective layer 310 to have a poor protective effect on the stacked structure 200 during the removal of the first sacrificial layer 240, and it is difficult to reduce the damage to the stacked structure 200. For this reason, in the present embodiment, in the step of forming the first protective layer 310 covering the sidewalls and the top of the stacked structure 200, the thickness d3 of the first protective layer 310 is 1nm to 4nm.
[0073] In this embodiment, in the step of forming the first protection layer 310 covering the sidewalls and the top of the stacked structure 200 , the material of the first protection layer 310 includes silicon.
[0074] The material of the first protective layer 310 is silicon, and the material of the first sacrificial layer 240 is silicon germanium. In the subsequent step of removing the first sacrificial layer 240, the etching selectivity of the first sacrificial layer 240 and the first protective layer 310 is relatively large, which can reduce the damage to the first protective layer 310 in the process of removing the first sacrificial layer 240, so that the protection effect of the first protective layer 310 is better.
[0075] refer to Figure 6 After forming the first protection layer 310 covering the sidewalls and top of the stacked structure 200 , and before subsequently forming the pseudo gate structure, it also includes: removing a portion of the thickness of the isolation structure 110 , and the top of the remaining isolation structure 110 is lower than the bottom of the first sacrificial layer 240 .
[0076] A portion of the thickness of the isolation structure 110 is removed to expose the sidewall of the first sacrificial layer 240 , in preparation for the subsequent removal of the first sacrificial layer 240 .
[0077] In this embodiment, the top of the remaining isolation structure 110 is lower than the bottom of the first sacrificial layer 240 , and the first sacrificial layer 240 not covered by the first protection layer 310 is completely exposed, which is beneficial to the subsequent removal of the first sacrificial layer 240 .
[0078] It should be noted that, in the present embodiment, in the step of removing a portion of the thickness of the isolation structure 110, the distance d4 between the top of the remaining isolation structure 110 and the bottom of the first sacrificial layer 240 should not be too large or too small. If the distance d4 between the top of the remaining isolation structure 110 and the bottom of the first sacrificial layer 240 is too large, the thickness of the remaining isolation structure 110 is too small, which may easily weaken the isolation effect of the remaining isolation structure 110; if the distance d4 between the top of the remaining isolation structure 110 and the bottom of the first sacrificial layer 240 is too small, it may easily lead to incomplete exposure of the side wall of the first sacrificial layer 240 by the isolation structure 110, thereby affecting the subsequent removal of the first sacrificial layer 240. For this reason, in the present embodiment, in the step of removing a portion of the thickness of the isolation structure 110, the distance d4 between the top of the remaining isolation structure 110 and the bottom of the first sacrificial layer 240 is 1nm to 20nm.
[0079] Combined with reference Figures 7 to 9 , Figure 8 for Figure 7 Cross-sectional view along AA direction, Fig. 9 for Figure 7In the cross-sectional view along the BB direction, a dummy gate structure 400 is formed on the substrate across the stacked structure 200 and the first sacrificial layer 240 . The dummy gate structure 400 covers part of the sidewalls and part of the top of the first protection layer 310 of the stacked structure 200 , and part of the sidewalls of the first sacrificial layer 240 .
[0080] The dummy gate structure 400 is used to occupy a space for the subsequent formation of a gate structure.
[0081] Specifically, the dummy gate structure 400 is a stacked structure, including a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) covering the dummy gate oxide layer.
[0082] As an example, the material of the dummy gate oxide layer is silicon oxide, and the material of the dummy gate layer is polysilicon.
[0083] Combined with reference Figures 10 to 12 , Fig.10 for Figure 8 The corresponding cross-sectional view, Fig.11 for Fig. 9 The corresponding cross-sectional view, Fig.12 for Figure 7 In the cross-sectional view along the CC direction, after the dummy gate structure 400 is formed, the first sacrificial layer 240 is removed to form a trench 250 penetrating the bottom of the stacked structure 200.
[0084] The groove 250 is used to provide a spatial position for the subsequent formation of an isolation layer. The groove 250 runs through the bottom of the stacked structure 200, and the subsequently formed isolation layer isolates the entire stacked structure 200 from the substrate, so that there is an isolation layer between the channel layer 230 and the substrate, and between the source and drain doping layers and the substrate.
[0085] In this embodiment, in the step of removing the first sacrificial layer 240 , the first protective layer 310 protects the top and sidewalls of the stacked structure 200 , and the second protective layer 320 protects the bottom of the stacked structure 200 , so that the stacked structure 200 is less damaged.
[0086] Accordingly, in this embodiment, in the step of removing the first sacrificial layer 240 , the second protection layer 320 at the bottom of the stacked structure 200 is exposed.
[0087] It should be noted that in the step of removing the first sacrificial layer 240 , the etching selection of the first sacrificial layer 240 and the second protective layer 320 is relatively large, so the second protective layer 320 can protect the stacked structure 200 , but the removed part of the second protective layer 320 is still damaged during the removal process.
[0088] It should be noted that if Fig.11 As shown, the stacked structure 200 is supported by the dummy gate structure 400, so that after the first sacrificial layer 240 is removed, the stacked structure 200 is suspended above the substrate.
[0089] In this embodiment, a wet etching process is used to remove the first sacrificial layer 240 .
[0090] The wet etching process is beneficial for completely removing the first sacrificial layer 240 . The wet etching process is also easy to achieve a larger etching selectivity ratio, so that in the process of removing the first sacrificial layer 240 , damage to the first protective layer 310 and the second protective layer 320 is reduced, thereby reducing damage to the stacked structure 200 .
[0091] In this embodiment, the etching solution of the wet etching process includes a hydrochloric acid solution.
[0092] The hydrochloric acid solution has good isotropic properties, which is conducive to the clean removal of the first sacrificial layer 240 , and the hydrochloric acid solution has a good etching selectivity ratio for silicon germanium and silicon, which is conducive to reducing damage to the first protective layer 310 and the second protective layer 320 during the removal of the first sacrificial layer 240 .
[0093] It should be noted that, in the present embodiment, in the step of removing the first sacrificial layer 240, the etching selectivity of the first sacrificial layer 240 and the second sacrificial layer 220 should not be too small. If the etching selectivity of the first sacrificial layer 240 and the second sacrificial layer 220 is too small, the second sacrificial layer 220 is easily damaged in the process of removing the first sacrificial layer 240, thereby affecting the subsequent formation of the inner sidewall, or, in the process of removing the first sacrificial layer 240, too much of the second sacrificial layer 220 is removed, or even the second sacrificial layer 220 is removed together, resulting in the subsequent width of the inner sidewall being too large, which correspondingly affects the formation of the gate structure between the adjacent channel layers 230 in the longitudinal direction, thereby affecting the performance of the semiconductor structure. For this reason, in the present embodiment, in the step of removing the first sacrificial layer 240, the etching selectivity of the first sacrificial layer 240 and the second sacrificial layer 220 is greater than 2.
[0094] It should also be noted that, in the present embodiment, in the step of removing the first sacrificial layer 240, the etching selectivity ratio between the first sacrificial layer 240 and the first protective layer 310 should not be too small. If the etching selectivity ratio between the first sacrificial layer 240 and the first protective layer 310 is too small, the first protective layer 310 is easily damaged during the process of removing the first sacrificial layer 240, affecting the protective effect of the first protective layer 310, thereby easily causing damage to the stacked structure 200. For this reason, in the present embodiment, in the step of removing the first sacrificial layer 240, the etching selectivity ratio between the first sacrificial layer 240 and the first protective layer 310 is greater than 5.
[0095] Combined with reference Figures 13 to 15 , Fig.13 for Fig.10 The corresponding cross-sectional view, Fig.14 for Fig.11The corresponding cross-sectional view, Fig.15 for Fig.12 Corresponding to the cross-sectional view, an isolation layer 260 is formed in the trench 250 .
[0096] The isolation layer 260 is used to isolate the gate structure from the substrate, and the source-drain doping layer from the substrate.
[0097] In this embodiment, after the second sacrificial layer 220 is subsequently removed to form a gate structure, the gate structure is formed on the isolation layer 260. The isolation layer 260 effectively isolates the contact between the gate structure and the substrate, thereby reducing the probability of leakage current between the gate structure and the substrate. At the same time, when the channel layer 230 is turned on, the parasitic capacitance of the substrate is reduced or avoided to increase due to the opening of the substrate.
[0098] In this embodiment, the material of the isolation layer 260 includes a dielectric material. The dielectric material can isolate the gate structure and the substrate. Moreover, the dielectric material has high process compatibility, thereby reducing the impact of the isolation layer 260 on the process.
[0099] In this embodiment, the material of the isolation layer 260 includes SiN, SiON, SiOCN, SiOC or SiOCH. The k value of SiN, SiON, SiOCN, SiOC or SiOCH is smaller, which is more conducive to better isolating the gate structure and the substrate, thereby reducing the parasitic capacitance between the gate structure and the substrate.
[0100] In this embodiment, after removing the first sacrificial layer 240 and before subsequently forming source and drain doping layers on the isolation layer 260 on both sides of the dummy gate structure 400 , the forming method further includes: forming a gate spacer 410 covering the sidewalls of the dummy gate structure 400 .
[0101] The gate spacer 410 is used to subsequently protect the sidewall of the gate structure.
[0102] The gate spacer 410 may be a single-layer structure or a stacked structure, and the material of the gate spacer 410 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In the present embodiment, the gate spacer 410 is a single-layer structure, and the material of the gate spacer 410 is silicon nitride.
[0103] In this embodiment, the gate spacer 410 and the isolation layer 260 in the trench 250 are formed in the same step.
[0104] In this embodiment, the gate sidewall 410 and the isolation layer 260 are formed in the trench 250 in the same step, which improves the process compatibility of forming the isolation layer 260 and the process efficiency, and is beneficial to improving the working performance of the semiconductor structure.
[0105] In this embodiment, the step of forming an isolation layer 260 in the groove 250 includes: forming an isolation material layer that fills the groove 250 and covers the side wall of the dummy gate structure 400, wherein the isolation material layer located in the groove 250 is retained as the isolation layer 260, and the isolation material layer covering the side wall of the dummy gate structure 400 is retained as the gate sidewall 410.
[0106] In this embodiment, in the step of forming the isolation material layer, the isolation material layer is formed by an atomic layer deposition process.
[0107] The isolation material layer formed by the atomic layer deposition process has good thickness uniformity and good step coverage, so that the isolation material layer can well cover the sidewalls and top of the dummy gate structure 400 and the sidewalls of the stacked structure 200 while filling the trench 250 .
[0108] Combined with reference Fig.16 and Fig.17 , Fig.16 for Fig.14 The corresponding cross-sectional view, Fig.17 for Fig.15 In the corresponding cross-sectional view, source-drain doped layers 500 are formed on the isolation layer 260 on both sides of the dummy gate structure 400 , and the source-drain doped layers 500 are in contact with the channel stack 210 below the dummy gate structure 400 .
[0109] The source-drain doped layer 500 is used as a source region or a drain region of a transistor.
[0110] The doping type of the source-drain doping layer 500 is the same as the channel conductivity type of the corresponding transistor. Specifically, when the substrate is used to form an NMOS transistor, the doped ions in the source-drain doping layer 500 are N-type ions, and the N-type ions include P ions, As ions or Sb ions; when the substrate is used to form a PMOS transistor, the doped ions in the source-drain doping layer 500 are P-type ions, and the P-type ions include B ions, Ga ions or In ions.
[0111] In this embodiment, an isolation layer 260 is formed between the source-drain doped layer 500 and the substrate, which is beneficial to reducing leakage between the source-drain doped layer 500 and, at the same time, reducing the parasitic capacitance between the source-drain doped layer 500 and the substrate.
[0112] In this embodiment, the step of forming a source-drain doping layer 500 on the isolation layer 260 on both sides of the dummy gate structure 400 includes: removing the stacked structure 200 on both sides of the dummy gate structure 400 and the first protective layer 310 covering the stacked structure 200 to expose the end of the remaining stacked structure 200 below the dummy gate structure 400.
[0113] The stacked structure 200 on both sides of the dummy gate structure 400 and the first protection layer 310 covering the stacked structure 200 are removed to expose the remaining end of the stacked structure 200 below the dummy gate structure 400 in preparation for forming the source-drain doped layer 500 .
[0114] In this embodiment, a dry etching process is used to remove the stacked structure 200 on both sides of the dummy gate structure 400 and the first protection layer 310 covering the stacked structure 200 .
[0115] The dry etching process is an anisotropic dry etching process. Therefore, by selecting the dry etching process, it is beneficial to reduce damage to the substrate. At the same time, dry etching is more directional, which is beneficial to improve the end morphology quality and dimensional accuracy of the remaining stacked structure 200 under the pseudo gate structure 400.
[0116] In the present embodiment, after removing the stacked structure 200 on both sides of the dummy gate structure 400 and the first protective layer 310 covering the stacked structure 200, before forming the source-drain doped layer 500 in contact with the end of the remaining stacked structure 200, the formation method also includes: removing a portion of the width of the second sacrificial layer 220 in a direction perpendicular to the side wall of the dummy gate structure 400 to form a groove (not shown); forming an inner side wall (not shown) in the groove; in the step of forming the source-drain doped layer 500 in contact with the end of the remaining stacked structure 200, the source-drain doped layer 500 is isolated from the second sacrificial layer 220 by the inner side wall.
[0117] The inner sidewall serves to isolate the gate structure and the source-drain doped layer 500 to be formed subsequently, so as to reduce the parasitic capacitance between the gate structure and the source-drain doped layer 500 .
[0118] In this embodiment, the material of the inner sidewall is an insulating material. As an example, in this embodiment, the material of the inner sidewall includes silicon oxide.
[0119] In this embodiment, a source-drain doped layer 500 is formed to contact the end of the remaining stacked structure 200 .
[0120] The source-drain doped layer 500 is epitaxially grown with the channel layer 230 as the epitaxial growth basis. Therefore, in the step of forming the source-drain doped layer 500 in this embodiment, the source-drain doped layer 500 is in contact with the inner sidewall.
[0121] Combined with reference Fig.18 and Fig.19 , Fig.18 for Fig.16 The corresponding cross-sectional view, Fig.19 for Fig.17 Corresponding to the cross-sectional view, after the source-drain doping layer is formed, the forming method further includes: forming an interlayer dielectric layer 600 covering the sidewalls of the dummy gate structure 400 and the source-drain doping layer 500 , wherein the interlayer dielectric layer 600 exposes the top of the dummy gate structure 400 .
[0122] The interlayer dielectric layer 600 is used to isolate adjacent devices. The interlayer dielectric layer 600 exposes the top of the dummy gate structure 400 to prepare for removing the dummy gate structure 400. The interlayer dielectric layer 600 is also used to provide a process basis for the subsequent formation of a gate structure.
[0123] The material of the interlayer dielectric layer 600 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.
[0124] In this embodiment, the dummy gate structure 400 is removed, and a gate opening 420 is formed in the interlayer dielectric layer 600 . The gate opening 420 exposes the first protection layer 310 .
[0125] The gate opening 420 provides a space for the subsequent formation of a gate structure and prepares for removing the first protection layer 310 .
[0126] refer to Fig. 20 , Fig. 20 for Fig.18 In the corresponding cross-sectional view, the first protection layer 310 is removed to expose the stacked structure 200 .
[0127] The first protection layer 310 is removed to expose the stacked structure 200 , and the second sacrificial layer 220 is correspondingly exposed, in preparation for removing the second sacrificial layer 220 .
[0128] In this embodiment, after removing the first protection layer 310 , the second sacrificial layer 220 is removed through the gate opening 420 .
[0129] The second sacrificial layer 220 is removed through the gate opening 420 to expose various surfaces of the channel layer 230 , so that the subsequently formed gate structure surrounds and covers the channel layer 230 .
[0130] Combined with reference Fig.21 and Fig. 22 , Fig.21 for Fig. 20 The corresponding cross-sectional view, Fig. 22 for Fig.19 Corresponding to the cross-sectional view, after removing the second sacrificial layer 220, a gate structure 700 is formed in the gate opening 420, and the gate structure 700 includes a gate dielectric layer surrounding the channel layer 230 along the extension direction of the gate structure 700, and a gate electrode layer located on the gate dielectric layer, and the bottom of the gate structure 700 and the substrate are isolated by the isolation layer 260.
[0131] The gate structure 700 is used to control the opening or closing of the channel of the transistor.
[0132] The gate structure 700 covers the channel layer 230 , so the top, bottom and sidewall of the channel layer 230 can all serve as channels, increasing the area of the channel layer 230 used as a channel, thereby increasing the operating current of the semiconductor structure.
[0133] The gate dielectric layer is used to isolate the gate electrode layer from the channel layer 230 , and the gate electrode layer from the substrate.
[0134] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Among them, the high-k dielectric material refers to a dielectric material whose relative dielectric constant is greater than the relative dielectric constant of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc.
[0135] It should be noted that the gate dielectric layer may further include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the channel layer 230. Specifically, the material of the gate oxide layer may be silicon oxide.
[0136] In this embodiment, the gate structure 700 is a metal gate structure, and therefore the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.
[0137] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer, wherein the work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to lead out the electrical properties of the metal gate structure.
[0138] In some other embodiments, the gate electrode layer may also only include a work function layer.
[0139] In other embodiments, according to process requirements, the gate structure may also be a polysilicon gate structure.
[0140] Specifically, refer to Fig.21 The isolation layer 260 effectively isolates the contact between the gate structure 700 and the substrate, thereby reducing the probability of leakage current between the gate structure 700 and the substrate. At the same time, when the channel layer 230 is turned on, it reduces or avoids the situation where the parasitic capacitance of the substrate increases due to being turned on.
[0141] refer to Fig. 22The isolation layer 260 effectively isolates the source-drain doped layer 500 from contact with the substrate, which is beneficial to reducing leakage between the source-drain doped layer 500 and, at the same time, reducing the parasitic capacitance between the source-drain doped layer 500 and the substrate.
[0142] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, a first sacrificial layer formed on the substrate, a stacked structure formed on the first sacrificial layer, the stacked structure comprising one or more stacked channel stacks, the channel stack comprising a second sacrificial layer and a channel layer located on the second sacrificial layer, wherein the etching resistance of the second sacrificial layer is greater than the etching resistance of the first sacrificial layer; forming a first protective layer covering the sidewalls and the top of the stacked structure; forming a dummy gate structure across the stacked structure and the first sacrificial layer on the substrate, wherein the dummy gate structure covers a portion of the sidewalls and a portion of the top of the first protection layer of the stacked structure, and a portion of the sidewalls of the first sacrificial layer; After forming the dummy gate structure, removing the first sacrificial layer to form a groove penetrating the bottom of the stacked structure; forming an isolation layer in the trench; A source-drain doping layer is formed on the isolation layer at both sides of the dummy gate structure, and the source-drain doping layer is in contact with the channel stack under the dummy gate structure.
2. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing the substrate, a second protective layer is formed between the first sacrificial layer and the stacked structure; In the step of removing the first sacrificial layer, the second protective layer at the bottom of the stacked structure is exposed.
3. The method for forming a semiconductor structure according to claim 2, wherein: In the step of providing the substrate, the thickness of the second protective layer is less than or equal to 10 nm.
4. The method for forming a semiconductor structure according to claim 2, wherein: The material of the second protection layer includes silicon.
5. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing the substrate, the substrate comprises a substrate and a bottom fin protruding from the substrate, and the first sacrificial layer is located on the bottom fin; Before forming a first protection layer covering the sidewalls and the top of the stacked structure, the forming method further comprises: forming an isolation structure covering the sidewalls of the bottom fin on the substrate, wherein the top of the isolation structure is lower than the bottom of the stacked structure and higher than the bottom of the first sacrificial layer; After forming a first protection layer covering the sidewalls and top of the stacked structure and before forming the dummy gate structure, the method further includes: removing a portion of the thickness of the isolation structure, with the top of the remaining isolation structure being lower than the bottom of the first sacrificial layer.
6. The method for forming a semiconductor structure according to claim 5, wherein: In the step of forming an isolation structure covering the sidewall of the bottom fin on the substrate, a distance between the top of the isolation structure and the bottom of the stacked structure is 1 nm to 10 nm.
7. The method for forming a semiconductor structure according to claim 5, wherein: In the step of removing a portion of the thickness of the isolation structure, the distance between the top of the remaining isolation structure and the bottom of the first sacrificial layer is 1 nm to 20 nm.
8. The method for forming a semiconductor structure according to claim 1, wherein: After removing the first sacrificial layer and before forming source-drain doping layers on the isolation layer at both sides of the dummy gate structure, the forming method further includes: forming a gate sidewall covering the sidewall of the dummy gate structure.
9. The method for forming a semiconductor structure according to claim 8, wherein: The gate spacer and the isolation layer in the trench are formed in the same step.
10. The method for forming a semiconductor structure according to claim 9, wherein: The step of forming an isolation layer in the trench includes: forming an isolation material layer filling the trench and covering the sidewalls of the pseudo gate structure, wherein the isolation material layer located in the trench is retained as the isolation layer, and the isolation material layer covering the sidewalls of the pseudo gate structure is retained as the gate sidewall.
11. The method for forming a semiconductor structure according to claim 10, wherein: In the step of forming the isolation material layer, the isolation material layer is formed by an atomic layer deposition process.
12. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a source-drain doping layer on the isolation layer on both sides of the dummy gate structure comprises: removing the stacked structure on both sides of the dummy gate structure and the first protection layer covering the stacked structure to expose the end of the remaining stacked structure under the dummy gate structure; A source-drain doped layer is formed to contact the remaining end of the stacked structure.
13. The method for forming a semiconductor structure according to claim 12, wherein: After removing the stacked structures on both sides of the dummy gate structure and the first protection layer covering the stacked structures, and before forming the source-drain doped layer in contact with the remaining end of the stacked structure, the forming method further comprises: removing a portion of the width of the second sacrificial layer in a direction perpendicular to the sidewall of the dummy gate structure to form a groove; forming an inner side wall in the groove; In the step of forming a source-drain doped layer in contact with the remaining end of the stacked structure, the source-drain doped layer is isolated from the second sacrificial layer by the inner sidewall.
14. The method for forming a semiconductor structure according to claim 1, wherein: After forming the source-drain doping layer, the forming method further comprises: forming an interlayer dielectric layer covering the sidewalls of the dummy gate structure and the source-drain doping layer, wherein the interlayer dielectric layer exposes the top of the dummy gate structure; removing the dummy gate structure, forming a gate opening in the interlayer dielectric layer, wherein the gate opening exposes the first protection layer; removing the first protective layer to expose the stacked structure; After removing the first protective layer, removing the second sacrificial layer through the gate opening; After removing the second sacrificial layer, a gate structure is formed in the gate opening, the gate structure comprising a gate dielectric layer surrounding the channel layer along an extension direction of the gate structure, and a gate electrode layer located on the gate dielectric layer, and the bottom of the gate structure and the substrate are isolated by the isolation layer.
15. The method for forming a semiconductor structure according to claim 1, wherein: In the step of removing the first sacrificial layer, an etching selectivity ratio between the first sacrificial layer and the second sacrificial layer is greater than 2, and an etching selectivity ratio between the first sacrificial layer and the first protective layer is greater than 5.
16. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing the substrate, the material of the first sacrificial layer includes silicon germanium, the material of the second sacrificial layer includes silicon germanium, and the material of the channel layer includes silicon, wherein the molar concentration of germanium in the first sacrificial layer is greater than the molar concentration of germanium in the second sacrificial layer.
17. The method for forming a semiconductor structure according to claim 16, wherein: The molar concentration of germanium in the first sacrificial layer is 15% to 80%, and the molar concentration of germanium in the second sacrificial layer is 5% to 50%.
18. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming a first protection layer covering the sidewalls and the top of the stacked structure, the material of the first protection layer includes silicon.
19. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming a first protective layer covering the sidewalls and the top of the stacked structure, the thickness of the first protective layer is 1 nm to 4 nm.
20. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing the substrate, the thickness of the first sacrificial layer is 3 nm to 30 nm.