Composite substrate and preparation method thereof, semiconductor structure and electronic equipment

Abstract

The invention provides a composite substrate and a preparation method thereof, a semiconductor structure and electronic equipment, relates to the technical field of semiconductors, and aims to reduce the preparation cost of the composite substrate. The preparation method of the composite substrate comprises the following steps: forming a mother board substrate, wherein the mother board substrate comprises a mother board and an epitaxial layer; a defect layer is formed in the epitaxial layer. Along the thickness direction of the mother board, the defect layer divides the epitaxial layer into a first sub-layer and a second sub-layer. And permanently bonding the substrate with the first sub-layer. The first sub-layer is separated from the second sub-layer. The substrate and the first sub-layer form a composite substrate. And circularly executing the step of forming the defect layer in the epitaxial layer to separate the first sub-layer from the second sub-layer for N times in the direction of the plane where the defect layer is located, and obtaining a composite substrate after each time of circular execution. And in the process of forming the defect layer in the epitaxial layer in each cycle, using the second sub-layer in the composite mother board formed in the previous cycle as the epitaxial layer in the current cycle process. The composite substrate is applied to a semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a composite substrate and a preparation method thereof, a semiconductor structure, and an electronic device. Background Art

[0002] Silicon carbide (SiC), as a representative material of the third-generation semiconductors, combines many excellent properties such as wide band gap (2.4eV~3.2eV), high physical strength, high thermal conductivity, high corrosion resistance, high melting point, wide light transmission window (0.37μm~5.6μm) and wide-area defect luminescence window (visible light to mid-infrared). It is an ideal material for high-voltage power devices. Summary of the invention

[0003] Embodiments of the present disclosure provide a composite substrate and a method for preparing the same, a semiconductor structure, and an electronic device, aiming to reduce the preparation cost of the composite substrate.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] On the one hand, a method for preparing a composite substrate is provided, the method comprising: forming a motherboard substrate, the motherboard substrate comprising a motherboard and an epitaxial layer located on one side of the motherboard. Forming a defective layer in the epitaxial layer. Along the thickness direction of the motherboard, the defective layer divides the epitaxial layer into a first sublayer away from the motherboard side and a second sublayer close to the motherboard side. Permanently bonding the substrate to the first sublayer. Separating the first sublayer from the second sublayer along the direction of the plane where the defective layer is located. The substrate and the first sublayer form a composite substrate. The motherboard and the second sublayer form a composite motherboard. The steps of forming a defective layer in the epitaxial layer, permanently bonding the substrate to the first sublayer, and separating the first sublayer from the second sublayer along the direction of the plane where the defective layer is located are performed N times in a loop, and a composite substrate and a composite motherboard are obtained after each loop is performed. In forming the defective layer in the epitaxial layer in each loop, the second sublayer in the composite motherboard formed in the previous loop is used as the epitaxial layer in the current loop process. N is greater than or equal to 1, and N is a positive integer.

[0006] In the embodiment of the present disclosure, a defect layer is formed in the epitaxial layer of the mother substrate, the epitaxial layer is divided into a first sublayer and a second sublayer by using the defect layer, the first sublayer is bonded to the substrate, and then the first sublayer is separated from the second sublayer to form a composite substrate including the substrate and the first sublayer, and a composite mother substrate including the mother substrate and the second sublayer, and then the above steps are cyclically performed on the composite mother substrate, so that multiple composite substrates can be prepared using the same mother substrate, avoiding the need to select a high-quality substrate for each composite substrate and the need to obtain an epitaxial layer through epitaxial growth, thereby reducing the preparation cost of the composite substrate and the preparation cost of the semiconductor structure. Moreover, the epitaxial structures on multiple composite substrates (the epitaxial structure here refers to the first sublayer) are taken from the epitaxial layer grown on the same mother substrate, so that the quality index of each first sublayer in the prepared multiple composite substrates can be the same or similar, thereby ensuring the stability of the quality of the composite substrate.

[0007] In some embodiments, forming a defect layer in the epitaxial layer includes: implanting target ions into the epitaxial layer from a side of the epitaxial layer away from a mother substrate to form the defect layer.

[0008] In some embodiments, the target ions are implanted at a depth ranging from 0.1 μm to 5 μm.

[0009] In some embodiments, the target ions include at least one of hydrogen ions and helium ions.

[0010] In some embodiments, forming a defect layer in the epitaxial layer includes: irradiating the epitaxial layer with a laser from a side of the epitaxial layer away from the mother substrate to form the defect layer.

[0011] In some embodiments, the laser irradiation depth is less than or equal to 200 μm.

[0012] In some embodiments, forming a mother substrate includes: providing a mother substrate, wherein the mother substrate has a single crystal crystal form, and homoepitaxially growing an epitaxial layer on the mother substrate.

[0013] In some embodiments, the dislocation density of the master substrate is less than or equal to a first preset value.

[0014] In some embodiments, the material of the motherboard includes: silicon carbide, diamond. The first preset value is 100 pieces / cm 2 .

[0015] In some embodiments, the material of the motherboard includes: gallium oxide or Al x Ga 1-x N. Where 0≤x≤1.

[0016] In some embodiments, the process of epitaxially growing the epitaxial layer on the mother substrate includes: a chemical vapor deposition process, a molecular beam epitaxy process, or a liquid phase epitaxy process.

[0017] In some embodiments, the epitaxial layer has a thickness ranging from 3 μm to 1000 μm.

[0018] In some embodiments, before the substrate is permanently bonded to the first sub-layer, the preparation method further includes: polishing the surface of the first sub-layer away from the motherboard. After separating the first sub-layer from the second sub-layer along the direction of the plane where the defective layer is located, the preparation method further includes: annealing and polishing the first sub-layer. Epitaxially growing an epitaxial sub-layer on the first sub-layer.

[0019] In some embodiments, after separating the first sub-layer from the second sub-layer along the direction of the plane where the defective layer is located, the preparation method further includes: annealing and polishing the second sub-layer.

[0020] On the other hand, a composite substrate is provided. The composite substrate is a composite substrate formed by the preparation method described in any of the above embodiments. The composite substrate includes a substrate and a first sublayer located on one side of the substrate.

[0021] It can be understood that the beneficial effects that can be achieved by the composite substrate provided by the above embodiments of the present disclosure can refer to the beneficial effects of the method for preparing the composite substrate described above, which will not be described in detail here.

[0022] In some embodiments, the composite substrate further includes an epitaxial sublayer located on a side of the first sublayer away from the substrate; the first sublayer is a P-type epitaxial structure, and the epitaxial sublayer is a P-type epitaxial structure.

[0023] On the other hand, a composite substrate is provided, including a first sublayer and an epitaxial sublayer located on one side of the first sublayer; the first sublayer is a P-type epitaxial structure, and the epitaxial sublayer is a P-type epitaxial structure.

[0024] On the other hand, a semiconductor structure is provided, comprising a heterojunction and a composite substrate or a composite base as described in the above embodiment and located on one side of the heterojunction.

[0025] It can be understood that the beneficial effects that can be achieved by the semiconductor device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the method for preparing the composite substrate described above, which will not be described in detail here.

[0026] On the other hand, an electronic device is provided, comprising the semiconductor structure and a circuit board as described in the above embodiment, wherein the circuit board is connected to the semiconductor structure.

[0027] It can be understood that the beneficial effects that can be achieved by the electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the method for preparing the composite substrate described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for use in some embodiments of the present disclosure are briefly introduced below.

[0029] Figure 1 is a structural diagram of an electronic device according to some embodiments of the present disclosure;

[0030] Figure 2 is a structural diagram of a semiconductor structure according to some embodiments of the present disclosure;

[0031] Figure 3 is a flow chart of a method for preparing a composite substrate according to some embodiments of the present disclosure;

[0032] Figures 4 to 9 is a structural diagram of a composite substrate in different preparation processes according to some embodiments of the present disclosure;

[0033] Fig.10 is a structural diagram of a composite substrate according to some embodiments of the present disclosure;

[0034] Fig.11 is a structural diagram of another composite substrate according to some embodiments of the present disclosure;

[0035] Fig.12 A structural diagram of a composite base substrate according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0036] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0037] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0038] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0039] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0040] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0041] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0042] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0043] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0044] In the context of this disclosure, the meanings of “on,” “above,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “above” or “over” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0045] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0046] The embodiments of the present disclosure provide an electronic device. The electronic device may include a mobile phone, a tablet computer (pad), a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR) device, and the like. The embodiments of the present disclosure do not impose any special restrictions on the specific form of the above electronic devices.

[0047] In some examples, such as Figure 1 As shown, the electronic device 1000 includes a semiconductor structure 100 and a circuit board 200 , and the circuit board 200 is connected to the semiconductor structure 100 .

[0048] Exemplarily, the semiconductor structure 100 may be a power device, for example, the power device may be a high electron mobility transistor (HEMT) device.

[0049] For example, the circuit board 200 may be a printed circuit board (PCB).

[0050] In some examples, such as Figure 2 As shown, the semiconductor structure 100 includes a heterojunction 60 and a composite substrate 40 or a composite base 70 located on one side of the heterojunction 60 .

[0051] For example, the heterojunction 60 may be composed of a channel layer and a barrier layer. A two-dimensional electron gas is generated at the interface between the channel layer and the barrier layer in the heterojunction due to a polarization effect, and the two-dimensional electron gas can be used to conduct electrons efficiently.

[0052] Taking the semiconductor structure 100 as a power device as an example, the semiconductor structure 100 further includes: a source S, a drain D, and a gate G. When the gate G does not receive a voltage signal, that is, when there is no bias voltage, the two-dimensional electron gas is allowed to pass through to achieve conduction between the source S and the drain D, and the semiconductor structure 100 is in an on state. When the gate G receives a voltage signal, that is, when a bias voltage is applied, the two-dimensional electron gas is in a pinch-off state to achieve cutoff between the source S and the drain D, and the semiconductor structure 100 is in an off state.

[0053] In the field of semiconductor technology, modern power electronic systems have an increasing demand for power devices with higher efficiency, smaller size and higher performance. However, due to the limitations of the material itself, such as low critical breakdown electric field strength, thermal conductivity and electron mobility, silicon-based power devices are difficult to operate under high voltage, high frequency, high temperature, extreme environment and other working conditions, and it is difficult to ensure working efficiency and reliability. Therefore, wide bandgap semiconductor materials such as silicon carbide can be used to prepare power devices, thereby overcoming the limitations of silicon-based materials and forming a new generation of high-performance power devices.

[0054] Exemplarily, the above-mentioned power device generally includes a composite substrate, which can be prepared using wide bandgap semiconductor materials such as silicon carbide. In one possible implementation, the composite substrate includes a substrate and an epitaxial layer formed by epitaxial growth on the substrate. Among them, the cost of the epitaxial growth process of the substrate is relatively high, so that the epitaxial growth process of the substrate accounts for about 40% to 70% of the entire preparation cost of the semiconductor structure. Therefore, the cost of preparing the composite substrate using the above-mentioned wide bandgap semiconductor material is extremely high, making the cost of the semiconductor structure extremely high.

[0055] Based on this, an embodiment of the present disclosure provides a method for preparing a composite substrate, such as Figure 3 As shown, the preparation method includes: A100~A500.

[0056] A100, such as Figure 4 (a) and Figure 4 As shown in (b), a mother substrate 10 is formed. The mother substrate 10 includes a mother substrate 11 and an epitaxial layer 12 located on one side of the mother substrate 11 .

[0057] For example, the epitaxial layer 12 is obtained by epitaxial growth on the mother substrate 11 .

[0058] Exemplarily, a mother substrate 11 with high quality indicators can be selected, thereby making the epitaxial layer 12 obtained by epitaxial growth have high quality indicators, few defects, and low dislocation density, which is conducive to forming a high-quality composite substrate 40 and semiconductor structure 100.

[0059] A200, such as Figure 4 (b) and Figure 4 As shown in (c), a defect layer 20 is formed in the epitaxial layer 12. Along the thickness direction of the mother board 11, the defect layer 20 divides the epitaxial layer 12 into a first sub-layer 13 away from the mother board 11 and a second sub-layer 14 close to the mother board 11.

[0060] For example, the defective layer 20 is in the form of a thin film (or a plane), and the thickness of the defective layer 20 is relatively small compared to the thickness of the epitaxial layer 12. The defective layer 20 is located inside the epitaxial layer 12, and the plane where the defective layer 20 is located is perpendicular to the thickness direction of the motherboard 11. The orthographic projection of the defective layer 20 on the motherboard 11, for example, coincides with the orthographic projection of the epitaxial layer 12 on the motherboard 11. The portion of the epitaxial layer 12 located on the side of the defective layer 20 away from the motherboard 11 constitutes the first sublayer 13, and the portion of the epitaxial layer 12 located on the side of the defective layer 20 close to the motherboard 11 constitutes the second sublayer 14.

[0061] For example, the thickness of the first sublayer 13 is less than the thickness of the second sublayer 14. For another example, the thickness of the first sublayer 13 is greater than or equal to the thickness of the second sublayer 14.

[0062] A300, such as Figure 5 As shown, the substrate 30 is permanently bonded to the first sublayer 13 .

[0063] For example, a low-temperature direct bonding process may be used to achieve permanent bonding between the substrate 30 and the first sub-layer 13 .

[0064] Permanent bonding means that the bonding between the substrate 30 and the first sub-layer 13 cannot be easily or even be separated.

[0065] For example, the substrate 30 and the first sublayer 13 are lattice-matched crystals. The substrate 30 can provide mechanical support for the first sublayer 13, and can also conduct heat in the first sublayer 13. The substrate 30 can be a conductor, and the substrate 30 can also have chemical corrosion resistance and light transmission properties.

[0066] In some examples, before permanently bonding the substrate 30 to the first sub-layer 13, the substrate 30 may be polished or otherwise treated so that the surface roughness of the substrate 30 is in the range of 0.05 nm to 0.5 nm, thereby improving the bonding strength between the substrate 30 and the first sub-layer 13 and facilitating good bonding between the substrate 30 and the first sub-layer 13.

[0067] For example, after the substrate 30 is polished or processed, the surface roughness of the substrate 30 may be 0.05 nm, 0.10 nm, 0.25 nm, 0.42 nm, or 0.5 nm.

[0068] The material of the substrate 30 can be selected and set according to the actual situation. The material of the substrate 30 can be the same as the material of the first sublayer 13, or it can be different. For example, in the case where the electrical performance requirements of the semiconductor structure are high, the material of the substrate 30 can be selected from polycrystalline silicon carbide materials with high resistance. For semiconductor structures that require low cost, the material of the substrate 30 can be selected from sapphire materials. For another example, the material of the substrate 30 can also be graphite, diamond, silicon carbide D-grade film, silicon nitride (Si3N4), gallium oxide or gallium aluminum nitride, etc.

[0069] The above-mentioned silicon carbide D-grade sheet means that the mass concentration of silicon carbide in the substrate is 90%.

[0070] The quality index of the substrate 30 may be lower than or equal to the quality index of the mother board 11. Thus, the preparation cost of the formed composite substrate may be reduced.

[0071] A400, such as Figure 5 , Figure 6 and Figure 8 As shown, the first sublayer 13 and the second sublayer 14 are separated along the plane where the defective layer 20 is located. The substrate 30 and the first sublayer 13 form a composite substrate 40. The motherboard 11 and the second sublayer 14 form a composite motherboard 50.

[0072] For example, a high temperature annealing process may be used to separate the first sub-layer 13 from the second sub-layer 14. Specifically, the annealing temperature may range from 700° C. to 2200° C., and the annealing time may range from 10 s to 10000 s.

[0073] Optionally, the annealing temperature may range from 700°C to 900°C, 700°C to 1300°C, 800°C to 1300°C, 1100°C to 2200°C, or 1800°C to 2200°C.

[0074] For example, the annealing temperature may be 700° C., 800° C., 900° C., 1100° C., 1200° C., 1300° C., 1800° C., or 2200° C. The annealing time may be 10 s, 60 s, 350 s, 5400 s, 9800 s, or 10000 s.

[0075] A500, such as Figure 4 Middle (c), Figure 5 , Figure 6 , Figure 8 and Fig. 9As shown, the steps of forming a defective layer 20 in the epitaxial layer 12, permanently bonding the substrate 30 to the first sublayer 13, and separating the first sublayer 13 from the second sublayer 14 along the plane where the defective layer 20 is located are performed cyclically N times, and a composite substrate 40 and a composite mother plate 50 are obtained after each cycle. In forming the defective layer 20 in the epitaxial layer 12 in each cycle, the second sublayer 14 in the composite mother plate 50 formed in the previous cycle is used as the epitaxial layer 12 in the current cycle. N is greater than or equal to 1, and N is a positive integer.

[0076] For example, the number N of times the above cycle is executed depends on the thickness of the epitaxial layer 12 and the thickness of the first sublayer 13. When the thickness of the epitaxial layer 12 is large and the thickness of the first sublayer 13 is small, the value of N is large.

[0077] For example, when N is 1, the above preparation method can prepare two composite substrates.

[0078] Thus, the epitaxial layer 12 on the same motherboard 11 can be used to prepare multiple composite substrates 40, thereby reducing the demand for high-quality motherboards 11 in the process of preparing the composite substrates 40 and reducing the preparation cost of the composite substrates 40. Moreover, the epitaxial structures on the multiple composite substrates (the epitaxial structure here refers to the first sublayer) are taken from the epitaxial layer grown on the same motherboard, so that the quality index of each first sublayer 13 in the prepared multiple composite substrates 40 can be the same or similar, so that the quality of each composite substrate 40 is the same, thereby ensuring the stability of the quality of the composite substrates 40.

[0079] For example, until the epitaxial layer 12 on the motherboard 11 is completely peeled off, the above step A500 is stopped. After the epitaxial layer 12 on the motherboard 11 is completely peeled off, the motherboard 11 can be reused, and the epitaxial layer can continue to be epitaxially grown on the motherboard 11, and the above steps A200 to A500 are repeated to prepare the composite substrate, thereby reducing the number of high-quality motherboards required, reducing the preparation cost of high-quality motherboards, and further reducing the preparation cost of the composite substrate.

[0080] In the embodiment of the present disclosure, a defect layer 20 is formed in the epitaxial layer 12 of the motherboard substrate 10, the epitaxial layer 12 is divided into a first sublayer 13 and a second sublayer 14 by using the defect layer 20, the first sublayer 13 is bonded to the substrate 30, and then the first sublayer 13 is separated from the second sublayer 14 to form a composite substrate 40 including the substrate 30 and the first sublayer 13, and a composite motherboard 50 including the motherboard 11 and the second sublayer 14, and then the above steps are cyclically performed on the composite motherboard 50, so that a plurality of composite substrates 40 can be prepared using the same motherboard substrate 10, avoiding the need to select a high-quality substrate for each composite substrate and avoiding the need to obtain an epitaxial layer through epitaxial growth, thereby reducing the preparation cost of the composite substrate 40 and reducing the preparation cost of the semiconductor structure. Furthermore, the epitaxial structures on the multiple composite substrates 40 (the epitaxial structures here refer to the first sublayers 13) are taken from the epitaxial layer 12 grown on the same motherboard 11, so that the quality indexes of the first sublayers 13 in the multiple composite substrates 40 prepared can be the same or similar, thereby ensuring the stability of the quality of the composite substrates 40. The stability of the quality of the multiple composite substrates 40 can also be ensured.

[0081] In some embodiments, the A100 forming the motherboard substrate 10 includes: A110 - A120 .

[0082] A110, such as Figure 4 As shown in (a), a motherboard 11 is provided, and the crystal form of the motherboard 11 is single crystal.

[0083] Exemplarily, taking the case where the material of the motherboard 11 is silicon carbide, the crystal form of the motherboard 11 may be 4H-SiC.

[0084] The motherboard 11 may be a P-type motherboard or an N-type motherboard.

[0085] By using a single crystal motherboard 11 , the epitaxially grown epitaxial layer 12 can also be a single crystal.

[0086] A120, such as Figure 4 As shown in (b) , an epitaxial layer 12 is epitaxially grown on a mother substrate 11 .

[0087] In some examples, homoepitaxial growth of the epitaxial layer 12 may be adopted, the epitaxial layer 12 and the mother board 11 are made of the same material, and the epitaxial layer 12 has a quality index equal to or substantially equal to that of the mother board 11. The quality index here may include dislocation density, defect density, inclusions, dislocation corrosion density, etc.

[0088] In other examples, heteroepitaxial growth of the epitaxial layer 12 may be adopted, the epitaxial layer 12 and the motherboard 11 are made of different materials, and the epitaxial layer 12 has the same or substantially the same quality index as the motherboard 11. For example, the motherboard 11 may be made of silicon carbide, and the epitaxial layer 12 may be made of gallium nitride.

[0089] For example, the motherboard 11 is an N-type motherboard, and the grown epitaxial layer 12 can be a P-type doped crystal or an N-type doped crystal.

[0090] Exemplarily, a mother substrate 11 with a higher quality index may be selected, for example, a mother substrate 11 with a low defect density and a low dislocation density may be selected, thereby ensuring that the quality of the grown epitaxial layer 12 is higher and that the quality of the prepared composite substrate 40 is higher.

[0091] In some examples, the dislocation density of the mother substrate 11 is less than or equal to a first preset value.

[0092] Thus, the dislocation density of the mother substrate 11 can be reduced, thereby increasing the quality of the mother substrate 11 and the quality of the formed epitaxial layer 12 and the composite substrate 40 , which is beneficial to improving the performance of the semiconductor structure 100 .

[0093] Exemplarily, the material of the motherboard 11 includes: silicon carbide or diamond. The first preset value is 100 pieces / cm 2 That is, silicon carbide or diamond is used as the material of the motherboard 11, and the dislocation density of the motherboard 11 is less than or equal to 100 / cm 2 .

[0094] For example, the dislocation density of the mother board 11 may be 100 / cm 2 , 95 pieces / cm 2 、84pcs / cm 2 , 75 pieces / cm 2 , 71 / cm 2 or 65 pieces / cm 2 .

[0095] Thus, it is possible to ensure that the quality of the formed epitaxial layer 12 is high, so that the dislocation density of the formed epitaxial layer 12 is small, and so that the quality of the formed composite substrate 40 is high.

[0096] In addition, when the material of the motherboard 11 is silicon carbide, the quality indicators of the motherboard 11 may include: microtube density is 0, thread-slip dislocation (TSD) is ≤ 100 / cm 2 , Basal plane dislocation (BPD) ≤ 100 / cm 2 , Etch Pileup Dislocation (TED) ≤ 1000 / cm 2 , Etch Pit Dislocation (EPD) ≤ 1000 / cm 2, stacking fault (SF) ≤ 0.2% area, inclusion ≤ 0.2% area, polymorphic region is not allowed (the polymorphic region here refers to the region where multiple crystal forms coexist), the thickness range of the motherboard is 10μm to 2000μm, and the diameter range is 1 inch to 12 inches.

[0097] When the material of the motherboard is diamond, the quality index of the motherboard may include: Full Width at half Maxima (FWHM) of diamond ≤ 2.0 cm -1 There are no obvious defects such as polycrystalline rings on the edge of the diamond appearance, and the thickness of the motherboard ranges from 10μm to 2000μm.

[0098] Exemplarily, the material of the motherboard 11 may also include: gallium oxide or Al x Ga 1-x N. Where 0≤x≤1.

[0099] For example, the material of the motherboard can be Ga2O3, AlN, GaN, Al 0.2 Ga 0.8 N、Al 0.3 Ga 0.7 N、Al 0.6 Ga 0.4 N or Al 0.5 Ga 0.5 N.

[0100] Illustratively, in the above A120 , before homoepitaxially growing the epitaxial layer 12 on the mother substrate 11 , the preparation method further includes: cleaning the mother substrate 11 .

[0101] The cleaning process can remove particles and interface dangling bonds on the motherboard 11. For example, after the cleaning process, all particles with a size of about 19 nm on the surface of the motherboard 11 are removed, or the density of particles with a size of about 19 nm remaining on the surface of the motherboard 11 is less than or equal to 10 / cm 2 .

[0102] In this way, the influence of particles or interface dangling bonds on the surface of the motherboard 11 on the quality of the subsequent epitaxially grown epitaxial layer 12 can be avoided or reduced, so that the quality index of the formed epitaxial layer 12 is higher, which is conducive to forming a higher quality composite substrate 40 and semiconductor structure 100.

[0103] There may be a variety of processes for epitaxially growing the epitaxial layer 12 on the motherboard 11 , which can be selected according to actual needs, and the embodiments of the present disclosure are not limited to this.

[0104] In some examples, the process of epitaxially growing the epitaxial layer 12 on the mother substrate 11 includes: Chemical Vapor Deposition (CVD), Molecular Beam Epitaxy (MBE), or Liquid Phase Epitaxy (LPE).

[0105] For example, the epitaxial layer 12 may be grown by using a chemical vapor deposition process.

[0106] Taking silicon carbide as the material of the motherboard as an example, specifically, the deposition of the epitaxial layer material can be carried out in a chemical vapor deposition reaction chamber. In the reaction process, silicon carbide, as a starting material or precursor material, plays a supporting role in the growth of the silicon carbide epitaxial layer, and the reaction gas includes at least a silicon source gas, a carbon source gas and a doping gas. Among them, the silicon source gas is at least one of silane, silicon tetrachloride, trichlorosilane and dichlorosilane; the carbon source gas is at least one of ethylene, propane, acetylene and carbon tetrachloride; the N-type doping gas is at least one of nitrogen and ammonia; the P-type doping gas is at least one of trimethylaluminum and borane; the carrier gas is hydrogen or argon.

[0107] Taking diamond as the material of the motherboard as an example, in the chemical vapor deposition reaction chamber, diamond is used as the starting material or precursor material to support the growth of the diamond epitaxial layer, and the reaction gas includes at least a carbon source gas and a doping gas. The carbon source gas is at least one of ethylene, propane, acetylene, and carbon tetrachloride; the N-type doping gas is at least one of nitrogen and ammonia; the P-type doping gas is at least one of trimethylaluminum and borane; and the carrier gas is hydrogen or argon.

[0108] For another example, the epitaxial layer 12 may be grown using a molecular beam epitaxy process.

[0109] Taking silicon carbide as the motherboard material as an example, specifically, the silicon carbide motherboard is heated to 300°C to 1000°C, and the system vacuum degree is set to ≤1×10 -11 Torr, evaporation sources include silicon source, carbon source and doping source. Doping source includes: aluminum (Al) source compound, nitrogen (N) plasma source, magnesium (Mg) source compound, etc.

[0110] Taking diamond as the motherboard material as an example, specifically, the diamond motherboard is heated to 300°C to 1000°C, and the system vacuum is set to ≤1×10 -11 Torr, evaporation sources include carbon sources and doping sources. Doping sources include: aluminum (Al) source compounds, nitrogen (N) plasma sources, magnesium (Mg) source compounds, etc.

[0111] For another example, the epitaxial layer 12 may be grown using a liquid phase epitaxial process.

[0112] Taking silicon carbide as the material of the motherboard as an example, specifically, a silicon-containing solvent is placed in a graphite crucible, the silicon-containing solvent is heated to melt, the carbon in the graphite crucible is dissolved into the silicon-containing solvent, the surface of the silicon carbide motherboard is contacted with the silicon-containing solvent solution, or the surface of the silicon carbide motherboard is immersed in the silicon-containing solvent solution, carbon will precipitate at the solid-liquid interface of the silicon carbide motherboard, and form a doped silicon carbide epitaxial layer with the silicon in the silicon-containing solvent. The doping concentration can be controlled by passing nitrogen and ammonia, or by adding metal elements such as Al to the solvent.

[0113] The epitaxial layer is prepared by the above process, so that the quality index of the epitaxial layer 12 is higher.

[0114] In some examples, the epitaxial layer 12 has a thickness ranging from 3 μm to 1000 μm.

[0115] Illustratively, the thickness of the epitaxial layer 12 may be in the range of 3 μm to 100 μm, 54 μm to 230 μm, 152 μm to 540 μm, 350 μm to 800 μm, or 700 μm to 1000 μm.

[0116] For example, the thickness of the epitaxial layer 12 may be 3 μm, 54 μm, 152 μm, 230 μm, 350 μm, 540 μm, 800 μm, or 1000 μm.

[0117] Thus, the epitaxial layer 12 can have a sufficiently large thickness, so that the epitaxial layer 12 can be separated multiple times (i.e., the above-mentioned A400 step), so that the mother substrate 10 can be recycled multiple times, and then multiple composite substrates 40 can be prepared, thereby reducing the preparation cost of the composite substrate 40 and the semiconductor structure 100.

[0118] For example, an epitaxial layer with a thickness of 100 μm can be separated 8 times (or 9 times) to form 8 (or 9) composite substrates, in which the thickness of the first sublayer is about 10 μm.

[0119] There are a variety of preparation methods for forming the defect layer 20 in the epitaxial layer 12 , which can be selected and set according to actual conditions, and the embodiments of the present disclosure are not limited to this.

[0120] In some embodiments, in the above A200 , forming the defect layer 20 in the epitaxial layer 12 includes: injecting target ions into the epitaxial layer 12 from a side of the epitaxial layer 12 away from the mother substrate 11 to form the defect layer 20 .

[0121] For example, the implantation depth of the target ions can be controlled by controlling the implantation energy.

[0122] Thereby, the formation of the defect layer 20 can be ensured.

[0123] In some examples, the target ions are implanted at a depth ranging from 0.1 μm to 5 μm.

[0124] For example, the implantation depth of the target ions may be 0.1 μm, 1.2 μm, 2.4 μm, 3.8 μm, or 5 μm.

[0125] It can be understood that the implantation depth of the target ions is substantially equal to the thickness of the first sub-layer 13 .

[0126] Exemplarily, the target ions include at least one of hydrogen ions and helium ions.

[0127] For example, the target ions may be hydrogen ions, helium ions, or both hydrogen ions and helium ions.

[0128] In some other embodiments, the above-mentioned A200 forms a defective layer 20 in the epitaxial layer 12 , including: irradiating the epitaxial layer 12 with laser from a side of the epitaxial layer 12 away from the mother substrate 11 to form the defective layer 20 .

[0129] Exemplarily, during the laser irradiation process, the wavelength range of the laser is 343 nm to 1064 nm, the laser pulse width range is 50 fs to 100000 fs (100 ps), and the laser energy range is 0.1 nJ to 10 mJ.

[0130] For example, the wavelength of the laser may be in the range of 343 nm to 523 nm, 523 nm to 754 nm, 754 nm to 889 nm, 754 nm to 1064 nm, or 889 nm to 1064 nm. Alternatively, the wavelength of the laser may be 343 nm, 523 nm, 754 nm, 889 nm, or 1064 nm.

[0131] For example, the laser pulse width may range from 50 fs to 1000 fs, 100 fs to 1000 fs, 1000 fs to 10000 fs, 500 fs to 100000 fs, or 50050 fs to 100000 fs. Alternatively, the laser pulse width may range from 50 fs, 100 fs, 500 fs, 1000 fs, 10000 fs, 50050 fs, or 100000 fs.

[0132] For example, the laser energy range may be 0.1nJ to 6nJ, 10nJ to 1000nJ, 100nJ to 5mJ, 1mJ to 10mJ or 7mJ to 10mJ. Alternatively, the laser energy may be 0.1nJ, 6nJ, 10nJ, 100nJ, 1000nJ, 1mJ, 5mJ, 7mJ or 10mJ.

[0133] By adjusting the wavelength, pulse width and laser energy of laser irradiation, the formation of the defect layer 20 can be ensured, so that the defect layer can divide the epitaxial layer 12 into the first sub-layer 13 and the second sub-layer 14 .

[0134] In some examples, the laser irradiation depth is less than or equal to 200 μm.

[0135] Exemplarily, the laser irradiation depth range may be less than or equal to 5 μm, less than or equal to 10 μm, less than or equal to 60 μm, less than or equal to 110 μm, etc. Optionally, the laser irradiation depth may be 5 μm, 10 μm, 60 μm, 110 μm or 200 μm.

[0136] It can be understood that the depth of laser irradiation is substantially equal to the thickness of the first sub-layer 13 .

[0137] The laser irradiation depth is within the above-mentioned range, which can ensure that the depth of the defect layer 20 formed in the epitaxial layer 12 has a larger adjustable range, so that the defect layer 20 can be located at different depths of the epitaxial layer, which is convenient for adjusting the thickness of the formed first sublayer 13, so that the thickness of the first sublayer 13 can be flexibly set, which is beneficial to reducing the difficulty of preparing the composite substrate 40 and the semiconductor structure 100.

[0138] Exemplarily, the laser may be a pulsed laser, for example, a laser generated by a solid-state laser or a fiber laser.

[0139] In some embodiments, before the above A300 , that is, before the substrate 30 is permanently bonded to the first sub-layer 13 , the preparation method further includes: polishing a surface of the first sub-layer 13 on a side away from the motherboard 11 .

[0140] Exemplarily, polishing can be performed by chemical mechanical polishing (CMP), electrochemical mechanical polishing (ECMP), plasma polishing (PAP), photoelectric chemical mechanical polishing (PECMP), magnetorheological polishing or other polishing processes.

[0141] For example, the surface roughness of the first sub-layer 13 after polishing is in the range of 0.05 nm to 0.5 nm.

[0142] For example, after the first sublayer 13 is polished, a cleaning process may be performed. After the cleaning process, all particles with a size of 19 nm on the surface of the first sublayer 13 are removed, and the density of particles with a size of less than 19 nm on the surface of the first sublayer 13 is less than or equal to 10 particles / cm 2 .

[0143] Thus, the surface roughness of the first sublayer 13 away from the motherboard 11 can be reduced and the surface can be cleaner, so that the bonding strength between the substrate 30 and the first sublayer 13 can be greater, thereby facilitating permanent bonding between the substrate 30 and the first sublayer 13.

[0144] Illustratively, after the above A400, that is, after the first sub-layer 13 and the second sub-layer 14 are separated along the direction of the plane where the defective layer 20 is located, the preparation method further includes: A410 to A420.

[0145] A410, performing annealing and polishing treatment on the first sub-layer 13.

[0146] For example, the composite substrate 40 may be placed in a high-temperature annealing furnace to perform annealing treatment on the first sublayer 13. In an epitaxial layer formed using a silicon carbide material as a motherboard, the annealing temperature of the first sublayer 13 may range from 1000° C. to 2300° C., and the annealing time may range from 10s to 10000s. In an epitaxial layer formed using a diamond material as a motherboard, the annealing temperature of the first sublayer 13 may range from 1200° C. to 3200° C., and the annealing time may range from 10s to 10000s.

[0147] For example, the first sublayer 13 may be polished by a CMP process, or by plasma bombarding the surface of the first sublayer away from the substrate to polish the first sublayer 13. After polishing, the surface roughness of the first sublayer is less than or equal to 0.2 nm.

[0148] In this way, the defective layer material remaining on the first sub-layer 13 can be removed, and the defects caused by the defective layer on the first sub-layer 13 can be repaired to avoid affecting the quality of the first sub-layer 13, so that the quality of the subsequently formed epitaxial sub-layer 15 can be higher, which is conducive to the formation of a high-quality composite substrate 40 and a semiconductor structure 100.

[0149] A420, such as Figure 7 As shown, an epitaxial sublayer 15 is epitaxially grown on the first sublayer 13 .

[0150] Exemplarily, the epitaxial sublayer 15 may be formed by homoepitaxial growth or heteroepitaxial growth.

[0151] For example, the epitaxial sublayer 15 may be a P-type doped epitaxial structure or an N-type doped epitaxial structure.

[0152] The epitaxial sublayer 15 is obtained by epitaxial growth of the first sublayer 13, and the first sublayer 13 is obtained by epitaxial growth of the mother board, so the quality index of the epitaxial sublayer 15 is related to the quality index of the mother board 11. In the embodiment of the present disclosure, a mother board 11 with a higher quality index is used, and the quality index of the epitaxial sublayer 15 obtained thereby is also higher, so that the quality index of the composite substrate 40 is higher, and thus a high-quality composite substrate 40 can be prepared.

[0153] For example, the motherboard 11 may be an N-type motherboard, the first sublayer 13 grown on the motherboard 11 may be a P-type doped epitaxial structure, and the epitaxial sublayer 15 grown from the first sublayer 13 may be a P-type doped epitaxial structure. Thus, the surface of the composite substrate 40 away from the substrate 30 is a P-type doped epitaxial structure (the epitaxial structure here includes the first sublayer 13 and the epitaxial sublayer 15), and epitaxial growth may continue on this surface to obtain a new P-type epitaxial structure.

[0154] Exemplarily, after the above A400, that is, after the first sub-layer 13 is separated from the second sub-layer 14 along the direction of the plane where the defective layer 20 is located, the preparation method further includes: polishing the second sub-layer 14.

[0155] For example, the second sublayer 14 may be polished by CMP process, or by plasma bombarding the surface of the second sublayer 14 away from the motherboard 11 to polish the second sublayer 14. After polishing, the surface roughness of the second sublayer 14 is less than or equal to 0.2 nm.

[0156] In this way, the defective layer material remaining on the surface of the second sub-layer 14 away from the mother substrate can be eliminated, and the defects on the surface of the second sub-layer 14 away from the mother substrate can be repaired, so that the quality of the second sub-layer 14 is higher, and the subsequent bonding strength between the second sub-layer 14 and another substrate is higher, which is beneficial to improving the quality of the prepared composite substrate.

[0157] Exemplarily, before the second sub-layer 14 is polished, the second sub-layer 14 may be annealed. The annealing may eliminate defects of the defective layer remaining on the second sub-layer 14 and improve the quality index of the second sub-layer 14 .

[0158] Illustratively, the annealing treatment of the first sublayer 13 and the second sublayer 14 can be performed simultaneously, the annealing treatment of the first sublayer 13 in multiple composite substrates 40 can also be performed simultaneously, the polishing treatment of the first sublayer 13 and the second sublayer 14 can also be performed simultaneously, and the polishing treatment of the first sublayer 13 in multiple composite substrates 40 can also be performed simultaneously. Thus, the annealing treatment can be performed in batches, and the polishing treatment can also be performed in batches, thereby reducing the preparation cost of multiple composite substrates 40.

[0159] The embodiment of the present disclosure also provides a composite substrate 40, such as Fig.10 As shown, the composite substrate 40 is prepared by using the preparation method described in any of the above embodiments.

[0160] The composite substrate 40 includes a substrate 30 and a first sublayer 13 located on one side of the substrate 30. The first sublayer 13 is an epitaxial structure of the composite substrate 30.

[0161] It can be understood that the beneficial effects that can be achieved by the composite substrate provided by the above embodiments of the present disclosure can refer to the beneficial effects of the method for preparing the composite substrate described above, which will not be described in detail here.

[0162] Exemplarily, the substrate 40 may be a P-type substrate, and the first sublayer 13 may be a P-type doped crystal.

[0163] like Fig.11 As shown, the composite substrate 40 further includes: an epitaxial sublayer 15 located on a side of the first sublayer 13 away from the substrate 40 .

[0164] The first sublayer 13 is a P-type epitaxial structure, and the epitaxial sublayer 15 is a P-type epitaxial structure. The epitaxial sublayer 15 can be obtained by epitaxial growth of the first sublayer 13 .

[0165] The embodiment of the present disclosure also provides a composite substrate 70, such as Fig.12 As shown, the composite substrate 70 includes: a first sub-layer 13 and an epitaxial sub-layer 15 located on one side of the first sub-layer 13 .

[0166] Exemplarily, the first sublayer 13 is a P-type epitaxial structure, and the epitaxial sublayer 15 is a P-type epitaxial structure.

[0167] There is no other structure between the first sub-layer 13 and the epitaxial sub-layer 15 .

[0168] The method for preparing the composite substrate 70 includes: forming a composite substrate 40 by using the preparation method described in any of the above embodiments, epitaxially growing an epitaxial sublayer 15 on the first sublayer 13 , and removing the substrate 30 in the composite substrate 40 .

[0169] During the process of forming the epitaxial sublayer 15 , the doping concentration and doping uniformity of the epitaxial sublayer 15 and the growth thickness of the epitaxial sublayer 15 may be controlled, thereby optimizing the quality of the epitaxial sublayer 15 .

[0170] In one implementation, a small-sized P-type composite substrate can be formed by bonding a P-type first sublayer and a P-type epitaxial sublayer. There is a dielectric layer between the first sublayer and the epitaxial sublayer for bonding. A small-sized P-type first sublayer or a P-type epitaxial sublayer can be formed by drawing, however, a large-sized P-type first sublayer or a P-type epitaxial sublayer cannot be formed by drawing, and thus a large-sized P-type composite substrate cannot be formed.

[0171] The preparation method of the composite substrate 70 provided in the above embodiment of the present disclosure can be used to form a large-sized P-type composite substrate, whose size is greater than or equal to 6 inches. The large-sized P-type composite substrate provided in the embodiment of the present disclosure does not need to be drawn, thereby bypassing the technical difficulties of drawing, and creating a method for epitaxially growing a P-type epitaxial layer (the epitaxial layer here can be the above-mentioned epitaxial sublayer 15) from a P-type substrate structure (the P-type substrate structure here can be the above-mentioned first sublayer 13), and the preparation cost is relatively low.

[0172] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for preparing a composite substrate, characterized in that: The preparation method comprises: forming a motherboard substrate, the motherboard substrate comprising a motherboard and an epitaxial layer located on one side of the motherboard; A defect layer is formed in the epitaxial layer; along the thickness direction of the motherboard, the defect layer divides the epitaxial layer into a first sublayer away from the motherboard and a second sublayer close to the motherboard; permanently bonding a substrate to the first sub-layer; The first sublayer and the second sublayer are separated along the direction of the plane where the defective layer is located; the substrate and the first sublayer form a composite substrate; the motherboard and the second sublayer form a composite motherboard; The steps of forming a defective layer in the epitaxial layer, permanently bonding the substrate to the first sublayer, and separating the first sublayer from the second sublayer along the plane where the defective layer is located are performed in a loop N times, and a composite substrate and a composite mother plate are obtained after each execution of the loop; in forming the defective layer in the epitaxial layer in each loop, the second sublayer in the composite mother plate formed in the previous loop is used as the epitaxial layer in the current loop process; N is greater than or equal to 1, and N is a positive integer.

2. The preparation method according to claim 1, characterized in that: The forming of a defect layer in the epitaxial layer comprises: Target ions are implanted into the epitaxial layer from a side of the epitaxial layer away from the mother plate to form the defect layer.

3. The preparation method according to claim 2, characterized in that: The target ion implantation depth ranges from 0.1 μm to 5 μm.

4. The preparation method according to claim 2, characterized in that: The target ions include at least one of hydrogen ions and helium ions.

5. The preparation method according to claim 1, characterized in that: The forming of a defect layer in the epitaxial layer comprises: The epitaxial layer is irradiated with laser light from a side of the epitaxial layer away from the mother substrate to form the defective layer.

6. The preparation method according to claim 5, characterized in that: The laser irradiation depth is less than or equal to 200 μm.

7. The preparation method according to claim 1, characterized in that: The thickness of the epitaxial layer ranges from 3 μm to 1000 μm.

8. The preparation method according to any one of claims 1 to 7, characterized in that The forming of the motherboard substrate comprises: Providing a motherboard, wherein the crystal form of the motherboard is single crystal; An epitaxial layer is epitaxially grown on the mother substrate.

9. The preparation method according to claim 8, characterized in that: The dislocation density of the mother plate is less than or equal to a first preset value.

10. The preparation method according to claim 9, characterized in that: The material of the motherboard includes: silicon carbide or diamond; the first preset value is 100 pieces / cm 2 .

11. The preparation method according to claim 8, characterized in that: The motherboard material includes: gallium oxide or Al x Ga 1-x N; where 0≤x≤1.

12. The preparation method according to claim 8, characterized in that: The process of homoepitaxially growing an epitaxial layer on the motherboard includes: a chemical vapor deposition process, a molecular beam epitaxy process or a liquid phase epitaxy process.

13. The preparation method according to claim 1, characterized in that: Before permanently bonding the substrate to the first sub-layer, the preparation method further comprises: Polishing a surface of the first sub-layer that is away from the motherboard; After separating the first sublayer from the second sublayer along the direction of the plane where the defective layer is located, the preparation method further comprises: performing annealing and polishing on the first sub-layer; An epitaxial sublayer is epitaxially grown on the first sublayer.

14. The preparation method according to claim 1, characterized in that: After separating the first sublayer from the second sublayer along the direction of the plane where the defective layer is located, the preparation method further comprises: The second sub-layer is subjected to annealing and polishing treatments.

15. A composite substrate, characterized in that: A composite substrate formed by the preparation method according to any one of claims 1 to 14; the composite substrate comprises a substrate and a first sublayer located on one side of the substrate.

16. The composite substrate according to claim 15, characterized in that The composite substrate further comprises an epitaxial sublayer located on a side of the first sublayer away from the substrate; The first sublayer is a P-type epitaxial structure, and the epitaxial sublayer is a P-type epitaxial structure.

17. A composite substrate, characterized in that The composite substrate comprises: a first sublayer and an epitaxial sublayer located on one side of the first sublayer; The first sublayer is a P-type epitaxial structure, and the epitaxial sublayer is a P-type epitaxial structure.

18. A semiconductor structure, characterized in that: include: Heterojunction, And the composite substrate according to claim 15 or the composite base according to claim 17 located at one side of the heterojunction.

19. An electronic device, characterized in that: It comprises the semiconductor structure and a circuit board as claimed in claim 18, wherein the circuit board is connected to the semiconductor structure.

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