LDMOS device and manufacturing method thereof

Abstract

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof. The method comprises the following steps: providing a semiconductor substrate; a photoresist layer with an opening is formed on the surface of the semiconductor substrate, the opening at least exposes the surface of a region, where a drain region is predetermined to be formed, of the semiconductor substrate, the photoresist layer covers part of the surface corresponding to the first region, and the body region is predetermined to be located on the side, away from the drain region, of the drift region; performing first-time first conduction type ion implantation on at least the first region exposed from the opening; performing a finishing process on the photoresist layer to enlarge the opening; taking the trimmed photoresist layer as a mask, and at least executing second-time first conductive type ion implantation on the first region exposed out of the opening; the trimming process and the first conduction type ion implantation step are repeatedly executed at least once, the drift region comprises a plurality of implantation regions with different doping concentrations, and the doping concentrations of the plurality of implantation regions are gradually reduced in the direction from the drain region to the body region, so that the breakdown voltage is improved, and the specific on-resistance is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an LDMOS device and a manufacturing method thereof. Background Art

[0002] As one of the important components of power devices, lateral double-diffused MOSFET (LDMOS) has broad application prospects.

[0003] For high-performance power devices, the breakdown voltage and on-resistance of LDMOS are important parameters for measuring device performance. The specific on-resistance (Ron,sp) will increase with the increase of the breakdown voltage (BV). In addition to the high breakdown voltage (BV), the device also needs a lower on-resistance Ron. Ron always decreases with the increase of the doping concentration in the drift region. However, the increase of the doping concentration in the drift region will cause the BV to decrease. Figure 1 and Figure 2 As shown, the current conventional LDMOS drift region (that is) adopts a one-time window opening and overall injection method. The drift region is uniformly doped, but the surface electric field of the uniformly doped drift region presents a deep "U"-shaped distribution, and the surface electric field of the drift region has two peaks. The drift region electric field peak generally appears at the junction of the body region and the drift region (that is, the Pbody / NDR junction) and the high-voltage drain (Drain) end. When the device breaks down, it is usually on the surface. The integral of the surface electric field along the length direction of the drift region is the lateral withstand voltage. Therefore, this uneven surface electric field greatly limits the breakdown voltage of the device, and this limitation becomes more and more obvious as the length of the drift region increases.

[0004] Therefore, in order to solve the above technical problems, it is necessary to provide a new LDMOS device and a manufacturing method thereof. Summary of the invention

[0005] A series of simplified concepts are introduced in the summary of the invention, which will be exemplarily described in detail in the detailed description of the invention. The summary of the invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] In view of the shortcomings of the related art, the present invention provides a method for manufacturing an LDMOS device, comprising:

[0007] Providing a semiconductor substrate, wherein the semiconductor substrate has a first region that is intended to form a drift region and a second region that is intended to form a body region;

[0008] forming a photoresist layer having an opening on the surface of the semiconductor substrate, wherein the opening at least exposes the surface of a region of the first region where the drain region is to be formed, the photoresist layer covers a portion of the surface corresponding to the first region, and the body region is to be located on a side of the drift region away from the drain region;

[0009] Using the photoresist layer as a mask, performing a first first conductivity type ion implantation on at least the first region exposed by the opening;

[0010] Performing a trimming process on the photoresist layer to enlarge the opening and reduce the first area covered by the photoresist layer;

[0011] Using the trimmed photoresist layer as a mask, performing a second first conductivity type ion implantation on at least the first region exposed by the opening;

[0012] Repeating the trimming process and the first conductivity type ion implantation step at least once until a drift region having the first conductivity type is formed in the semiconductor substrate,

[0013] The drift region includes a plurality of implantation regions with different doping concentrations, and the doping concentrations of the plurality of implantation regions gradually decrease along a direction from the drain region to the body region.

[0014] Exemplarily, the energy of the first conductivity type ion implantation in the previous time is higher than the energy of the first conductivity type ion implantation in the next time, and / or

[0015] The doping dose of the first conductivity type ion implantation in the previous time is higher than the doping dose of the first conductivity type ion implantation in the next time.

[0016] Exemplarily, the trimming process is performed by a plasma etching method.

[0017] Exemplarily, the trimming process includes isotropically etching the photoresist layer.

[0018] Exemplarily, the manufacturing method further includes:

[0019] removing the photoresist layer;

[0020] Performing second conductivity type ion implantation on the semiconductor substrate to form a body region of second conductivity type in the semiconductor substrate, wherein the second conductivity type is opposite to the first conductivity type;

[0021] forming a gate structure on the surface of the semiconductor substrate, wherein the gate structure covers a portion of the surface of the drift region and a portion of the surface of the body region;

[0022] A source region and a drain region with a first conductivity type are formed respectively on both sides of the gate structure, and the source region is located in the body region.

[0023] Exemplarily, a buried layer of the first conductivity type is further formed below the drift region, and the manufacturing method further includes:

[0024] After forming the drift region and before forming the body region, a first well region with a first conductivity type and a second well region with a second conductivity type are formed in the semiconductor substrate, wherein the first well region extends downward from the surface of the semiconductor substrate to connect with the buried layer, the first well region is used to lead out the buried layer, and the second well region extends downward from the surface of the semiconductor substrate to contact with the buried layer.

[0025] Exemplarily, when the LDMOS device is in an off state, the peak value of the electric field in the drift region is consistent with the number of the injection regions.

[0026] Another aspect of the present application further provides an LDMOS device, the device comprising:

[0027] Semiconductor substrate;

[0028] A drift region of the first conductivity type is disposed in the semiconductor substrate;

[0029] A body region of a second conductivity type is arranged outside the drift region, wherein the second conductivity type is opposite to the first conductivity type;

[0030] A drain region of the first conductivity type is arranged in the drift region and away from the body region,

[0031] The drift region includes a plurality of implantation regions with different doping concentrations, and the doping concentrations of the plurality of implantation regions gradually decrease along a direction from the drain region to the body region.

[0032] Exemplarily, it also includes:

[0033] A gate structure is disposed on the surface of the semiconductor substrate, and the gate structure covers a portion of the surface of the drift region and a portion of the surface of the body region;

[0034] A source region of a first conductivity type, the source region and the drain region are respectively located at two sides of the gate structure, wherein the source region is located in the body region.

[0035] Exemplarily, a buried layer of the first conductivity type is also formed below the drift region, and a first well region with the first conductivity type and a second well region with the second conductivity type are formed in the semiconductor substrate, wherein the first well region extends downward from the surface of the semiconductor substrate to connect with the buried layer, the first well region is used to lead out the buried layer, and the second well region extends downward from the surface of the semiconductor substrate to contact the buried layer.

[0036] The LDMOS device and the manufacturing method thereof of the present invention perform at least one trimming on the photoresist layer, thereby realizing multiple window openings (i.e., corresponding openings in the photoresist layer) when ion implantation is performed on the drift region, and first conductive type ion implantation is performed after each opening, thereby forming multiple implantation regions with different doping concentrations in the drift region, and the doping concentrations of the multiple implantation regions gradually decrease from the drain region to the body region, thereby forming a slowly varying doping structure, increasing the number of surface electric field peaks in the drift region, improving the surface electric field distribution, increasing BV, and reducing the specific on-resistance. In addition, the method of the present application is simple, low-cost, and does not require additional mask plates. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0038] In the attached figure:

[0039] Figure 1 A cross-sectional view of a drift region formed in an LDMOS device in the related art;

[0040] Figure 2 A schematic diagram of the surface electric field of the drift region of an LDMOS device in the related art;

[0041] Figure 3A and Figure 3B A schematic structural diagram of a device obtained by the relevant steps of a method for manufacturing an LDMOS device in the related art is shown;

[0042] Figure 4A and Figure 4B A schematic structural diagram of a device obtained by the relevant steps of a method for manufacturing an LDMOS device in the related art is shown;

[0043] FIG. 5A to FIG. 5E A schematic structural diagram of a device obtained by the relevant steps of a method for manufacturing an LDMOS device in an embodiment of the present application is shown;

[0044] FIG. 6A to FIG. 6B A schematic diagram of trimming a photoresist layer in one embodiment of the present application is shown;

[0045] Figure 7 A schematic diagram showing multiple trimming of a photoresist layer and multiple ion implantation in one embodiment of the present application is shown;

[0046] Figure 8 FIG. 4 is a process flow chart of a method for manufacturing an LDMOS device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0048] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0049] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0050] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0051] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "a", "an" and " / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "consisting of" and / or "comprising" when used in this specification determine the presence of features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0052] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0053] In order to fully understand the present invention, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0054] Related technologies such as LDMOS Figure 1 and Figure 2As shown in the figure, for high-voltage power devices, the breakdown voltage and on-resistance of LDMOS are important parameters for measuring device performance. In order to reduce the on-resistance of the drift region, it is usually chosen to increase the doping concentration of the drift region or reduce the length of the drift region. However, both of these will lead to a decrease in the withstand voltage of the device. Generally, the specific on-resistance (Ron,sp) of the device will increase with the increase of the breakdown voltage (BV).

[0055] As above Figure 1 As shown, the LDMOS drift region is often injected once with a window, and then injected once. The drift region is uniformly doped by high-temperature annealing. This solution is relatively simple and low in cost, but the surface electric field of the uniformly doped drift region presents a deep "U"-shaped distribution, and the surface electric field of the drift region has two peaks: 1. Pbody / NDR junction, 2. High-voltage Drain end. When the device breaks down, it is usually on the surface. The surface electric field is integrated along the length of the drift region, which is the lateral withstand voltage. Therefore, this uneven surface electric field greatly limits the breakdown voltage of the device, and this limitation becomes more and more obvious as the length of the drift region increases. In order to ensure the reliability of the device, the drift region size of the high-voltage LDMOS cannot be made very small, that is, the pitch of the device cannot be very small. When the drift region is uniformly injected once, the on-resistance of the device is relatively large. Under normal working conditions, the device will generate a lot of heat, which seriously affects the device performance. At the same time, the limitation of the device pitch also leads to the inability to further reduce the chip area.

[0056] In order to improve the above-mentioned problem of uniformly doping the drift region, the technology of step doping of the drift region has been proposed many times, such as Figure 3A and Figure 3B As shown, in the first related technology, the step doping of the drift region is realized by using a solution of multiple masks, which greatly increases the process cost. At the same time, the doping times of the drift region are limited by the number of mask layers and there are also alignment errors in multiple exposures, and the repeatability of the device is not good. In the second related technology, the gate oxide 301 and the polysilicon 302 are first formed to generate a step difference. The drift region (IMP1, IMP2, IMP3, IMP4) needs to be implanted through different film layers, and the implantation depth and concentration are inconsistent, so as to form the step doping of the drift region. This solution still has the disadvantage that the doping times are limited by the number of steps, and the injection error caused by the error in the thickness of the film layer will also cause the error of the device. The process flow is complicated and the cost is correspondingly increased.

[0057] In order to solve the above technical problems, the present invention provides a method for manufacturing an LDMOS device, such as Figure 8 As shown, it includes:

[0058] In step S810, a semiconductor substrate is provided, wherein the semiconductor substrate has a first region that is intended to form a drift region and a second region that is intended to form a body region;

[0059] In step S820, a photoresist layer having an opening is formed on the surface of the semiconductor substrate, wherein the opening at least exposes the surface of the region where the drain region is to be formed in the first region, the photoresist layer covers a portion of the surface corresponding to the first region, and the body region is to be located on a side of the drift region away from the drain region;

[0060] In step S830, using the photoresist layer as a mask, a first first conductivity type ion implantation is performed at least on the first region exposed by the opening;

[0061] In step S840, a trimming process is performed on the photoresist layer to enlarge the opening and reduce the first area covered by the photoresist layer;

[0062] In step S850, using the trimmed photoresist layer as a mask, a second first conductivity type ion implantation is performed at least on the first region exposed by the opening;

[0063] In step S860, the trimming process and the first conductive type ion implantation step are repeated at least once until a drift region with the first conductive type is formed in the semiconductor substrate, wherein the drift region includes a plurality of implantation regions with different doping concentrations, and the doping concentrations of the plurality of implantation regions gradually decrease along a direction from the drain region to the body region.

[0064] The LDMOS device and the manufacturing method thereof of the present invention perform at least one trimming on the photoresist layer, thereby realizing multiple window openings (i.e., corresponding openings in the photoresist layer) when ion implantation is performed on the drift region, and first conductive type ion implantation is performed after each opening, thereby forming multiple implantation regions with different doping concentrations in the drift region, and the doping concentrations of the multiple implantation regions gradually decrease from the drain region to the body region, thereby forming a slowly varying doping structure, increasing the number of surface electric field peaks in the drift region, improving the surface electric field distribution, increasing BV, and reducing the specific on-resistance. In addition, the method of the present application is simple, low-cost, and does not require additional mask plates.

[0065] Embodiment 1

[0066] The following will refer to FIG. 5A to FIG. 5E , FIG. 6A to FIG. 6B , Figure 7 and Figure 8 , the LDMOS device and the manufacturing method thereof of the present invention are described in detail. Under the premise of no conflict, the technical features of the various embodiments of the present application can be combined with each other.

[0067] In one embodiment, the manufacturing method 800 of the LDMOS device of the present application includes the following steps S810 to S860:

[0068] First, in step S810, Figure 5A As shown, a semiconductor substrate 500 is provided, wherein the semiconductor substrate 500 has a first region where a drift region is to be formed and a second region where a body region is to be formed.

[0069] Specifically, the semiconductor substrate 500 may be at least one of the following materials: silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). As an example, in this embodiment, the constituent material of the semiconductor substrate 500 is SOI.

[0070] Exemplarily, the semiconductor substrate 500 may be a P-type substrate or an N-type substrate. For example, the semiconductor substrate 500 includes a first region predetermined to form a drift region, a third region predetermined to form a drain region, and a second region predetermined to form a body region, wherein the third region is located at a first side of the first region and in the first region, the second region is adjacent to a second side of the first region, and the first side and the second side are opposite.

[0071] Next, in step S820, continue to refer to Figure 5A A photoresist layer 510 having an opening 511 is formed on the surface of the semiconductor substrate 500, wherein the opening 511 at least exposes the surface of the area where the drain region is predetermined to be formed in the first region, and the photoresist layer 510 covers a portion of the surface corresponding to the first region, and the body region is predetermined to be located on the side of the drift region away from the drain region.

[0072] In some examples, the photoresist layer 510 can be selected from a photoresist material in the group including a positive photoresist material, a negative photoresist material, and a mixed photoresist material. The photoresist layer 510 can include a positive photoresist material or a negative photoresist material having a thickness from about 2000 to about 5000 angstroms. This thickness range is only used as an example, and other suitable values ​​can also be selected without limitation.

[0073] In a specific embodiment, a photoresist layer 510 may be coated on the surface of the semiconductor substrate 500, and then exposure may be performed, and a portion of the light beam may be transmitted through the photoresist layer 510 using a photomask, and irradiated onto the photoresist layer 510, and reacted with the photoresist layer 510, thereby defining a preliminary pattern. Optionally, a post-exposure bake (PEB) step may be performed after exposure to reduce the standing wave effect. In one example, a hot plate method is used to perform the post-baking step.

[0074] The exposed photoresist layer 510 is developed, and a developer is sprayed onto the surface of the photoresist layer 510 to remove the reacted photoresist layer 510 to form a final pattern, that is, a photoresist layer 510 with an opening 511. A suitable developer can be selected according to the type of the photoresist layer 510 used. For example, when the photoresist layer 510 is a positive photoresist, tetramethylammonium hydroxide (TMAH) can be selected as the developer, and when the photoresist layer 510 is a negative photoresist, xylene can be selected as the developer.

[0075] Among them, the opening 511 exposes the surface corresponding to the area predetermined to form the drain region, or can also expose a portion of the surface of the first area adjacent to the drain region for forming the drift region, while the portion of the surface of the first area adjacent to the body region for forming the drift region is covered by the photoresist layer 510, and the area predetermined to form the body region is also covered by the photoresist layer 510. Through such a setting, it is convenient to control the position of the injection area corresponding to each ion injection, so that the injection sequence is gradually expanded from the drain region side to the body region side.

[0076] Next, in step S830, continue to refer to Figure 5A , using the photoresist layer 510 as a mask, performing a first first conductivity type ion implantation on at least the first region exposed by the opening 511 .

[0077] The doping impurities of the first conductive type ion implantation can be determined according to the conductive type of the drift region to be formed. For example, if the drift region is to be formed with an N-type conductive type, the doping impurities of the ion implantation can be phosphorus, arsenic, etc., and if the drift region is to be formed with a P-type conductive type, the doping impurities of the ion implantation can be boron, BF2, etc. In the embodiment of the present application, the first conductive type and the second conductive type are opposite, for example, if the first conductive type is N-type, the second conductive type is P-type, or if the first conductive type is P-type, the second conductive type is N-type. In the embodiment of the present application, the first conductive type is N-type and the second conductive type is P-type as an example, but this is not intended to constitute a limitation.

[0078] Through the first conductivity type 1 ion implantation, a first implant region IMP1 is formed in the semiconductor substrate 500 , where the first implant region IMP1 is a part of the drift region.

[0079] Next, in step S840, refer to Figure 5B , the photoresist layer 510 is trimmed to expand the opening 511, reduce the first area covered by the photoresist layer 510, and reduce the surface of the area in the semiconductor substrate 500 where the drift region is to be formed and covered by the photoresist layer 510.

[0080] The trimming process is performed by etching. The etching may refer to plasma etching or any other method capable of etching and trimming the photoresist layer. For example, plasma etching uses plasma capable of reacting with molecules of the photoresist layer 510, such as oxygen plasma, to trim the photoresist layer 510. In a specific example, a semiconductor substrate 500 having a photoresist layer 510 is placed in a vacuum chamber of a plasma processing device, oxygen is introduced, and then the oxygen molecules are excited by discharge to generate a plasma containing a large number of active oxygen ions and oxygen atoms. These active oxygen ions and atoms have high energy and can chemically react with carbon, hydrogen and other elements in a portion of the photoresist layer 510, thereby removing the photoresist layer 510 on the side wall of the opening 511 and increasing the size of the opening 511.

[0081] Trimming is similar to etching. It can remove part of the photoresist through plasma, and the etching of the photoresist is isotropic. Fig. 6A and Figure 6B As shown, the photoresist layer 510 (PR) forms a pattern (i.e., an opening 511) through an exposure process, and its line width is x. Then, the pattern in the photoresist layer 510 formed by exposure is trimmed by a trimming process. In the trimming process, by controlling the trimming time, the width of the opening 511 expanded to both sides, i.e., the width of the PR, can be accurately controlled dx. At the same time, due to the isotropy of the photoresist layer 510 process, the thickness of the PR also decreases dt accordingly. Although the thickness of the photoresist is also reduced accordingly while the width of the pattern is expanded each time the photoresist layer 510 is expanded. The amount of doping impurities implanted into each implantation region can be controlled by making the energy of the previous first conductivity type ion implantation higher than the energy of the next first conductivity type ion implantation and / or the doping dose of the previous first conductivity type ion implantation higher than the doping dose of the next first conductivity type ion implantation, i.e., by gradually reducing the energy and / or dose of the ion implantation, thereby controlling the doping concentration of multiple implantation regions from the drain region to the body region, so that the doping concentration of multiple implantation regions gradually decreases.

[0082] In some embodiments, in order to ensure the masking effect of the photoresist layer 510, the initial thickness of the photoresist layer 510 can be controlled to overcome the problem of PR thinning caused by subsequent trimming, which affects the concentration of doped impurities in the drift region, thereby achieving precise control of the doping concentration in the drift region.

[0083] As the size of the opening 511 increases, the surface of the semiconductor substrate 500 exposed in the opening 511 increases, especially more surfaces corresponding to the drift region are exposed, so that it is convenient to implant the drift region through subsequent ion implantation. After the first trimming, the area of ​​the drift region covered by the photoresist layer 510 can be reduced to zero, or part of the drift region can still be covered by the photoresist layer 510, and during the subsequent second first conductivity type ion implantation, the implantation of the area covered by the photoresist layer 510 is reduced.

[0084] Next, in step S850, refer to Figure 5B , using the trimmed photoresist layer 510 as a mask, performing a second first conductivity type ion implantation on at least the first region exposed by the opening 511 .

[0085] Due to the expansion of the opening 511, the second first conductivity type ion implantation is performed on more areas in the first region, and the second first conductivity type ion implantation is also performed on the aforementioned first implantation region IMP1. At the same time, a second implantation region IMP2 is formed on the side of the first implantation region IMP1 away from the drain region. Since the first implantation region IMP1 is implanted with the first conductivity type ion twice, its doping concentration is higher than that of the second implantation region IMP2.

[0086] Next, execute step S860, such as Figure 5C As shown, the trimming process and the first conductivity type ion implantation steps are repeated at least once until a drift region 520 having the first conductivity type is formed in the semiconductor substrate 500, that is, ion implantation is performed on all regions between the drain region and the body region for forming the drift region 520.

[0087] It is worth mentioning that only one trimming and one first conductivity type ion implantation may be performed, or two or more trimming and two or more first conductivity type ion implantations may be performed, so that the drift region 520 of the row has more implantation regions with different doping concentrations, so as to increase the number of surface electric field peaks in the drift region 520, improve the surface electric field distribution, increase BV, and reduce the specific on-resistance. In addition, the method of the present application is simple, low-cost, and does not require additional mask plates.

[0088] Optionally, when the LDMOS device is in an off state, the peak value of the electric field in the drift region 520 is consistent with the number of the injection region.

[0089] In some embodiments, Figure 5CAs shown, the photoresist layer 510 is trimmed for the second time to further expand the opening 511, and then the semiconductor substrate 500 exposed by the opening 511 is implanted with the first conductive type ion again. Since the edge and body region of the opening 511 correspond to the boundary of the drift region 520 after this trimming, the implantation of the entire drift region 520 is completed after this first conductive type ion implantation. The first conductive type ion implantation again implants ions into the first implantation region IMP1 and the second implantation region IMP2 formed previously, and forms a third implantation region IMP3 on the side of the second implantation region IMP2 away from the drain region. The doping concentration of the first implantation region IMP1 is higher than that of the second implantation region IMP2, and the doping concentration of the second implantation region IMP1 is higher than that of the third implantation region IMP2. That is, the window opening region (that is, the opening 511 region) after the second trimming includes the window opening region of the previous time, that is, the ion implantation region of the next time includes the implantation region of the previous time, and as the trimming proceeds, step doping of the drift region 520 is generated.

[0090] like Figure 7 As shown, the photoresist layer 510 can be trimmed and implanted with the first conductive type ions multiple times, for example, trimmed five times, and then implanted with the first conductive type ions five times after the first implantation. Then, six implantation regions with different doping concentrations are formed in the drift region 520. If the number of trimming and first conductive type ion implantations increases, more peaks may appear in the surface electric field of the drift region 520, and the breakdown voltage can be greatly improved.

[0091] Since multiple trimmings can be performed, in some embodiments, the number of implantation regions with different doping concentrations included in the drift region 520 in the embodiments of the present application can reach 4 or more.

[0092] Through the above, the drift region 520 includes multiple injection regions with different doping concentrations, and the doping concentrations of the multiple injection regions gradually decrease along the direction from the drain region to the body region. For example, along the direction from the drain region to the body region, the doping concentrations of the multiple injection regions present a descending step-like distribution. Through such a setting, the surface electric field of the drift region 520 is evenly distributed, the breakdown voltage is improved, and the specific on-resistance is reduced, thereby improving the performance of the device.

[0093] The device structure of the step-doped drift region 520 and the surface electric field distribution of the drift region 520 achieved by multiple first conductive type ion implantation and trimming processes are shown in FIG. Figure 5E As shown, similar to the electric field distribution of the drift region 520 uniformly doped with LDMOS, there are higher electric field peaks at both ends of the drift region 520. At the same time, at the junction of the step doping, a new electric field peak appears due to different doping concentrations.

[0094] Through the trimming process, the surface doping concentration changes stepwise, reducing the electric field at the Pbody / NDR junction and the drain end of the device (i.e., the drain region), while introducing a new electric field peak in the middle of the drift region 520, increasing the electric field in the middle of the drift region 520, and improving the surface electric field distribution, which is conducive to reducing the on-resistance while achieving high withstand voltage. Moreover, as the number of trimming processes increases, the electric field at the source and drain end of the drift region 520 decreases, and the surface electric field becomes more uniform. In addition, since the trimming process does not need to increase the mask cost, its cost and technical implementation can be low.

[0095] In addition, by gradually reducing the doping concentration of the drift region 520 from the drain region to the body region, the size of the drift region 520 can be reduced while ensuring a high breakdown voltage and a low specific on-resistance, thereby reducing the device size and better balancing the breakdown voltage and specific on-resistance.

[0096] Furthermore, in some embodiments, after the implantation of the drift region 520 is completed, the photoresist layer 510 may be removed to perform subsequent manufacturing steps.

[0097] For example, Figure 5D and Figure 5E As shown, the manufacturing method of the present application also includes: performing second conductive type ion implantation on the semiconductor substrate 500 to form a body region 530 with a second conductive type in the semiconductor substrate 500; forming a gate structure 560 on the surface of the semiconductor substrate 500, the gate structure 560 covering a portion of the surface of the drift region 520 and a portion of the surface of the body region 530; forming a source region 580 and a drain region 570 with a first conductive type respectively located on both sides of the gate structure 560, wherein the drain region 570 and the body region 530 are respectively located on both sides of the drift region 520, and the source region 580 is located in the body region 530.

[0098] Optionally, the drift region 520 is an N-type drift region 520 , preferably a lightly doped N-type drift region 520 , and the body region 530 is a P-type body region 530 .

[0099] Exemplarily, the body region 530 is formed by a second conductivity type ion implantation process, and the specific implanted doping ion type is reasonably selected according to the process of the actual device, which will not be described in detail here.

[0100] The depth of ion implantation can be controlled by controlling the energy of ion implantation. After ion implantation, an annealing step can also be performed to activate the doped ions in each implantation region. The annealing process uses rapid thermal annealing (RTA) or other suitable annealing methods. The annealing can be performed after the drift region 520 is formed, and then annealed after the body region 530 is formed, or it can be uniformly annealed after all ion implantations are completed. The specific setting can be reasonable according to actual needs.

[0101] Exemplarily, the gate structure 560 can be prepared by any suitable method. A gate dielectric layer can be first formed on the surface of the semiconductor substrate 500 by deposition or thermal oxidation, and then a polysilicon material layer is deposited to cover the gate dielectric layer and the field oxide layer. The polysilicon material layer is patterned to form a gate layer. The gate dielectric layer and the gate layer constitute the gate structure 560.

[0102] The gate dielectric layer may include conventional dielectric materials such as oxides, nitrides and oxynitrides of silicon having a dielectric constant ranging from about 4 to about 20 (measured in vacuum). Alternatively, the material of the gate layer may include polysilicon and / or metal materials such as W or the like.

[0103] In some embodiments, a buried layer NBL of the first conductivity type is further formed below the drift region 520. The manufacturing method of the present application further includes: after forming the drift region 520 and before forming the body region 530, forming a first well region 540 having the first conductivity type and a second well region 550 having the second conductivity type in the semiconductor substrate 500, wherein the first well region 540 extends downward from the surface of the semiconductor substrate 500 to connect with the buried layer NBL, and is used to lead out the buried layer NBL, and the first well region 540 is used as an isolation ring, which together with the buried layer NBL acts as a device isolation. In order to achieve the isolation effect, the doping concentration of the first well region 540 is higher than the doping concentration of the drift region 520. Optionally, the first well region 540 and the second well region 550 can both be deep well regions. For example, the bottom of the first well region 540 is connected to a buried layer NBL of the first conductivity type in the substrate, and the second well region 550 extends downward from the surface of the semiconductor substrate to contact the buried layer NBL. It can also be used as an isolation ring to achieve isolation. When an inversion layer (not shown) with the second conductivity type can also be formed between the buried layer NBL and the drift region, the second well region 550 is connected to the inversion layer.

[0104] The source region 580 and the drain region 570 have the same conductivity type as the drift region 520. For example, if the drift region 520 is an N-type drift region 520, the source region 580 and the drain region 570 are N-type source region 580 and drain region 570. In the present embodiment, the impurity doping concentration of the drain region 570 is greater than the impurity doping concentration of the drift region 520. For example, the drift region 520 is a lightly doped N-type drift region 520, and the drain region 570 is a heavily doped N-type doping region.

[0105] So far, the key steps of the manufacturing method of the LDMOS device of this embodiment have been introduced. The complete device preparation may also include other steps, which are not limited here. It should be explained that, in addition, in this embodiment, "N-type" refers to being doped with N-type dopant ions, and "P-type" refers to being doped with P-type dopant ions.

[0106] Embodiment 2

[0107] like Figure 5E As shown, the present application further provides an LDMOS device, which can be manufactured using the aforementioned manufacturing method. To avoid repetition, some details in the embodiments of the present application may refer to the aforementioned related descriptions, which will not be repeated here.

[0108] As an example, Figure 5E As shown, the LDMOS device in the embodiment of the present application includes:

[0109] A semiconductor substrate 500;

[0110] A drift region 520 of the first conductivity type is disposed in the semiconductor substrate 500;

[0111] A body region 530 of a second conductivity type, disposed outside the drift region 520, wherein the second conductivity type is opposite to the first conductivity type;

[0112] The drain region 570 of the first conductivity type is disposed in the drift region 520 and is away from the body region 530.

[0113] The drift region 520 includes a plurality of implantation regions with different doping concentrations, and the doping concentrations of the plurality of implantation regions gradually decrease along a direction from the drain region 570 to the body region 530 .

[0114] In some embodiments, a gate structure 560 and a source region 580 of the first conductive type are also included. The gate structure 560 is disposed on the surface of the semiconductor substrate 500. The gate structure 560 covers a portion of the surface of the drift region 520 and a portion of the surface of the body region 530. The source region 580 and the drain region 570 are respectively located on both sides of the gate structure 560, wherein the source region 580 is located in the body region 530.

[0115] In some embodiments, a buried layer NBL of the first conductivity type is also formed below the drift region 520, and a first well region 540 with the first conductivity type and a second well region 550 with the second conductivity type are formed in the semiconductor substrate 500, wherein the first well region 540 extends downward from the surface of the semiconductor substrate 500 to connect with the buried layer NBL, the first well region 540 is used to lead out the buried layer NBL, the doping concentration of the first well region 540 is higher than the doping concentration of the drift region 520, and the second well region 550 extends downward from the surface of the semiconductor substrate 500 to contact with the buried layer NBL.

[0116] The LDMOS device of the present application has substantially the same advantages as the aforementioned manufacturing method.

[0117] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for manufacturing an LDMOS device, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate has a first region that is intended to form a drift region and a second region that is intended to form a body region; forming a photoresist layer having an opening on the surface of the semiconductor substrate, wherein the opening at least exposes the surface of a region of the first region where the drain region is to be formed, the photoresist layer covers a portion of the surface corresponding to the first region, and the body region is to be located on a side of the drift region away from the drain region; Using the photoresist layer as a mask, performing a first first conductivity type ion implantation on at least the first region exposed by the opening; Performing a trimming process on the photoresist layer to enlarge the opening and reduce the first area covered by the photoresist layer; Using the trimmed photoresist layer as a mask, performing a second first conductivity type ion implantation on at least the first region exposed by the opening; Repeating the trimming process and the first conductivity type ion implantation step at least once until a drift region having the first conductivity type is formed in the semiconductor substrate, The drift region includes a plurality of implantation regions with different doping concentrations, and the doping concentrations of the plurality of implantation regions gradually decrease along a direction from the drain region to the body region.

2. The manufacturing method according to claim 1, characterized in that The energy of the first conductivity type ion implantation in the previous time is higher than the energy of the first conductivity type ion implantation in the next time, and / or The doping dose of the first conductivity type ion implantation in the previous time is higher than the doping dose of the first conductivity type ion implantation in the next time.

3. The manufacturing method according to claim 1, characterized in that: The trimming process is performed by a plasma etching method.

4. The manufacturing method according to claim 1, characterized in that: The trimming process includes isotropically etching the photoresist layer.

5. The manufacturing method according to claim 1, characterized in that: The manufacturing method further comprises: removing the photoresist layer; Performing ion implantation of a second conductivity type into the semiconductor substrate to form a body region of a second conductivity type in the semiconductor substrate, wherein the second conductivity type is opposite to the first conductivity type; forming a gate structure on the surface of the semiconductor substrate, wherein the gate structure covers a portion of the surface of the drift region and a portion of the surface of the body region; A source region and a drain region with a first conductivity type are formed respectively on both sides of the gate structure, and the source region is located in the body region.

6. The manufacturing method according to claim 1, characterized in that: A buried layer of the first conductivity type is also formed below the drift region, and the manufacturing method further includes: After forming the drift region and before forming the body region, a first well region with a first conductivity type and a second well region with a second conductivity type are formed in the semiconductor substrate, wherein the first well region extends downward from the surface of the semiconductor substrate to connect with the buried layer, the first well region is used to lead out the buried layer, and the second well region extends downward from the surface of the semiconductor substrate to contact with the buried layer.

7. The manufacturing method according to claim 1, characterized in that: When the LDMOS device is in an off state, the peak value of the electric field in the drift region is consistent with the number of the injection regions.

8. An LDMOS device, characterized in that: The device comprises: Semiconductor substrate; A drift region of a first conductivity type is disposed in the semiconductor substrate; A body region of a second conductivity type is disposed outside the drift region, wherein the second conductivity type is opposite to the first conductivity type; a drain region of a first conductivity type, arranged in the drift region and away from the body region, The drift region includes a plurality of implantation regions with different doping concentrations, and the doping concentrations of the plurality of implantation regions gradually decrease along a direction from the drain region to the body region.

9. The device according to claim 8, characterized in that Also includes: A gate structure, disposed on a surface of the semiconductor substrate, the gate structure covering a portion of the surface of the drift region and a portion of the surface of the body region; A source region of a first conductivity type, the source region and the drain region are respectively located at two sides of the gate structure, wherein the source region is located in the body region.

10. The device according to claim 8, characterized in that A buried layer of the first conductivity type is also formed below the drift region, and a first well region with the first conductivity type and a second well region with the second conductivity type are formed in the semiconductor substrate, wherein the first well region extends downward from the surface of the semiconductor substrate to connect with the buried layer, the first well region is used to lead out the buried layer, and the second well region extends downward from the surface of the semiconductor substrate to contact with the buried layer.

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