Semiconductor structure and preparation method thereof

Abstract

The embodiment of the invention discloses a semiconductor structure and a preparation method thereof, relates to the technical field of semiconductors, and can reduce the manufacturing process complexity and cost of the semiconductor structure and improve the performance of the semiconductor structure. The semiconductor structure includes a semiconductor substrate and a transistor structure. The semiconductor substrate includes a first isolation structure and a second isolation structure. The transistor structure is arranged on one side of the semiconductor substrate; the transistor structure comprises an epitaxial layer, a dielectric layer and a conductive layer. The epitaxial layers are arranged on the surface of one side of the semiconductor substrate and located between the adjacent first isolation structures and the second isolation structures and / or between every two adjacent second isolation structures. The dielectric layer is arranged on one side of the epitaxial layer away from the semiconductor substrate; the dielectric layer wraps the epitaxial layer and covers the second isolation structure. The conductive layer is arranged on the side, away from the semiconductor substrate, of the dielectric layer, covers the dielectric layer and is filled between the two adjacent epitaxial layers.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] With the technological development of the semiconductor industry, the density of semiconductor devices per unit area is getting higher and higher, and the size of semiconductor devices is shrinking. In a semiconductor structure (such as an integrated circuit) formed by multiple semiconductor elements (such as transistors), improving the ability to accurately control each semiconductor element has always been an important research direction in the industry. For example, the relative area of ​​the gate and channel region of a transistor is studied. As a result, the complexity and process cost of the structure and preparation process of the transistor are also the focus of the research process. Summary of the invention

[0003] In view of this, an embodiment of the present application provides a semiconductor structure and a method for preparing the same, which reduces the complexity and cost of the manufacturing process of the semiconductor structure and improves the performance of the semiconductor structure.

[0004] To achieve the above purpose, the technical solution of this application is implemented as follows:

[0005] In one aspect, an embodiment of the present application provides a semiconductor structure, which includes a semiconductor substrate and a transistor structure.

[0006] The semiconductor substrate includes a first isolation structure and at least one second isolation structure arranged in an area enclosed by the first isolation structure; the first isolation structure and the second isolation structure are respectively at opposite ends along a direction perpendicular to the plane where the semiconductor substrate is located, one end of which is exposed from the same side surface of the semiconductor substrate, and the other end of which is located inside the semiconductor substrate.

[0007] A transistor structure is arranged on one side of the semiconductor substrate; the transistor structure includes an epitaxial layer, a dielectric layer and a conductive layer. A plurality of epitaxial layers are arranged on a surface of one side of the semiconductor substrate, and are respectively located between adjacent first isolation structures and second isolation structures, and / or between two adjacent second isolation structures. A dielectric layer is arranged on a side of the epitaxial layer away from the semiconductor substrate; the dielectric layer covers the epitaxial layer and covers the second isolation structure. A conductive layer is arranged on a side of the dielectric layer away from the semiconductor substrate, the conductive layer covers the dielectric layer, and fills between two adjacent epitaxial layers.

[0008] In some examples, a plurality of the second isolation structures are spaced apart along the first direction. The first isolation structure surrounds the second isolation structure, and along the second direction, opposite ends of the second isolation structure are respectively connected to the first isolation structure; and the second direction intersects the first direction.

[0009] In some examples, the epitaxial layer includes a first electrode region, a second electrode region, and a channel region between the first electrode region and the second electrode region. The channel region of the epitaxial layer includes a groove, the opening of the groove faces away from the semiconductor substrate; the dielectric layer extends along the sidewall of the groove. The conductive layer covers the channel region of the epitaxial layer, and part of the conductive layer material is filled in the groove.

[0010] In some examples, the conductive layer includes a first conductive portion and a second conductive portion connected to each other. The first conductive portion extends along the arrangement direction of the plurality of epitaxial layers and covers the channel regions of the plurality of epitaxial layers. The second conductive portion is disposed on a side of the first isolation structure away from the semiconductor substrate.

[0011] In some examples, the dimension of the first isolation structure along a direction perpendicular to the plane where the semiconductor substrate is located is greater than the dimension of the second isolation structure along a direction perpendicular to the plane where the semiconductor substrate is located. One first isolation structure encloses a unit area; the semiconductor structure includes a plurality of the unit areas, and two adjacent unit areas share part of the first isolation structure.

[0012] In some examples, the semiconductor substrate includes a silicon-on-insulator layer.

[0013] In some examples, the transistor structure further includes: a first transfer structure and a second transfer structure. The first transfer structure is disposed on a side of the first electrode region of the epitaxial layer away from the semiconductor substrate and coupled to the first electrode region. The second transfer structure is disposed on a side of the second electrode region of the epitaxial layer away from the semiconductor substrate and coupled to the second electrode region.

[0014] In the semiconductor structure, an epitaxial layer is provided on one side of the semiconductor substrate, and the epitaxial layer can be used as an active layer of a transistor structure. That is to say, from the perspective of the manufacturing process of the semiconductor structure, the epitaxial layer is manufactured after the semiconductor substrate is formed, rather than using part of the semiconductor substrate material as the epitaxial layer structure during the manufacturing process of the semiconductor substrate. The manufacturing process of the epitaxial layer obtained in this way is simple and the process cost is low. In addition, the semiconductor structure may include multiple conductive layers, and one conductive layer may be electrically connected to multiple epitaxial layers. Based on the spacing area between the multiple epitaxial layers, the conductive layer may extend along the side edge of the epitaxial layer and continuously cover the multiple epitaxial layers. In this way, a part of the conductive layer is also provided on the side wall of the epitaxial layer, which is conducive to increasing the relative area between the conductive layer and an epitaxial layer, and is conducive to improving the control ability of the conductive layer as the gate of the transistor over the channel region; and based on the process of the epitaxial layer, the manufacturing process of the entire semiconductor structure (including the transistor) is simple and the process cost is low, and based on the relative position relationship and structure of each layer in the semiconductor structure, it can be integrated into the process of the current semiconductor structure manufacturing process, and has high compatibility.

[0015] On the other hand, the present application also provides a method for preparing a semiconductor structure. The preparation method includes forming a semiconductor substrate; the semiconductor substrate includes a first isolation structure and at least one second isolation structure disposed in an area surrounded by the first isolation structure; one end of the first isolation structure and the second isolation structure at opposite ends along a direction perpendicular to the plane where the semiconductor substrate is located is exposed from the same side surface of the semiconductor substrate, and the other end is located inside the semiconductor substrate.

[0016] An epitaxial layer is formed on one side of the semiconductor substrate; the epitaxial layer is located between adjacent first isolation structures and second isolation structures, and / or between two adjacent second isolation structures.

[0017] A dielectric layer is formed on a side of the epitaxial layer away from the semiconductor substrate; the dielectric layer encapsulates the epitaxial layer and covers the second isolation structure.

[0018] A conductive layer is formed on a side of the dielectric layer away from the semiconductor substrate, the conductive layer covers the dielectric layer and fills between two adjacent epitaxial layers.

[0019] In some examples, the forming of the semiconductor substrate includes: forming a first trench and at least one second trench located in an area enclosed by the first trench on an initial semiconductor substrate; the depth of the first trench is greater than the depth of the second trench; the first trench surrounds the second trench and is connected to the second trench.

[0020] A dielectric material is deposited in the first trench and the second trench to form the first isolation structure and the second isolation structure to obtain the semiconductor substrate.

[0021] In some examples, the forming of the epitaxial layer includes: forming an initial epitaxial layer; the initial epitaxial layer includes a first electrode region, a second electrode region, and a channel region between the first electrode region and the second electrode region; and forming at least one groove in the channel region.

[0022] The preparation method comprises: forming the dielectric layer extending along the inner wall of the groove, forming a channel region covering the epitaxial layer, and partially filling the conductive layer in the groove with material.

[0023] The method for preparing the semiconductor structure described above prepares a semiconductor structure as provided in any of the above examples. The technical effect achieved by the method for preparing the semiconductor structure described above is the same as the technical effect of the semiconductor structure provided in any of the above examples, which will not be repeated here. In addition, the semiconductor structure prepared by the method for preparing the semiconductor structure provided in any of the above examples, by growing an epitaxial layer on a semiconductor substrate, obtains a channel structure of a transistor (i.e., an active layer of the transistor, including a source and a drain), and sets the structural features of the relative regions of the epitaxial layer and the conductive layer (i.e., the gate of the transistor), thereby improving the control capability of the gate of the transistor over the channel region and improving the performance of the semiconductor structure. Among them, the process of growing an epitaxial layer on a semiconductor substrate can reduce the process difficulty of making the active layer of the transistor and reduce the process cost, compared with the process of increasing the trench depth in the related art, and can be integrated into the process steps of the current semiconductor structure manufacturing process, with high compatibility.

[0024] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic top view of a semiconductor structure provided in one embodiment of the present application Figure 1 ;

[0026] Figure 2 A schematic cross-sectional view along the BB direction of a semiconductor structure provided by an embodiment of the present application;

[0027] Figure 3 A schematic cross-sectional view of a semiconductor structure along the AA direction provided in one embodiment of the present application Figure 1 ;

[0028] Figure 4 A schematic top view of a semiconductor structure provided in one embodiment of the present application Figure 2 ;

[0029] Figure 5 A schematic cross-sectional view of a semiconductor structure along the AA direction provided in one embodiment of the present application Figure 2 ;

[0030] Figure 6 A schematic cross-sectional view of a semiconductor structure along the AA direction provided in one embodiment of the present application Figure 3 ;

[0031] Figure 7 A schematic diagram of a method for preparing a semiconductor structure provided in an embodiment of the present application Figure 1 ;

[0032] Figure 8 (a)~ Figure 8 (f) is a schematic structural cross-sectional diagram of a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0033] Fig. 9 A schematic diagram of a method for preparing a semiconductor structure provided in an embodiment of the present application Figure 2 . DETAILED DESCRIPTION

[0034] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0035] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0036] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0037] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0038] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0039] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0041] With the technological development of the semiconductor industry, the density of semiconductor devices per unit area is getting higher and higher, and the size of semiconductor devices is constantly shrinking. In integrated circuit (IC) devices formed by multiple semiconductor elements (such as transistors), improving the ability to accurately control each semiconductor element has always been an important research direction in the industry. For example, the semiconductor structure can be a single electronic element (such as a transistor). For example, the semiconductor structure is a transistor structure including a drain terminal, a source terminal and a gate terminal, or the semiconductor structure is a fin field effect transistor (finfield-effecttransistor, FinFET), which is a multi-gate device including two or more gates located on two or three sides of the FinFET device channel. In this way, by setting the relative area of ​​the gate and the channel, the control ability of the gate over the channel can be improved, achieving better electrostatic control characteristics, superior short channel behavior, shorter switching time and higher current density.

[0042] However, the effective width of the FinFET device in the related art is limited, so the overall performance of the semiconductor device cannot meet the future expansion requirements. In addition, the process of the FinFET in the related art is complex, which is not conducive to widespread production and has high costs.

[0043] Based on this, the embodiments of the present application provide a semiconductor structure and a method for preparing the same, which can reduce the complexity and cost of the manufacturing process, improve the control ability of the gate of the semiconductor structure over the channel, and improve the performance of the semiconductor structure.

[0044] In some embodiments, Figure 1 to Figure 6 As shown, an embodiment of the present application provides a semiconductor structure 100. For example, the semiconductor structure 100 can be a chip (Chip), a die (Die), or a wafer (Wafer). It should be noted that the chip (Chip) and the die (Die) can refer to the same structure (the names can be interchangeable), or the die can be a chip that is not packaged. Different levels of chip structures are set according to requirements. For example, the chip Chip, the die Die and the wafer Wafer are three different levels of chip structures. The embodiments provided in the present application are not limited to this, and any semiconductor structure formed with transistors can be implemented using the technology provided in the present application. Subsequent examples all use "semiconductor structure" for illustrative purposes.

[0045] In some examples, such as Figure 1 As shown, the semiconductor structure 100 includes: a semiconductor substrate 110 and a transistor structure 120. The transistor structure 120 is disposed on one side of the semiconductor substrate 110.

[0046] For example, the semiconductor substrate 110 may be a composite layer structure of a multilayer dielectric material and a conductive material including a circuit structure. For example, the semiconductor substrate 110 may include a silicon on insulator (SOI) layer.

[0047] For example, the transistor structure 120 may include a plurality of transistors. The transistor may include a field effect transistor (FET). FET includes other transistors such as a metal oxide semiconductor field effect transistor (MOSFET) and a silicon on insulator field effect transistor (SOI FET), which are not specifically shown in this application and may be set as required. For example, the semiconductor substrate 110 is made of SOI material, and the transistor structure 120 formed on the semiconductor substrate 110 may include an SOI FET transistor.

[0048] like Figure 1 As shown, the transistor structure 120 can be divided into multiple unit areas N, and multiple transistors T can be set in one unit area N. The number of transistors T in a unit area N can be adjusted under the condition that the control capability of the gate of the transistor T over the channel area is satisfied. It should be noted that the "unit area" defined in this application is not limited to a specific physical structure and can be divided according to actual conditions. This application does not impose specific restrictions. The area size of the unit area N can also be adjusted according to the size of the actual semiconductor structure 100. The area sizes of different unit areas N can be different, and the number of transistors T in different unit areas N can be different. For example, Figure 1 The number of transistors in a unit area N shown mainly reflects the influence of the gate on the control ability of the channel area from the perspective of the structural characteristics of the active layer (i.e., the epitaxial layer mentioned in the subsequent example) of the transistor T and the relative area size relationship between the channel area of ​​the active layer and the gate. The following example is exemplified by the layer structure of the semiconductor structure 100 in a unit area N.

[0049] In some examples, such as Figure 1 and Figure 2 As shown, the semiconductor substrate 110 includes a first isolation structure 111 and at least one second isolation structure 112 disposed in a region enclosed by the first isolation structure 111 (ie, in a cell region N).

[0050] For example, Figure 1As shown, a first isolation structure 111 surrounds a unit region N. The semiconductor structure 100 includes a plurality of unit regions N, and two adjacent unit regions N share a portion of the first isolation structure 111 .

[0051] The first isolation structure 111 and the second isolation structure 112 both extend in a direction perpendicular to the plane of the semiconductor substrate 110. For example, Figure 2 As shown, the dimension of the first isolation structure 111 along the direction Z perpendicular to the plane where the semiconductor substrate 110 is located is greater than the dimension of the second isolation structure 112 along the direction Z perpendicular to the plane where the semiconductor substrate 110 is located.

[0052] Continue reading Figure 2 The first isolation structure 111 and the second isolation structure 112 are respectively located at opposite ends along a direction perpendicular to the plane of the semiconductor substrate 110 , one end of which is exposed from the same side surface of the semiconductor substrate 110 , and the other end of which is located inside the semiconductor substrate 110 .

[0053] For example, the materials used for the first isolation structure 111 and the second isolation structure 112 may include oxide insulating materials.

[0054] The first isolation structure 111 may be a shallow trench isolation (STI) structure. The STI is used to separate the cell regions N where different transistors are located (see Figure 1 ). For example, multiple transistors that achieve the same functional effect can be divided into the same unit area N, and STI can reduce the interference between transistors T in different unit areas N when achieving different functions.

[0055] The second isolation structure 112 may be located in the area surrounded by the first isolation structure 111, and Figure 2 As shown, along the direction Z perpendicular to the plane where the semiconductor substrate 110 is located, the size of the second isolation structure 112 is smaller than the size of the first isolation structure 111, and the second isolation structure 112 is used to separate the active layers of different transistors in the area enclosed by the first isolation structure 111 (i.e., the epitaxial layer 121 mentioned in subsequent examples).

[0056] In some examples, such as Figure 1 As shown, a plurality of second isolation structures 112 are arranged along the first direction X at intervals.

[0057] The first isolation structure 111 surrounds the second isolation structure 112 , and along the second direction Y, opposite ends of the second isolation structure 112 are respectively connected to the first isolation structure 111 ; the second direction Y intersects the first direction X.

[0058] For example, the first isolation structure 111 is in a square ring shape, and the second isolation structure 112 is in a strip shape, connected to two opposite sides of the first isolation structure 111 .

[0059] It should be noted that the present application does not impose any specific restrictions on the number of transistors set in the same unit area, and can be set according to the actual function and structure size of the semiconductor structure. Since the number of second isolation structures 112 set is related to the number of transistors, only the structural relationship between the first isolation structure 111 and the second isolation structure 112 is exemplarily embodied here for exemplary description. For example, Figure 1 As shown, a unit area N surrounded by a first isolation structure 111 is provided with four transistors, and two second isolation structures 112 are provided to separate two adjacent transistors.

[0060] In some examples, such as Figure 1 and Figure 2 As shown, the transistor structure 120 includes an epitaxial layer 121 , a dielectric layer 122 and a conductive layer 123 .

[0061] like Figure 2 As shown, a plurality of epitaxial layers 121 are disposed on a surface of one side of the semiconductor substrate 110 , and are respectively located between adjacent first isolation structures 111 and second isolation structures 112 , and / or between two adjacent second isolation structures 112 .

[0062] For example, one epitaxial layer 121 may be located between adjacent first isolation structures 111 and second isolation structures 112. For example, a second isolation structure 112 is provided in the region enclosed by the first isolation structure 111 (i.e., in a cell region N). Thus, two epitaxial layers 121 may be provided in the region enclosed by the first isolation structure 111, and each epitaxial layer 121 is located between adjacent first isolation structures 111 and second isolation structures 112.

[0063] Alternatively, one epitaxial layer 121 may be located between two adjacent second isolation structures 112. For example, at least two second isolation structures 112 are provided in the region enclosed by the first isolation structure 111 (i.e., in one cell region N). In this way, the epitaxial layer 121 may be provided only between two adjacent second isolation structures 112 in the region enclosed by the first isolation structure 111. No epitaxial layer 121 may be provided between adjacent first isolation structures 111 and second isolation structures 112.

[0064] Or, if Figure 2As shown, part of the epitaxial layers 121 in the plurality of epitaxial layers 121 may be located between adjacent first isolation structures 111 and second isolation structures 112, and the remaining part of the epitaxial layers 121 may be located between two adjacent second isolation structures 112. For example, at least two second isolation structures 112 are provided in the region enclosed by the first isolation structure 111 (i.e., in a cell region N). In this way, a plurality of epitaxial layers 121 may be provided in the region enclosed by the first isolation structure 111, an epitaxial layer 121 is provided between two adjacent second isolation structures 112, and an epitaxial layer 121 is also provided between adjacent first isolation structures 111 and second isolation structures 112, which can increase the number of transistors in a cell region N and improve the integration density.

[0065] And, if Figure 2 As shown, the dielectric layer 122 is disposed on a side of the epitaxial layer 121 away from the semiconductor substrate 110 ; the dielectric layer 122 encapsulates the epitaxial layer 121 and covers the second isolation structure 112 .

[0066] For example, the material of the dielectric layer 122 includes one or more insulating materials such as silicon oxynitride SiON, silicon oxide SiO2, silicon nitride SiN or silicon carbide SiC. The dielectric layer 122 is used to insulate the epitaxial layer 121 from the conductive layer 123. In this way, the dielectric layer 122 covers the epitaxial layer 121 on the semiconductor substrate 110, which can prevent the epitaxial layer 121 from being directly electrically connected to the subsequently formed conductive layer 123 under the conductive state. Moreover, the dielectric layer 122 extends from the surface of the epitaxial layer 121 to the surface of the second isolation structure 112 and covers the second isolation structure 112, which can prevent the conductive particles in the conductive layer 123 from diffusing into the second isolation structure 112 after the subsequently formed conductive layer 123 contacts the second isolation structure 112, thereby improving the reliability of the conductive layer 123 subsequently formed on the dielectric layer 122.

[0067] Continue reading Figure 2 The conductive layer 123 is disposed on a side of the dielectric layer 122 away from the semiconductor substrate 110 . The conductive layer 123 covers the dielectric layer 122 and fills between two adjacent epitaxial layers 121 .

[0068] For example, the conductive layer 123 can be a gate of a transistor. The conductive layer 123 covers the dielectric layer 122, and the dielectric layer 122 serves as a gate dielectric layer between the active layer and the gate layer in the transistor structure, that is, the conductive layer does not contact the epitaxial layer 121. The conductive layer 123 is arranged to extend along the edge of the epitaxial layer 121, which can increase the relative area between the conductive layer 123 and the epitaxial layer 121, thereby improving the control capability of the conductive layer 123 over the channel region of the epitaxial layer 121.

[0069] For example, the material used for the conductive layer 123 may include one or more of a metal element or compound, a semiconductor material or a conductive polymer. For example, the material used for the conductive layer 123 may include one or more of a conductive element or compound such as gold, silver, copper, aluminum, tin, etc.

[0070] In the semiconductor structure 100, an epitaxial layer 121 is provided on one side of the semiconductor substrate 110, and the epitaxial layer 121 can be used as an active layer of a transistor structure. That is to say, from the perspective of the manufacturing process of the semiconductor structure 100, the epitaxial layer 121 is manufactured after the semiconductor substrate 110 is formed, rather than using part of the material of the semiconductor substrate 110 as the structure of the epitaxial layer 121 during the manufacturing process of the semiconductor substrate 110. The manufacturing process of the epitaxial layer 121 obtained in this way is simple and the process cost is low. In addition, the semiconductor structure 100 can include multiple conductive layers 123, and one conductive layer 123 can electrically connect multiple epitaxial layers 121. Based on the spacing area between multiple epitaxial layers 121, the conductive layer 123 can extend along the edge of the epitaxial layer 121 and continuously cover multiple epitaxial layers 121. In this way, the conductive layer 123 is also provided on the side wall of the epitaxial layer 121, which increases the relative area between the conductive layer 123 and one epitaxial layer 121, which is conducive to improving the control ability of the conductive layer 123 as the gate of the transistor over the channel region; and based on the process of the epitaxial layer 121, the manufacturing process of the entire semiconductor structure (including the transistor) is simple and the process cost is low. Moreover, based on the relative position relationship and structure of each layer in the above-mentioned semiconductor structure, it can be integrated into the process of the current semiconductor structure manufacturing process, and has high compatibility.

[0071] In some examples, such as Figure 3 to Figure 6 As shown, the epitaxial layer 121 includes a first electrode region 1211 , a second electrode region 1212 , and a channel region 1213 located between the first electrode region 1211 and the second electrode region 1212 .

[0072] like Figure 3 As shown, the transistor structure 120 further includes: a first transfer structure 1241 and a second transfer structure 1242 .

[0073] The first transfer structure 1241 is disposed on a side of the first electrode region 1211 of the epitaxial layer 121 away from the semiconductor substrate 110 , and is coupled to the first electrode region 1211 .

[0074] The second transfer structure 1242 is disposed on a side of the second electrode region 1212 of the epitaxial layer 121 away from the semiconductor substrate 110 , and is coupled to the second electrode region 1212 .

[0075] For example, the first electrode region 1211 of the epitaxial layer 121 can be used as the source of the transistor when the first transfer structure 1241 is conductive. The second electrode region 1212 of the epitaxial layer 121 can be used as the drain of the transistor when the second transfer structure 1242 is conductive. The conductive layer 123 serves as the gate of the transistor. In this way, an epitaxial layer 121, a dielectric layer 122, and a portion of the conductive layer 123 in an area opposite to the channel region 1213 of the epitaxial layer 121 can form a transistor.

[0076] The materials used for the first transfer structure 1241 and the second transfer structure 1242 may include one or more conductive single substances or compounds such as gold, silver, copper, aluminum, and tin.

[0077] In some examples, such as Figure 4 As shown, the conductive layer 123 includes a first conductive portion 1231 and a second conductive portion 1232 that are connected.

[0078] The first conductive portion 1231 extends along the arrangement direction X of the plurality of epitaxial layers 121 and covers the channel regions 1213 of the plurality of epitaxial layers 121 .

[0079] The second conductive portion 1232 is disposed on a side of the first isolation structure 111 away from the semiconductor substrate 110. The second conductive portion 1232 can be used to realize electrical connection between the plurality of first conductive portions 1231 and external electronic components. The present application does not impose any specific restrictions on the shape and extension direction of the second conductive portion 1232, as long as the second conductive portion 1232 does not overlap with the epitaxial layer 121.

[0080] In addition, if Figure 5 As shown, the transistor structure 120 also includes a transfer structure 1230 coupled to the conductive layer 123, which is used to couple the conductive layer 123 to a word line (not shown in the figure) in the semiconductor structure 100, and transmit electrical signals to the conductive layer 123 through the word line, thereby realizing the control capability of the conductive layer 123 over the channel region 1213.

[0081] In some examples, such as Figure 5 and Figure 6 As shown, the channel region 1213 of the epitaxial layer 121 includes a groove 1214 , and the opening of the groove 1214 faces the direction Z away from the semiconductor substrate 110 .

[0082] The dielectric layer 122 extends along the sidewall of the groove 1214 . The conductive layer 123 covers the channel region 1213 of the epitaxial layer 121 , and a portion of the conductive layer 123 fills the groove 1214 .

[0083] It can be understood that the depth of the groove 1214 is greater than the layer thickness of the dielectric layer 122, and after the material of the dielectric layer 122 is deposited in the groove 1214, a recessed structure can be characterized on the top surface of the dielectric layer 122, so that the conductive material can be filled in the recessed structure, and the relative area between the conductive layer 123 and the channel region 1213 is increased without increasing the spacing between the first electrode region 1211 and the second electrode region 1212 along the direction Y, which is beneficial to increase the control ability of the conductive layer 123 over the channel region 1213 when the conductive layer 123 is conductive. The present application does not impose a specific limitation on the depth of the groove 1214, and it can be adjusted according to the materials of the dielectric layer 122 and the conductive layer 123, and the thickness of the epitaxial layer 121.

[0084] For example, Figure 5 As shown, the channel region 1213 of the epitaxial layer 121 includes a groove 1214. The dielectric layer 122 extends along the inner wall of the groove 1214. The conductive layer 123 is located on the dielectric layer 122 and fills the groove 1214.

[0085] Another example, such as Figure 6 As shown, the channel region 1213 of the epitaxial layer 121 includes three grooves 1214 . The dielectric layer 122 covers the three grooves 1214 and extends continuously along the inner walls of the three grooves 1214 . The conductive layer 123 fills the three grooves 1214 .

[0086] In addition, when a plurality of grooves 1214 are provided in the channel region 1213 of the epitaxial layer 121, the plurality of grooves 1214 may be arranged in a plurality of rows along the arrangement direction Y of the first electrode region 1211 and the second electrode region 1212; or, arranged in a plurality of columns along the arrangement direction X perpendicular to the first electrode region 1211 and the second electrode region 1212; or, the plurality of grooves 1214 may be arranged in a plurality of rows and columns. The examples provided in the present application do not impose specific limitations on this.

[0087] The number of the above-mentioned grooves 1214 , the sizes of different grooves 1214 , and the arrangement of the multiple grooves 1214 in the channel region 1213 can be set according to actual conditions, as long as the material of the dielectric layer 122 and the material of the conductive layer 123 can be filled in the grooves 1214 .

[0088] It should be noted that the examples provided in this application do not impose specific restrictions on the specific layer structure and internal conductive signal lines of the semiconductor structure 1000, and can be set according to actual needs. The following example uses the structure of the epitaxial layer 121 and the structure in the semiconductor structure 100 that affects the control ability of the conductive layer 123 on the channel region 1213 of the epitaxial layer 121 to exemplarily illustrate the preparation process of the semiconductor structure.

[0089] In the process of manufacturing the semiconductor structure 100, in order to reduce the process complexity and cost of the semiconductor structure 100 while forming a transistor having a better control capability of the conductive layer 123 over the channel region 1213 of the epitaxial layer 121, as shown in FIG. Figure 7 to Figure 9 As shown, the embodiment of the present application provides a method S100 to S400 for preparing a semiconductor structure 100 , and the process of this preparation method is more compatible with the process of the semiconductor structure manufacturing method in the related art.

[0090] S100: Figure 7 ,and Figure 8 (a) and Figure 8 As shown in (b) of FIG. 1 , a semiconductor substrate 110 is formed. The semiconductor substrate 110 includes a first isolation structure 111 and at least one second isolation structure 112 disposed in a region surrounded by the first isolation structure 111. Figure 2 As shown, one end of the first isolation structure 111 and the second isolation structure 112 at opposite ends along a direction Z perpendicular to the plane of the semiconductor substrate 110 is exposed from the same side surface of the semiconductor substrate 110 , and the other end is located inside the semiconductor substrate 110 .

[0091] S200: Figure 7 and Figure 8 As shown in (c) of FIG. 1 , an epitaxial layer 121 is formed on one side of the semiconductor substrate 110 . The epitaxial layer 121 is located between adjacent first isolation structures 111 and second isolation structures 112 , and / or between two adjacent second isolation structures 112 .

[0092] For example, the semiconductor substrate 110 is made of silicon or SOI material, and a semiconductor material can be grown between the first isolation structure 111 and the second isolation structure 112, and / or in a region between two adjacent second isolation structures 112, and ion doping is performed to obtain an epitaxial layer 121. The epitaxial layer 121 can be used as an active layer of a transistor.

[0093] It can be understood that a first isolation structure 111 and a second isolation structure 112 are arranged on the semiconductor substrate 110, and the materials of the first isolation structure 111 and the second isolation structure 112 include dielectric materials. In this way, based on the material properties of the first isolation structure 111 and the second isolation structure 112 and the relative positional relationship between the two, semiconductor materials can be grown on the top surface of the semiconductor substrate 110 and in the area where the top surfaces of the first isolation structure 111 and the second isolation structure 112 are not exposed. The quality of the obtained epitaxial layer 121 is high and will not be formed on the top surface of the first isolation structure 111 or the second isolation structure 112; moreover, the manufacturing process of the epitaxial layer 121 is simple.

[0094] S300: Figure 7 and Figure 8 As shown in (d) , a dielectric layer 122 is formed on a side of the epitaxial layer 121 away from the semiconductor substrate 110 ; the dielectric layer 122 covers the epitaxial layer 121 and covers the second isolation structure 112 .

[0095] For example, a deposition process is used to deposit a dielectric material on a side of the epitaxial layer 121 away from the semiconductor substrate 110 .

[0096] S400: Figure 7 and Figure 8 As shown in (e) , a conductive layer 123 is formed on a side of the dielectric layer 122 away from the semiconductor substrate 110 . The conductive layer 123 covers the dielectric layer 122 and fills between two adjacent epitaxial layers 121 .

[0097] For example, a deposition process may be used to deposit a conductive material on a side of the dielectric layer 122 away from the semiconductor substrate 110. The material used for the conductive layer 123 includes one or more of a metal element, a semiconductor material, or a conductive polymer. For example, the material used for the conductive layer 123 may include one or more of conductive elements or compounds such as gold, silver, copper, aluminum, and tin.

[0098] In the process of manufacturing the semiconductor structure 100, after forming the semiconductor substrate 110, the epitaxial layer 121 is manufactured. The semiconductor substrate 110 has a first isolation structure 111 and a second isolation structure 112. By growing the epitaxial layer 121 on the semiconductor substrate 110, the channel structure of the transistor (i.e., the active layer of the transistor, including the source and the drain) is obtained, and the structural features of the relative regions of the epitaxial layer 121 and the conductive layer 123 (i.e., the gate of the transistor) are set, so as to improve the control capability of the gate of the transistor over the channel region and improve the performance of the semiconductor structure 100. Compared with the related art method of increasing the trench depth, the process means of growing the epitaxial layer 121 on the semiconductor substrate 110 can reduce the process difficulty of manufacturing the active layer of the transistor, improve the structural yield of the transistor, reduce the process cost, and can be integrated into the current process of manufacturing the semiconductor structure, with high compatibility.

[0099] In some examples, such as Figure 8 (a) and Figure 8 (b) in the above, and Fig. 9 As shown, the above step S100: forming a semiconductor substrate 110 includes S110.

[0100] S110: forming a first trench 1101 and at least one second trench 1102 in the area surrounded by the first trench 1101 on the initial semiconductor substrate 110'. The depth of the first trench 1101 is greater than the depth of the second trench 1102; the first trench 1101 surrounds the second trench 1102 and is connected to the second trench 1102.

[0101] For example, a dry etching or wet etching process may be used to etch the initial semiconductor substrate 110 ′ to form the first trench 1101 . Then, etching is performed again in the area surrounded by the first trench 1101 to form the second trench 1102 .

[0102] S120 : depositing a dielectric material in the first trench 1101 and the second trench 1102 to form a first isolation structure 111 and a second isolation structure 112 , thereby obtaining a semiconductor substrate 110 .

[0103] For example, a chemical vapor deposition (CVD) or spin-on process may be used to fill a dielectric material with a low dielectric constant in the first trench 1101 and the second trench 1102. The dielectric material may include one or more insulating materials such as silicon oxynitride SiON, silicon oxide SiO2, silicon nitride SiN, or silicon carbide SiC.

[0104] For example, by using a spin coating process, dielectric material can be filled into the first trench 1101 and the second trench 1102 in one process, which is beneficial to improving process efficiency. One side surface of the first isolation structure 111 and the second isolation structure 112 formed in this way is flush with one side surface of the semiconductor substrate 110.

[0105] For another example, by using CVD to fill the dielectric material in the first trench 1101 and the second trench 1102, the filling amount of the dielectric material in different trenches can be controlled. For example, after the dielectric material is deposited in the first trench 1101, the surface of one side of the formed first isolation structure 111 is flush with the surface of one side of the semiconductor substrate 110. After the dielectric material is deposited in the second trench, the surface of one side of the formed second isolation structure 112 is lower than the surface of one side of the semiconductor substrate 110. In this way, the side area of ​​the epitaxial layer 121 formed subsequently is increased, which is conducive to increasing the area of ​​the channel region 1213 of the epitaxial layer 121 surrounded by the conductive layer 123 on three sides, and increasing the control ability of the conductive layer 123 over the channel region 1213.

[0106] In some examples, such as Figure 8 (c) and Fig. 9 As shown, the above step S200: forming an epitaxial layer includes S210 and S220.

[0107] S210: forming an initial epitaxial layer (i.e., the epitaxial layer in the channel region 1213 that has not been patterned). Figure 3 As shown, the initial epitaxial layer includes a first electrode region 1211 , a second electrode region 1212 , and a channel region 1213 located between the first electrode region 1211 and the second electrode region 1212 .

[0108] S220: Figure 5 and Figure 6 As shown, at least one groove 1214 is formed in the channel region 1213 .

[0109] For example, a photolithography process may be used to form at least one groove 1214 in the channel region 1213 of the epitaxial layer 121 .

[0110] For example, the opening sizes of different grooves 1214 in one channel region 1213 may be different. For example, the minimum size of the opening of the groove 1214 is related to the material of the dielectric layer 122 and the material of the conductive layer 123, and it is sufficient that after the dielectric layer 122 is deposited on the inner wall of the groove 1214, the recessed structure represented on the top surface of the dielectric layer 122 can be filled or filled with the material of the conductive layer 123, so that the conductive layer 123 has good conductive properties.

[0111] For example, the shapes of the openings of different grooves 1214 may also be different. For example, the shapes of the openings of the grooves 1214 may include one or more of polygons such as a circle, a square, and a triangle.

[0112] For example, the arrangement of the plurality of grooves 1214 may also be set according to actual needs. For example, the plurality of grooves 1214 may be arranged in a plurality of rows along the arrangement direction Y of the first electrode region 1211 and the second electrode region 1212; or, may be arranged in a plurality of columns along the arrangement direction X perpendicular to the first electrode region 1211 and the second electrode region 1212; or, the plurality of grooves 1214 may be arranged in a plurality of rows and columns. The examples provided in this application do not impose specific limitations on this.

[0113] And, if Fig. 9 As shown, in the preparation method, the above step S300 includes S310, and the above step S400 includes S410.

[0114] S310: Figure 5 and Figure 6 As shown, a dielectric layer 122 is formed to extend along the inner wall of the groove 1214 .

[0115] For example, considering that the area of ​​the channel region 1213 of the epitaxial layer 121 is small and the size of the groove 1214 formed in the channel region 1213 is small, the process parameters for depositing the dielectric layer 122 can be set so that the material of the dielectric layer 122 can be deposited on the inner wall of the groove and extend along the inner wall of the groove 1214 to form a recessed structure on the top surface of the dielectric layer 122.

[0116] S410: Figure 5 and Figure 6 As shown, a channel region 1213 is formed covering the epitaxial layer 121 , and a portion of the material of the conductive layer 123 is filled in the groove 1214 .

[0117] For example, a deposition process is used to form a conductive layer 123 on a side of the dielectric layer 122 away from the semiconductor substrate 110, that is, the conductive layer 123 does not contact the layers on the side of the dielectric layer 122 close to the semiconductor substrate 110. Since the dielectric layer 122 at least covers the channel region 1213 of the epitaxial layer 121, the conductive layer 123 can be insulated from the epitaxial layer 121. After the dielectric layer 122 extends along the inner wall of the groove 1214, the conductive material is deposited in a concave structure on the top surface of the dielectric layer 122, so that the conductive layer 123 can extend along the side of the dielectric layer 122 or the epitaxial layer 121 (such as Figure 2 As shown in the figure, the epitaxial layer 122 is surrounded on three sides, the relative area of ​​the conductive layer 123 and the channel region 1213 of the epitaxial layer 121 is increased, and the control ability of the conductive layer 123 over the channel region 1213 of the epitaxial layer 121 is improved.

[0118] In addition, if Figure 8 As shown in (f), the preparation method also includes: forming a first transition structure 1241 and a second transition structure 1242.

[0119] For example, Figure 8 As shown in (f), an insulating layer 125 is formed on the side of the conductive layer 123 away from the semiconductor substrate 110, and the insulating layer 125 covers multiple epitaxial layers 121 (including the dielectric layer 122 and the top surface of the semiconductor substrate 110). A plurality of through holes are formed on the insulating layer, and the plurality of through holes can be filled with conductive materials. Part of the through holes can expose the first electrode region 1211 of the epitaxial layer 121 to form a first transfer structure 1241; part of the through holes can expose the second electrode region 1212 of the epitaxial layer 121 to form a second transfer structure 1242; part of the through holes can expose the portion of the conductive layer 123 located on the first isolation structure 111 to form a transfer structure 1230 electrically connected to the conductive layer 123.

[0120] The first transfer structure 1241 and the second transfer structure 1242 are also used to couple with different conductive signal lines (not shown in the figure) in the semiconductor structure 100. For example, in the case where the stacked structure of the epitaxial layer 121, the dielectric layer 122 and the conductive layer 123 forms a transistor, under the control of the electrical signal transmitted by the conductive layer 123 (coupled with the transfer structure 1230), the electrical signal transmitted by the conductive signal line coupled to the first transfer structure 1241 can be transmitted to the conductive signal line coupled to the second transfer structure 1242, thereby realizing the function of the transistor.

[0121] It should be noted that the embodiments of the semiconductor structure provided in the present application and the embodiments of the method for manufacturing the semiconductor structure belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict. However, it should be further noted that the combination of the various technical features of the semiconductor structure provided in the embodiments of the present application can already solve the technical problem to be solved by the present application; therefore, the method for manufacturing the semiconductor structure provided in the embodiments of the present application may not be limited by the semiconductor structure provided in the embodiments of the present application, and any semiconductor structure prepared by the method for manufacturing the semiconductor structure provided in the embodiments of the present application is within the scope of protection of the present application.

[0122] The above is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A semiconductor structure, characterized in that: include: A semiconductor substrate, comprising a first isolation structure and at least one second isolation structure disposed in a region enclosed by the first isolation structure; The first isolation structure and the second isolation structure have two opposite ends along a direction perpendicular to the plane where the semiconductor substrate is located, one end of each of which is exposed from the same side surface of the semiconductor substrate, and the other end of each of which is located inside the semiconductor substrate; A transistor structure, disposed on one side of the semiconductor substrate; The transistor structure comprises: A plurality of epitaxial layers are disposed on a surface of one side of the semiconductor substrate and are respectively located between adjacent first isolation structures and second isolation structures and / or between two adjacent second isolation structures; A dielectric layer is disposed on a side of the epitaxial layer away from the semiconductor substrate; the dielectric layer covers the epitaxial layer and covers the second isolation structure; The conductive layer is arranged on a side of the dielectric layer away from the semiconductor substrate, the conductive layer covers the dielectric layer, and is filled between two adjacent epitaxial layers.

2. The semiconductor structure according to claim 1, characterized in that: A plurality of the second isolation structures are arranged at intervals along the first direction; The first isolation structure surrounds the second isolation structure, and along a second direction, opposite ends of the second isolation structure are respectively connected to the first isolation structure; the second direction intersects the first direction.

3. The semiconductor structure according to claim 1, characterized in that: The epitaxial layer includes a first electrode region, a second electrode region, and a channel region located between the first electrode region and the second electrode region; The channel region of the epitaxial layer includes a groove, and the opening of the groove faces a direction away from the semiconductor substrate; The dielectric layer extends along the sidewall of the groove; The conductive layer covers the channel region of the epitaxial layer, and part of the material of the conductive layer is filled in the groove.

4. The semiconductor structure according to claim 1, characterized in that: The conductive layer includes a first conductive portion and a second conductive portion connected; The first conductive portion extends along an arrangement direction of the plurality of epitaxial layers and covers channel regions of the plurality of epitaxial layers; The second conductive portion is disposed on a side of the first isolation structure away from the semiconductor substrate.

5. The semiconductor structure according to claim 1, characterized in that: The dimension of the first isolation structure along a direction perpendicular to the plane where the semiconductor substrate is located is greater than the dimension of the second isolation structure along a direction perpendicular to the plane where the semiconductor substrate is located; One of the first isolation structures encloses a unit area; the semiconductor structure includes a plurality of the unit areas, and two adjacent unit areas share part of the first isolation structure.

6. The semiconductor structure according to claim 1, characterized in that The semiconductor substrate includes a silicon-on-insulator layer.

7. The semiconductor structure according to claim 3, characterized in that: The transistor structure further comprises: A first transfer structure is disposed on a side of the first electrode region of the epitaxial layer away from the semiconductor substrate and is coupled to the first electrode region; The second transfer structure is disposed on a side of the second electrode region of the epitaxial layer away from the semiconductor substrate and is coupled to the second electrode region.

8. A method for preparing a semiconductor structure, characterized in that: include: forming a semiconductor substrate; The semiconductor substrate comprises a first isolation structure and at least one second isolation structure disposed in a region enclosed by the first isolation structure; One end of the first isolation structure and the second isolation structure at opposite ends along a direction perpendicular to the plane where the semiconductor substrate is located is exposed from the same side surface of the semiconductor substrate, and the other end is located inside the semiconductor substrate; forming an epitaxial layer on one side of the semiconductor substrate; The epitaxial layer is located between adjacent first isolation structures and second isolation structures, and / or between two adjacent second isolation structures; forming a dielectric layer on a side of the epitaxial layer away from the semiconductor substrate; The dielectric layer covers the epitaxial layer and covers the second isolation structure; A conductive layer is formed on a side of the dielectric layer away from the semiconductor substrate, the conductive layer covers the dielectric layer and fills between two adjacent epitaxial layers.

9. The preparation method according to claim 8, characterized in that: The forming of the semiconductor substrate comprises: Forming a first trench and at least one second trench located in an area surrounded by the first trench on an initial semiconductor substrate; the depth of the first trench is greater than the depth of the second trench; the first trench surrounds the second trench and is connected to the second trench; A dielectric material is deposited in the first trench and the second trench to form the first isolation structure and the second isolation structure to obtain the semiconductor substrate.

10. The preparation method according to claim 8, characterized in that: The forming of the epitaxial layer comprises: forming an initial epitaxial layer; the initial epitaxial layer comprising a first electrode region, a second electrode region and a channel region located between the first electrode region and the second electrode region; forming at least one groove in the channel region; The preparation method comprises: forming the dielectric layer extending along the inner wall of the groove; A channel region covering the epitaxial layer is formed, and a portion of the material is filled in the conductive layer in the groove.

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