A MOSFET device and its fabrication method, and a pixel circuit.

Abstract

This invention discloses a MOSFET device and its fabrication method, as well as a pixel circuit. The MOSFET device includes: a substrate; a well region with a first doping type formed on the substrate; the well region including an active region and trench structures disposed on opposite sides of the active region; a gate structure disposed above the active region; the active region including a lightly doped drain region and a lightly doped source region with a second doping type disposed on opposite sides of the gate structure; the lightly doped drain region having a heavily doped drain region with a second doping type; the lightly doped source region having a heavily doped source region with a second doping type; a first side of the heavily doped region being flush with the trench structure, and a gap forming between the second side of the heavily doped region and the gate structure; a depletion injection region with a first doping type disposed within the gap; the first side of the depletion injection region being flush with the second side of the heavily doped region; and a gap also forming between the second side of the depletion injection region and the gate structure. The technical solution provided by this invention can reduce the leakage current of the MOSFET device.

Description

Technical Field

[0001] This invention relates to the field of metal-oxide-semiconductor field-effect transistor technology, and more particularly to a MOSFET device and its fabrication method, and a pixel circuit. Background Technology

[0002] The pixel circuit design of Mini-LED or Micro-OLED display panels used in the micro-display field requires the use of medium-voltage MOS devices with ultra-low leakage current, because excessive leakage current of medium-voltage MOS devices can easily lead to abnormal bright and dark spot phenomena in Micro-OLED display panels.

[0003] Therefore, developing medium-voltage MOS devices with ultra-low leakage current performance has become a core issue, and reducing the leakage current performance of medium-voltage MOS devices involves optimizing the design of their drain electric field distribution. The peak drain electric field of conventional medium-voltage MOS devices is often located in the gate / drain overlap region, close to the channel surface. This peak electric field location is detrimental to reducing the leakage current of medium-voltage devices. Therefore, a new source-drain structure needs to be designed to improve the electric field distribution in the gate / drain overlap region as much as possible, dispersing the electric field accumulated here towards the substrate and reducing the peak electric field at this location. Summary of the Invention

[0004] This invention provides a MOSFET device and its fabrication method, as well as a pixel circuit, to reduce the leakage current of the MOSFET device.

[0005] In a first aspect, embodiments of the present invention provide a MOSFET device, comprising: a substrate;

[0006] The substrate forms a well region having a first doping type; the well region includes an active region and trench structures disposed on opposite sides of the active region; a gate structure is disposed above the active region;

[0007] The active region includes a lightly doped drain region and a lightly doped source region having a second doping type disposed on opposite sides of the gate structure; the lightly doped drain region is provided with a heavily doped drain region having a second doping type; the lightly doped source region is provided with a heavily doped source region having a second doping type.

[0008] The first side of the heavily doped drain region is flush with the trench structure, and the second side of the heavily doped drain region forms a first gap with the gate structure; a drain depletion injection region with a first doping type is disposed in the first gap; the first side of the drain depletion injection region is flush with the second side of the heavily doped drain region; a second gap is formed between the second side of the drain depletion injection region and the gate structure.

[0009] The first side of the heavily doped source region is flush with the trench structure, and the second side of the heavily doped source region forms a third gap with the gate structure; a source depletion injection region with a first doping type is disposed in the third gap; the first side of the source depletion injection region is flush with the second side of the heavily doped source region; a fourth gap is formed between the second side of the source depletion injection region and the gate structure.

[0010] Secondly, embodiments of the present invention provide a method for fabricating a MOSFET device, used to form the MOSFET device provided in any embodiment of the present invention, comprising:

[0011] Provide substrate;

[0012] The substrate is ion implanted to form a well region with a first doping type; the well region includes an active region and trench structures disposed on opposite sides of the active region;

[0013] Ion implantation is performed on the active region to form a lightly doped drain region and a lightly doped source region having a second doping type;

[0014] A gate structure is formed above the active region; the lightly doped drain region and the lightly doped source region are respectively disposed on opposite sides of the gate structure;

[0015] A heavily doped drain region is formed in the lightly doped drain region by ion implantation; a heavily doped source region is formed in the lightly doped source region by ion implantation; a first side of the heavily doped drain region is flush with the trench structure, and a first gap is formed between the second side of the heavily doped drain region and the gate structure; a first side of the heavily doped source region is flush with the trench structure, and a third gap is formed between the second side of the heavily doped source region and the gate structure.

[0016] A drain depletion implantation region with a first doping type is formed within the first gap by ion implantation; the first side of the drain depletion implantation region is flush with the second side of the heavily doped drain region; a second gap is formed between the second side of the drain depletion implantation region and the gate structure; a source depletion implantation region with a first doping type is formed within the third gap by ion implantation; the first side of the source depletion implantation region is flush with the second side of the heavily doped source region; a fourth gap is formed between the second side of the source depletion implantation region and the gate structure.

[0017] Thirdly, embodiments of the present invention also provide a pixel circuit, including: a MOSFET device provided in any embodiment of the present invention.

[0018] In this invention, the MOSFET device sequentially includes a substrate and a gate structure above the substrate. The substrate includes a well region of a first doping type, the well region comprising an active region and trench structures disposed on opposite sides of the active region. The gate structure is disposed above the active region. The active region includes a lightly doped drain region and a lightly doped source region of a second doping type on opposite sides of the gate structure. The lightly doped drain region is provided with a heavily doped drain region having a second doping type, and the lightly doped source region is provided with a heavily doped source region having a second doping type. It should be noted that the first side of the heavily doped drain region is flush with the trench structure, and the second side of the heavily doped drain region forms a first gap with the gate structure. A drain depletion implantation region having a first doping type is provided within the first gap. The first side of the drain depletion implantation region is flush with the second side of the heavily doped drain region. A second gap is formed between the second side of the drain depletion implantation region and the gate structure. The first side of the heavily doped source region is flush with the trench structure, and the second side of the heavily doped source region forms a third gap with the gate structure. A source depletion implantation region having a first doping type is provided within the third gap. The first side of the source depletion implantation region is flush with the second side of the heavily doped source region. A fourth gap is formed between the second side of the source depletion implantation region and the gate structure. In this embodiment, a gap is formed between the heavily doped region and the gate structure, and a depletion injection region is formed within the gap, namely, a drain depletion injection region and a source depletion injection region. The drain depletion injection region completely depletes the lightly doped drain region surrounding it and close to the channel, leaving no free electrons. Similarly, the source depletion injection region between the heavily doped source region and the gate structure completely depletes the lightly doped source region surrounding it and close to the channel, leaving no free electrons. This results in a more uniform electric field distribution in the overlapping region between the gate structure and the lightly doped drain region, and shifts the peak electric field of the medium-voltage device as far towards the substrate as possible, improving the leakage current performance of the MOSFET device. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of a MOSFET device provided in an embodiment of the present invention;

[0020] Figure 2 A comparative example structural schematic diagram of a MOSFET device provided in an embodiment of the present invention;

[0021] Figure 3 for Figure 2 A schematic diagram of the electric field distribution of a comparative example of a MOSFET device;

[0022] Figure 4 This is a schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0023] Figure 5 This is a schematic flowchart illustrating a method for fabricating a MOSFET device according to an embodiment of the present invention.

[0024] Figure 6 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0025] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0026] Figure 1 This is a schematic diagram of the structure of a MOSFET device provided in an embodiment of the present invention, as shown below. Figure 1 As shown, an embodiment of the present invention provides a MOSFET device, including: a substrate 11;

[0027] The substrate 11 forms a well region 12 having a first doping type; the well region 12 includes an active region 121 and trench structures 17 disposed on opposite sides of the active region 121; a gate structure 13 is disposed above the active region 121.

[0028] The active region 121 includes a lightly doped drain region 122 and a lightly doped source region 123 with a second doping type disposed on opposite sides of the gate structure 13; the lightly doped drain region 122 is provided with a heavily doped drain region 124 with a second doping type; the lightly doped source region 123 is provided with a heavily doped source region 125 with a second doping type.

[0029] The first side of the heavily doped drain region 124 is flush with the trench structure 17, and the second side of the heavily doped drain region 124 forms a first gap with the gate structure 13; a drain depletion injection region 126 with a first doping type is disposed in the first gap; the first side of the drain depletion injection region 126 is flush with the second side of the heavily doped drain region 124; a second gap is formed between the second side of the drain depletion injection region 126 and the gate structure 13.

[0030] The first side of the heavily doped source region 125 is flush with the trench structure 17, and the second side of the heavily doped source region 125 forms a third gap with the gate structure 13; a source depletion injection region 127 with a first doping type is disposed in the third gap; the first side of the source depletion injection region 127 is flush with the second side of the heavily doped source region 125; a fourth gap is formed between the second side of the source depletion injection region 127 and the gate structure 13.

[0031] In this invention, the MOSFET device sequentially includes a substrate and a gate structure above the substrate. The substrate includes a well region of a first doping type, the well region comprising an active region and trench structures disposed on opposite sides of the active region. The gate structure is disposed above the active region. The active region includes a lightly doped drain region and a lightly doped source region of a second doping type on opposite sides of the gate structure. The lightly doped drain region is provided with a heavily doped drain region having a second doping type, and the lightly doped source region is provided with a heavily doped source region having a second doping type. It should be noted that the first side of the heavily doped drain region is flush with the trench structure, and the second side of the heavily doped drain region forms a first gap with the gate structure. A drain depletion implantation region having a first doping type is provided within the first gap. The first side of the drain depletion implantation region is flush with the second side of the heavily doped drain region. A second gap is formed between the second side of the drain depletion implantation region and the gate structure. The first side of the heavily doped source region is flush with the trench structure, and the second side of the heavily doped source region forms a third gap with the gate structure. A source depletion implantation region having a first doping type is provided within the third gap. The first side of the source depletion implantation region is flush with the second side of the heavily doped source region. A fourth gap is formed between the second side of the source depletion implantation region and the gate structure. In this embodiment, a gap is formed between the heavily doped region and the gate structure, and a depletion injection region is formed within the gap, namely, a drain depletion injection region and a source depletion injection region. The drain depletion injection region completely depletes the lightly doped drain region surrounding it and close to the channel, leaving no free electrons. Similarly, the source depletion injection region between the heavily doped source region and the gate structure completely depletes the lightly doped source region surrounding it and close to the channel, leaving no free electrons. This results in a more uniform electric field distribution in the overlapping region between the gate structure and the lightly doped drain region, and shifts the peak electric field of the medium-voltage device as far towards the substrate as possible, improving the leakage current performance of the MOSFET device.

[0032] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0033] like Figure 1As shown, the MOSFET device includes a substrate 11, which is a silicon substrate. In other embodiments, it can also be a substrate made of other suitable materials. A well region 12 can be formed on the substrate 11. Specifically, a well region 12 with a first doping type can be formed on the substrate 11 by ion implantation. The first doping type can be P-type or N-type. Then, a trench structure 17 can be formed by trenching or etching on the well region 12. The well region 12 can include an active region 121 with the first doping type and trench structures 17 on opposite sides of the active region 121. When multiple MOSFET devices are disposed on the same substrate 11, the trench structure 17 is used to isolate the active regions 121 of different MOSFET devices. A gate structure 13 is formed on the active region 121, that is, the gate structure 13 is disposed above the active region 121 away from the substrate 11. Optionally, the gate structure 13 can include a gate dielectric layer 131 and a gate layer 132 disposed sequentially away from the substrate 11. It should be noted that in this embodiment, "the gate structure 13 is located above the active region 121" means that a gate structure 13 is set close to the surface of the active region 121. In addition, "above" in other positions in this embodiment specifically refers to setting a new film layer on the surface of the current film layer, rather than at a high or low position of the current film layer.

[0034] A lightly doped drain region 122 and a lightly doped source region 123 of the second doping type are formed within the active region 121. The lightly doped drain region 122 and the lightly doped source region 123 are respectively disposed on opposite sides of the gate structure 13 in a plane parallel to the substrate 11. When forming the lightly doped drain region 122, the process of forming the lightly doped drain region 122 and the lightly doped source region 123 can employ processes such as spin coating. Photoresist is formed above the active region 121 away from the substrate 11. Then, a photomask is used to expose the photoresist. After exposure, a corresponding developer is used to develop the photoresist to remove the photoresist located on the lightly doped drain region 122 and the lightly doped source region 123, thereby exposing the lightly doped drain region 122 and the lightly doped source region 123. Ion implantation is then used to dope the lightly doped drain region 122 and the lightly doped source region 123 to form a P-type lightly doped drain region or an N-type lightly doped drain region. Other areas are not doped due to the obstruction of the photoresist.

[0035] It should be noted that if well region 12 is a P-type well region, then the doping type of the lightly doped drain region 122 and the lightly doped source region 123 is N-type; if well region 12 is an N-type well region, then the doping type of the lightly doped drain region 122 and the lightly doped source region 123 is P-type. Based on this, the lightly doped drain region 122 is provided with a heavily doped drain region 124 having a second doping type, and the lightly doped source region 123 is provided with a heavily doped source region 125 having a second doping type. The doping concentration of the heavily doped drain region 124 is greater than that of the lightly doped drain region 122, and the doping concentration of the heavily doped source region 125 is greater than that of the lightly doped source region 123. After a gate voltage is applied to the gate structure 13, a lateral channel parallel to the substrate 11 is formed between the heavily doped drain region 124 and the heavily doped source region 125, enabling the MOSFET device to conduct.

[0036] The lightly doped drain region 122 is further provided with a drain depletion injection region 126 having a first doping type; the drain depletion injection region 126 is disposed between the heavily doped drain region 124 and the gate structure 13; the lightly doped source region 123 is further provided with a source depletion injection region 127 having a first doping type; the source depletion injection region 127 is disposed between the heavily doped source region 125 and the gate structure 13. It should be noted that there is a gap between the heavily doped drain region 124 and the gate structure 13, which can be referred to as the first gap in this embodiment. The first gap is also provided with a drain depletion injection region 126. Similarly, the third gap between the heavily doped source region 125 and the gate structure 13 is also provided with a source depletion injection region 127. Both the drain depletion injection region 126 and the source depletion injection region 127 are of the first doping type. It should be noted that after the drain depletion injection region 126 and the source depletion injection region 127 are formed, there is a second gap between the drain depletion injection region 126 and the gate structure 13, and there is a fourth gap between the source depletion injection region 127 and the gate structure 13. When the MOSFET device is in the off state, the carriers in the lateral channel between the heavily doped drain region 124 and the heavily doped source region 125 can be consumed by the drain depletion injection region 126 and the source depletion injection region 127, which have the opposite doping type to the heavily doped drain region 124 and the heavily doped source region 125. The depletion injection region can completely deplete the lightly doped drain region surrounding it and close to the channel, so that the free carriers in the lightly doped drain region 122 and the lightly doped source region 123 are completely depleted, making the electric field distribution in the overlapping area between the gate structure and the lightly doped drain region more uniform, and making the peak electric field of the medium voltage device move as far towards the substrate as possible, thus improving the leakage current performance of the MOSFET device.

[0037] Continue to refer to Figure 1Optionally, the MOSFET device may further include: a sidewall 18; the sidewall 18 being disposed on opposite sides of a second gap and a fourth gap; the first side of the sidewall 18 of the second gap being flush with the second side of the drain depletion injection region 126; the first side of the sidewall 18 of the fourth gap being flush with the second side of the source depletion injection region 127; in a plane parallel to the substrate 11, the sidewall 18 does not overlap with the drain depletion injection region 126 and the source depletion injection region 127. In a plane parallel to the substrate 11, the lightly doped drain region 122 overlaps with the gate structure 13; the lightly doped source region 123 overlaps with the gate structure 13, facilitating the formation of a conduction channel between the lightly doped drain region 122 and the lightly doped source region 123 under the control of the gate structure 13. In this embodiment, the sidewall 18 may be disposed around the gate structure 13. Optionally, the sidewall 18 may be fabricated using a dry etching process and may be made of silicon dioxide, which also provides good isolation. In this embodiment, the sidewall 18 is beneficial for further reducing leakage current and parasitic capacitance in small-sized MOSFET devices. Furthermore, when forming the drain depletion injection region 126 and the source depletion injection region 127 through a doping process, the sidewall 18 and the gate structure 13 can be used as masks for fabrication, so there is no overlap between the sidewall 18 and the drain depletion injection region 126 and the source depletion injection region 127.

[0038] Figure 2 This is a structural schematic diagram of a comparative example of a MOSFET device provided in an embodiment of the present invention. Figure 3 for Figure 2 A schematic diagram of the electric field distribution of a comparative example of a MOSFET device. The MOSFET device includes a substrate 11', a well region 12' formed on the substrate 11', and a gate structure 13'. The well region 12' includes an active region 121' and trench structures 17' on opposite sides of the active region 121'. The active regions 121' on opposite sides of the gate structure 13' are provided with lightly doped drain regions 122' and lightly doped source regions 123' having a second doping type. The gate structure 13' is provided with heavily doped drain regions 124' and heavily doped source regions 125' on opposite sides. However, no drain depletion injection regions and source depletion injection regions are provided, and both the heavily doped drain regions 124' and heavily doped source regions 125' extend to be flush with the sidewalls 18', that is, no gap is provided between the heavily doped drain regions 124' and the sidewalls 18', nor is a gap provided between the heavily doped source regions 125' and the sidewalls 18'. However, as... Figure 3 As shown, Figure 2 In ultra-low leakage medium-voltage devices, the peak electric field is often located in the overlapping region between the gate and drain, and close to the channel surface. Figure 3The horizontal axis represents the horizontal position, and the vertical axis represents the vertical position. In the electric field distribution diagram, lighter gray colors represent larger energy values, and darker gray colors represent smaller energy values. Figure 3 The peak electric field is located in the overlap region A1 between the gate and drain. This peak electric field location is detrimental to reducing the two main leakage currents that constitute the leakage current of medium-voltage devices: junction leakage at the drain-to-lightly doped drain region 122' and gate-induced leakage (GIDL leakage). Therefore, it is necessary to improve the electric field distribution in the gate / drain overlap region as much as possible. Figure 1 The MOSFET device provided in this embodiment shown in the figure has a gap between the heavily doped drain region 124 and the sidewall 18 to arrange the drain depletion injection region 126, and a gap between the heavily doped source region 125 and the sidewall 18 to arrange the source depletion injection region 127. The drain depletion injection region 126 and the source depletion injection region 127 enable the electric field accumulated on the surface to be dispersed to the substrate as much as possible, so that the peak electric field located therein decreases.

[0039] Continue to refer to Figure 1 Optionally, the MOSFET device may further include: a drain metal silicide 15, a gate metal silicide 14, and a source metal silicide 16; the gate metal silicide 14 is disposed above the gate structure 13; the drain metal silicide 15 is disposed above the heavily doped drain region 124 and the partial drain depletion injection region 126; the source metal silicide 16 is disposed above the heavily doped source region 125 and the partial source depletion injection region 127. A gap exists between the drain metal silicide 15 and the sidewall 18; a gap also exists between the source metal silicide 16 and the sidewall 18. The drain metal silicide 15, the gate metal silicide 14, and the source metal silicide 16 can be metal layers, used for electrical connection with light-emitting elements or other MOSFET devices on the display panel to realize the signal transmission function of the MOSFET device. Because there is a gap between the drain metal silicide 15 and the sidewall 18, and a gap between the source metal silicide 16 and the sidewall 18, the gaps increase the extended resistance of the drain of the MOSFET device. This can improve the electric field distribution gradient in the overlapping area between the gate and the drain, especially near the contact surface between the active region 121 and the gate structure 13, and reduce the maximum electric field at that location, thereby reducing the leakage current.

[0040] As described above, the first doping type can be P-type or N-type. When the first doping type is P-type, the MOSFET device is an N-type device; when the first doping type is N-type, the MOSFET device is a P-type device. This embodiment will first use an N-type device as an example. Optionally, the first doping type can be P-type; the second doping type can be N-type.

[0041] Optionally, the well region 12 can be formed by first ion implantation; the implantation energy of the first ion is in the range of 100 KeV to 400 KeV; the implantation dose of the first ion is in the range of 2E13 atom / cm 2 ~6E13atom / cm 2 The first ion is a p-type doped ion such as boron; both the lightly doped drain region 122 and the lightly doped source region 123 are formed by implantation of the second ion; the implantation energy range of the second ion is 50 KeV to 300 KeV; the implantation dose range of the second ion is 1 E12 atom / cm 2 ~8E12atom / cm 2 The second ion is an N-type doped ion such as phosphorus; both the heavily doped drain region 124 and the heavily doped source region 125 are formed by implantation of the third ion; the implantation energy range of the third ion is 10 KeV to 50 KeV; the implantation dose range of the third ion is 2E14 atom / cm 2 ~2E15atom / cm 2 The third ion is an N-type doped ion such as phosphorus.

[0042] When doping different parts of the active region using ion implantation, the well region 12 is P-type doped, and P-type dopant ions such as boron can be used for ion implantation, as boron ions themselves have strong diffusion properties. The lightly doped drain region 122 and the lightly doped source region 123 are N-type doped, and both can be implanted using N-type dopant ions such as phosphorus. The heavily doped drain region 124 and the heavily doped source region 125 are N-type doped, and N-type dopant ions such as phosphorus are used for ion implantation. Compared to the implantation energy range of 50 KeV to 300 KeV for the lightly doped drain region 122, the implantation energy range of the heavily doped drain region 124 is 10 KeV to 50 KeV. The heavily doped drain region 124 has a lower implantation energy but a higher implantation dose, resulting in a film with a higher concentration but a lower film thickness. In other words, the heavily doped drain region 124 exhibits a more severe doping effect than the lightly doped drain region 122. Similarly, the heavily doped source region 125 has a heavier doping effect than the lightly doped source region 123, thereby forming a conductive connection between the heavily doped drain region 124 and the heavily doped source region 125.

[0043] Optionally, both the drain depletion implantation region 126 and the source depletion implantation region 127 can be formed by fourth ion implantation; the implantation energy range of the fourth ion is 5 KeV to 10 KeV; the implantation dose range of the fourth ion is 1 E13 atom / cm 2 ~1E14atom / cm 2 The fourth ion is a p-type doped ion such as boron difluoride.

[0044] In this embodiment, the drain depletion implantation region 126 and the source depletion implantation region 127 can be ion-doped with boron fluoride ions with weak diffusion, thereby forming a stable medium-voltage N-type well region and improving the reliability of the final semiconductor structure. Furthermore, the drain depletion implantation region 126 and the source depletion implantation region 127 have a relatively large dose but a low implantation energy. After sequentially forming the well region 12, the lightly doped drain region 122, and the lightly doped source region 123, a P-type IMP with very low energy but a large dose is applied, forming the drain depletion implantation region 126 and the source depletion implantation region 127. This P-type IMP completely depletes the lightly doped drain region 122 and the lightly doped source region 123 surrounding it and close to the channel. Since there are no free electrons in the completely depleted regions of the lightly doped drain region 122 and the lightly doped source region 123, the electric field distribution in the gate / drain overlap region is more uniform, and the peak electric field is shifted as far towards the substrate as possible while controlling the width of the depletion region. This is beneficial for improving leakage current performance and also for improving the hot carrier effect performance of the MOSFET device.

[0045] In this embodiment, the MOSFET device can also be a P-type device. Optionally, the first doping type can be N-type, and the second doping type can be P-type. In this case, the doping situation of each part of the active region of the P-type device is different from that of each part of the active region of the N-type device.

[0046] Optionally, the well region 12 can be formed by fifth ion implantation; the implantation energy of the fifth ion is in the range of 200 KeV to 800 KeV; the implantation dose of the fifth ion is in the range of 2E13 atom / cm 2 ~6E13atom / cm 2 The fifth ion is an N-type doped ion such as phosphorus; both the lightly doped drain region 122 and the lightly doped source region 123 are formed by implantation of the sixth ion; the implantation energy range of the sixth ion is 40 KeV to 200 KeV; the implantation dose range of the sixth ion is 1 E12 atom / cm 2 ~8E12atom / cm 2 The sixth ion is a p-type doped ion such as boron; both the heavily doped drain region 124 and the heavily doped source region 125 are formed by implantation of the seventh ion; the implantation energy range of the seventh ion is 5 KeV to 30 KeV; the implantation dose range of the seventh ion is 2E14 atom / cm 2 ~2E15atom / cm 2 The seventh ion is a p-type doped ion such as boron.

[0047] When doping the active region 121 using ion implantation, the well region 12 is N-type doped, and N-type dopant ions such as phosphorus can be used for ion implantation. The lightly doped drain region 122 and the lightly doped source region 123 are P-type doped, and both can be ion implanted using P-type dopant ions such as boron. The heavily doped drain region 124 and the heavily doped source region 125 are also P-type doped, and boron is used for ion implantation. Compared to the implantation energy range of 40 KeV to 200 KeV for the lightly doped drain region 122, the implantation energy range of the heavily doped drain region 124 is 5 KeV to 30 KeV. The implantation energy of the heavily doped drain region 124 is lower, but the implantation dose is higher. Therefore, the heavily doped drain region 124 forms a film with a higher concentration but a lower film thickness. That is, the heavily doped drain region 124 forms a heavier doping effect than the lightly doped drain region 122. Similarly, the heavily doped source region 125 has a heavier doping effect than the lightly doped source region 123, thereby forming a conductive connection between the heavily doped drain region 124 and the heavily doped source region 125.

[0048] Optionally, both the drain depletion implantation region 126 and the source depletion implantation region 127 can be formed by eighth ion implantation; the implantation energy range of the eighth ion is 5 KeV to 20 KeV; the implantation dose range of the eighth ion is 1E13 atom / cm 2 ~1E14atom / cm 2 The eighth ion is an N-type doped ion such as arsenic.

[0049] In this embodiment, the drain depletion injection region 126 and the source depletion injection region 127 are doped with arsenic ions. The injection dose of the drain depletion injection region 126 and the source depletion injection region 127 is relatively large, but the injection energy is low. After sequentially forming the well region 12, the lightly doped drain region 122, and the lightly doped source region 123, a very low-energy but high-dose N-type IMP is applied, forming the drain depletion injection region 126 and the source depletion injection region 127. This N-type IMP completely depletes the lightly doped drain region 122 and the lightly doped source region 123 surrounding it and close to the channel. Since there are no free holes in the completely depleted regions of the lightly doped drain region 122 and the lightly doped source region 123, the electric field distribution in the gate / drain overlap region is more uniform. Furthermore, while controlling the width of the depletion region, the peak electric field is shifted as far towards the substrate as possible. This is beneficial for improving leakage current performance and also for improving the hot carrier effect performance of the MOSFET device.

[0050] Figure 4This is a schematic diagram of another MOSFET device provided in an embodiment of the present invention. Optionally, there can be multiple MOSFET devices. A trench structure 17 is provided between the active regions 121 of two adjacent MOSFET devices. The trench structure 17 is filled with an isolation material. Figure 4 Taking two MOSFET devices as an example, a trench structure 17 is provided between the active regions 121 of two adjacent MOSFET devices, isolating the different active regions 121. This avoids mutual interference of free carriers within the active regions 121 of adjacent MOSFET devices, especially when N-type and P-type MOSFET devices are simultaneously disposed on the same silicon substrate. In this embodiment, the trench structure 17 effectively isolates the N-type and P-type MOSFET devices, improving the reliability of the MOSFET devices. The trench structure 17 is filled with an isolation material, which can be a material such as silicon oxide that can achieve electrical isolation.

[0051] Based on the same concept, embodiments of the present invention also provide a method for fabricating a MOSFET device. Figure 5 This is a schematic flowchart of a method for fabricating a MOSFET device according to an embodiment of the present invention, as shown below. Figure 5 As shown, the method in this embodiment includes the following steps:

[0052] Step S110: Provide a substrate.

[0053] Step S120: Ion implantation is performed on the substrate to form a well region with a first doping type; the well region includes an active region and trench structures disposed on opposite sides of the active region.

[0054] Step S130: Ion implantation is performed on the active region to form a lightly doped drain region and a lightly doped source region with a second doping type.

[0055] Step S140: A gate structure is formed above the active region; a lightly doped drain region and a lightly doped source region are respectively disposed on opposite sides of the gate structure.

[0056] Step S150: A heavily doped drain region is formed in the lightly doped drain region by ion implantation; a heavily doped source region is formed in the lightly doped source region by ion implantation; the first side of the heavily doped drain region is flush with the trench structure, and the second side of the heavily doped drain region forms a first gap with the gate structure; the first side of the heavily doped source region is flush with the trench structure, and the second side of the heavily doped source region forms a third gap with the gate structure.

[0057] Step S160: A drain depletion implantation region with a first doping type is formed in the first gap by ion implantation; the first side of the drain depletion implantation region is flush with the second side of the heavily doped drain region; a second gap is formed between the second side of the drain depletion implantation region and the gate structure; a source depletion implantation region with a first doping type is formed in the third gap by ion implantation; the first side of the source depletion implantation region is flush with the second side of the heavily doped source region; a fourth gap is formed between the second side of the source depletion implantation region and the gate structure.

[0058] After forming the lightly doped drain and source regions, sidewalls can be formed on opposite sides of the gate structure. Then, using the gate structure and sidewalls as masks, a drain depletion implantation region is formed in the lightly doped drain region by ion implantation, and a source depletion implantation region is formed in the lightly doped source region by ion implantation. This doping process eliminates the need for photoresist coating and exposure, saving a coating step, reducing process time, improving process efficiency, and lowering process costs.

[0059] It should be noted that after forming the lightly doped drain region and lightly doped source region in step S140, step S150 can be performed first to form the heavily doped drain region and heavily doped source region, followed by step S160 to form the drain depletion implantation region and source depletion implantation region; alternatively, step S160 can be performed first to form the drain depletion implantation region and source depletion implantation region, followed by step S150 to form the heavily doped drain region and heavily doped source region. This embodiment does not impose any special restrictions on the execution order of steps S150 and S160.

[0060] In this invention, the MOSFET device sequentially includes a substrate and a gate structure above the substrate. The substrate includes a well region of a first doping type, the well region comprising an active region and trench structures disposed on opposite sides of the active region. The gate structure is disposed above the active region. The active region includes a lightly doped drain region and a lightly doped source region of a second doping type on opposite sides of the gate structure. The lightly doped drain region is provided with a heavily doped drain region having a second doping type, and the lightly doped source region is provided with a heavily doped source region having a second doping type. It should be noted that the first side of the heavily doped drain region is flush with the trench structure, and the second side of the heavily doped drain region forms a first gap with the gate structure. A drain depletion implantation region having a first doping type is provided within the first gap. The first side of the drain depletion implantation region is flush with the second side of the heavily doped drain region. A second gap is formed between the second side of the drain depletion implantation region and the gate structure. The first side of the heavily doped source region is flush with the trench structure, and the second side of the heavily doped source region forms a third gap with the gate structure. A source depletion implantation region having a first doping type is provided within the third gap. The first side of the source depletion implantation region is flush with the second side of the heavily doped source region. A fourth gap is formed between the second side of the source depletion implantation region and the gate structure. In this embodiment, a gap is formed between the heavily doped region and the gate structure, and a depletion injection region is formed within the gap, namely, a drain depletion injection region and a source depletion injection region. The drain depletion injection region completely depletes the lightly doped drain region surrounding it and close to the channel, leaving no free electrons. Similarly, the source depletion injection region between the heavily doped source region and the gate structure completely depletes the lightly doped source region surrounding it and close to the channel, leaving no free electrons. This results in a more uniform electric field distribution in the overlapping region between the gate structure and the lightly doped drain region, and shifts the peak electric field of the medium-voltage device as far towards the substrate as possible, improving the leakage current performance of the MOSFET device.

[0061] Based on the above embodiments, optionally, after forming the gate structure above the active region, the method may further include: forming sidewalls in the second gap and the fourth gap on opposite sides of the gate structure; the first side of the sidewall of the second gap is flush with the second side of the drain depletion implantation region; the first side of the sidewall of the fourth gap is flush with the second side of the source depletion implantation region; in a plane parallel to the substrate, the sidewalls overlap with the lightly doped drain region and the lightly doped source region; forming a drain depletion implantation region of the first doping type in the first gap by ion implantation; forming a source depletion implantation region of the first doping type in the third gap by ion implantation, including: using the gate structure and the sidewalls as masks, forming a drain depletion implantation region of the first doping type in the lightly doped drain region by ion implantation, and forming a source depletion implantation region of the first doping type in the lightly doped source region by ion implantation. In this embodiment, when preparing the drain depletion implantation region and the source depletion implantation region, the gate structure and the sidewalls are also used as masks to dope the lightly doped drain region and the lightly doped source region. This eliminates the need for photoresist coating and exposure etching, saving a coating step, reducing process time, and improving process efficiency. In summary, this embodiment saves one process step in fabricating the lightly doped drain and source regions, and another process step in fabricating the drain depletion injection and source depletion injection regions, thus improving the fabrication efficiency of the MOSFET device.

[0062] This invention also provides a pixel circuit. Figure 6 A schematic diagram of a pixel circuit provided in an embodiment of the present invention is shown below. Figure 6 As shown, the pixel circuit 100 provided in this embodiment of the invention includes the MOSFET device 200 provided in any embodiment of the invention. The pixel circuit 100 can be used to drive light-emitting devices 300 such as LED chips, Mini-LEDs, or Micro-OLEDs for image display. Optionally, in this embodiment, the light-emitting device driven by the MOSFET device 22 can be a micro-OLED or other micro-devices that are smaller in size, have a faster response speed, higher luminous efficiency, stronger stability, and longer lifespan, thereby improving the abnormal bright and dark spot phenomena of Mini-LEDs or Micro-OLED micro-display devices.

[0063] The pixel circuit provided in the embodiments of the present invention includes the technical features of the MOSFET device provided in any embodiment of the present invention, and has the beneficial effects of the corresponding technical features, which will not be repeated here.

[0064] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A MOSFET device, characterized by, Comprising: a substrate; the substrate forms a well region having a first doping type; the well region includes an active region and a trench structure disposed on opposite sides of the active region; a gate structure disposed above the active region; the active region includes a lightly-doped drain region and a lightly-doped source region having a second doping type disposed on opposite sides of the gate structure; the lightly-doped drain region is disposed with a heavily-doped drain region having the second doping type; the lightly-doped source region is disposed with a heavily-doped source region having the second doping type; a first side of the heavily-doped drain region is flush with the trench structure, a second side of the heavily-doped drain region forms a first gap with the gate structure; the first gap is disposed with a drain depletion implant region having the first doping type; a first side of the drain depletion implant region is flush with the second side of the heavily-doped drain region; a second side of the drain depletion implant region forms a second gap with the gate structure; a first side of the heavily-doped source region is flush with the trench structure, a second side of the heavily-doped source region forms a third gap with the gate structure; the third gap is disposed with a source depletion implant region having the first doping type; a first side of the source depletion implant region is flush with the second side of the heavily-doped source region; a second side of the source depletion implant region forms a fourth gap with the gate structure.

2. The MOSFET device of claim 1, wherein, Further comprising: a sidewall; the sidewall is disposed in the second gap and the fourth gap on opposite sides of the gate structure; a first side of the sidewall in the second gap is flush with the second side of the drain depletion implant region; a first side of the sidewall in the fourth gap is flush with the second side of the source depletion implant region; in a plane parallel to the substrate, the lightly-doped drain region overlaps the gate structure; the lightly-doped source region overlaps the gate structure.

3. The MOSFET device of claim 2, wherein, Further comprising: a drain metal silicide, a gate metal silicide, and a source metal silicide; the gate metal silicide is disposed above the gate structure; the drain metal silicide is disposed above the heavily-doped drain region and a portion of the drain depletion implant region; the source metal silicide is disposed above the heavily-doped source region and a portion of the source depletion implant region; a gap exists between the drain metal silicide and the sidewall; a gap exists between the source metal silicide and the sidewall.

4. The MOSFET device of claim 1, wherein, the first doping type is P-type; the second doping type is N-type.

5. The MOSFET device of claim 4, wherein, The trap region is formed by first ion implantation; the implantation energy of the first ion ranges from 100 Kev to 400 Kev; the implantation dose of the first ion ranges from 2E13 atom / cm 2 to 6E13 atom / cm 2 ; the first ion is P-type doping ion; The lightly doped drain region and the lightly doped source region are formed by second ion implantation; the implantation energy of the second ion ranges from 50Kev to 300Kev; the implantation dose of the second ion ranges from 1E12atom / cm 2 to 8E12atom / cm 2 ; the second ion is N-type doping ion; The heavy doped drain region and the heavy doped source region are formed by third ion implantation; the implantation energy of the third ion ranges from 10Kev to 50Kev; the implantation dose of the third ion ranges from 2E14atom / cm 2 to 2E15atom / cm 2 ; the third ion is N-type doping ion.

6. The MOSFET device of claim 4, wherein, The drain depletion implant region and the source depletion implant region are both formed by a fourth ion implantation; the fourth ion implantation has an energy range of 5Kev-10Kev; the fourth ion implantation has a dose range of 1E13atom / cm 2 -1E14atom / cm 2 The fourth ion is a P-type doping ion.

7. The MOSFET device of claim 1, wherein, the first doping type is N-type; the second doping type is P-type.

8. The MOSFET device of claim 7, wherein, The trap region is formed by fifth ion implantation; the implantation energy of the fifth ion ranges from 200Kev to 800Kev; the implantation dose of the fifth ion ranges from 2E13atom / cm 2 to 6E13atom / cm 2 The fifth ion is N-type doping ion. The lightly doped drain region and the lightly doped source region are formed by implanting sixth ions; the implantation energy of the sixth ions ranges from 40Kev to 200Kev; the implantation dose of the sixth ions ranges from 1E12atom / cm 2 to 8E12atom / cm 2 ; the sixth ions are P-type doping ions; The heavy doped drain region and the heavy doped source region are formed by seventh ion implantation; the implantation energy of the seventh ion ranges from 5Kev to 30Kev; the implantation dose of the seventh ion ranges from 2E14atom / cm 2 to 2E15atom / cm 2 The seventh ion is P type doping ion.

9. The MOSFET device of claim 7, wherein, The drain depletion implant region and the source depletion implant region are both formed by an eighth ion implantation; the implantation energy of the eighth ion ranges from 5Kev to 20Kev; the implantation dose of the eighth ion ranges from 1E13atom / cm 2 to 1E14atom / cm 2 ; and the eighth ion is an N-type doping ion.

10. The MOSFET device of claim 1, wherein, the number of MOSFET devices is a plurality; a trench structure is disposed between active regions of adjacent two MOSFET devices; the trench structure is filled with an isolation material.

11. A method of fabricating a MOSFET device, characterized by, For forming the MOSFET device of any one of claims 1-10, comprising: providing a substrate; ion implanting the substrate to form a well region having a first doping type; the well region includes an active region and a trench structure disposed on opposite sides of the active region; ion implanting the active region to form a lightly-doped drain region and a lightly-doped source region having a second doping type; forming a gate structure above the active region; the lightly-doped drain region and the lightly-doped source region are disposed on opposite sides of the gate structure, respectively; forming a heavily-doped drain region in the lightly-doped drain region by ion implantation; forming a heavily-doped source region in the lightly-doped source region by ion implantation; a first side of the heavily-doped drain region is flush with the trench structure, and a second side of the heavily-doped drain region forms a first gap with the gate structure; a first side of the heavily-doped source region is flush with the trench structure, and a second side of the heavily-doped source region forms a third gap with the gate structure; forming a drain depletion implant region having a first doping type in the first gap by ion implantation; a first side of the drain depletion implant region is flush with the second side of the heavily-doped drain region; a second side of the drain depletion implant region forms a second gap with the gate structure; forming a source depletion implant region having the first doping type in the third gap by ion implantation; a first side of the source depletion implant region is flush with the second side of the heavily-doped source region; a second side of the source depletion implant region forms a fourth gap with the gate structure.

12. The method of claim 11, wherein the step of forming the trench gate further comprises the step of: forming a gate oxide layer on the surface of the substrate. after forming the gate structure above the active region, further comprising: forming a sidewall in the second gap and the fourth gap on opposite sides of the gate structure; a first side of the sidewall in the second gap is flush with the second side of the drain depletion implant region; a first side of the sidewall in the fourth gap is flush with the second side of the source depletion implant region; the sidewall overlaps the lightly-doped drain region and the lightly-doped source region in a plane parallel to the substrate; forming a drain depletion implant region having a first doping type in the first gap by ion implantation; forming a source depletion implant region having the first doping type in the third gap by ion implantation, comprising: forming a drain depletion implant region having a first doping type in the lightly-doped drain region by ion implantation and forming a source depletion implant region having the first doping type in the lightly-doped source region by ion implantation, using the gate structure and the sidewall as a mask.

13. A pixel circuit, characterized in that, comprising: a MOSFET device as claimed in any one of claims 1 to 10.

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