Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: forming a first doping layer in a substrate of a long channel device region, and enabling the first doping layer to have doping ions; forming a first sacrificial layer in the substrate in the short-channel device region, wherein the top surface of the first sacrificial layer is flush with the top surface of the first doping layer; a laminated structure covering the first doping layer and the first sacrificial layer is formed above the substrate, the laminated structure comprises one or more channel laminated layers which are sequentially stacked in the longitudinal direction, and each channel laminated layer comprises a second sacrificial layer and a channel layer located on the second sacrificial layer; forming a gate structure crossing the laminated structure on the substrate, wherein the gate structure covers part of the top and part of the side wall of the laminated structure; after the gate structure is formed, the first sacrificial layer is removed, and a first groove defined by the bottom of the laminated structure, the side wall of the first doping layer and the top of the substrate of the short-channel device region is formed; and forming a first insulating layer in the first groove. And the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor transistors are moving towards higher component density and higher integration, and semiconductor process nodes are continuously decreasing in accordance with Moore's Law. Transistors, as the most basic semiconductor transistors, are currently being widely used. Therefore, with the increase in component density and integration of semiconductor transistors, in order to adapt to the reduction of process nodes, the channel length of transistors must be continuously shortened.

[0003] In order to better adapt to the requirement of proportional reduction of transistor size, semiconductor processes have gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as fin field effect transistors (FinFETs) and gate-all-around (GAA) transistors. Among them, gate-all-around transistors include vertical gate-all-around transistors and horizontal gate-all-around transistors. In a gate-all-around transistor, the gate surrounds the area where the channel is located from all sides. Compared with planar transistors, the gate of a gate-all-around transistor has a stronger control ability over the channel and can better suppress the short channel effect.

[0004] Currently, the performance of gate-all-around (GAA) transistors still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to further improve the performance of the semiconductor structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, including a short channel device region and a long channel device region adjacent thereto; a first doped layer, located in the substrate in the long channel device region, and the top surface of the first doped layer is flush with the top surface of the substrate; a first insulating layer, located in the substrate in the short channel device region, and the top surface of the first insulating layer is flush with the top surface of the first doped layer; a channel structure layer, suspended on the substrate, and the channel structure comprises one or more channel layers spaced apart in the longitudinal direction; a device gate structure, located on the substrate and spanning the channel structure layer; source and drain doped layers, located in the channel structure layer on both sides of the device gate structure, and the source and drain doped layers cover the top surface of the first doped layer and the top surface of the first insulating layer.

[0007] Optionally, the doping ions in the first doping layer include one or more of P ions, As ions and B ions.

[0008] Optionally, the material of the first insulating layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

[0009] Optionally, along the normal direction of the substrate surface, the thickness of the first insulating layer is 10 nanometers to 30 nanometers.

[0010] Optionally, the semiconductor structure further includes: a protection layer located between the bottom of the device gate structure and the top of the first doping layer, and between the bottom of the device gate structure and the top of the first insulating layer.

[0011] Optionally, the device gate structure includes a gate dielectric layer surrounding and covering the channel layer, and a gate electrode layer covering the gate dielectric layer; the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0012] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a short channel device region and a long channel device region adjacent thereto; forming a first doped layer in the substrate in the long channel device region, wherein the top surface of the first doped layer is flush with the top surface of the substrate; forming a first sacrificial layer in the substrate in the short channel device region, wherein the top surface of the first sacrificial layer is flush with the top surface of the first doped layer; forming a stacked structure covering the first doped layer and the first sacrificial layer above the substrate, the stacked structure comprising one or more channel stacks stacked in sequence in the longitudinal direction, the channel stack comprising a second sacrificial layer and a channel layer located on the second sacrificial layer; forming a first sacrificial layer on the substrate; A gate structure is formed across the stacked structure, the gate structure covers part of the top and part of the sidewalls of the stacked structure; after the gate structure is formed, the first sacrificial layer is removed to form a first groove surrounded by the bottom of the stacked structure, the sidewalls of the first doped layer, and the top of the substrate in the short channel device area; a first insulating layer is formed in the first groove; after the first insulating layer is formed, a second groove located in the long channel device area is formed in the stacked structure on both sides of the gate structure, and a second groove located in the short channel device area is formed, the second groove exposes the stacked structure; a source-drain doped layer is formed in the second groove, the source-drain doped layer covers the top surface of the first doped layer and the top surface of the first insulating layer.

[0013] Optionally, the step of forming a first doping layer includes: forming a first mask layer on the top of the substrate of the short channel device area, the first mask layer exposing the top surface of the substrate of the long channel device area; performing doping treatment on the substrate of the long channel device area to form an ion doping layer in the substrate of the long channel device area, the ion doping layer is used as the first doping layer; and removing the first mask layer.

[0014] Optionally, the process of performing doping treatment on the substrate of the long channel device region includes an ion implantation process.

[0015] Optionally, the parameters of the ion implantation process include: the implanted ions include one or more of P ions, As ions and B ions.

[0016] Optionally, after forming the first doping layer, a first sacrificial layer is formed.

[0017] Optionally, the step of forming a first sacrificial layer includes: forming a second mask layer on the top of the substrate in the long channel device area, the second mask layer exposing the top surface of the substrate in the short channel device area; using the second mask layer as a mask to remove a portion of the thickness of the substrate in the short channel device area; forming a first sacrificial material layer on the top surface of the substrate in the short channel device area; using the top surface of the substrate in the long channel device area as a stop position, flattening the first sacrificial material layer and the second mask layer that are higher than the top surface of the substrate in the long channel device area, and using the remaining first sacrificial material layer as the first sacrificial layer.

[0018] Optionally, the material of the first sacrificial layer includes Si 1-x Ge x , wherein X represents the content of Ge element in SiGe, and the range of X is 40% to 60%.

[0019] Optionally, along the normal direction of the substrate surface, the thickness of the first sacrificial layer is 10 nanometers to 30 nanometers.

[0020] Optionally, after forming the first sacrificial layer and the first doped layer and before forming the stacked structure, the method for forming the semiconductor structure also includes: forming a protective layer on top of the first sacrificial layer and the first doped layer; in the step of removing the first sacrificial layer, there is an etching selectivity ratio between the first sacrificial layer and the protective layer; in the step of forming the second groove, it also includes removing the protective layer on both sides of the gate structure.

[0021] Optionally, the material of the protective layer includes silicon.

[0022] Optionally, along the normal direction of the substrate surface, the thickness of the protective layer is 1 nanometer to 5 nanometers.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0024] An embodiment of the present invention provides a method for forming a semiconductor structure, wherein a first sacrificial layer is formed in a substrate in a short channel device region, wherein the top surface of the first sacrificial layer is flush with the top surface of the first doped layer, and a stacked structure covering the first doped layer and the first sacrificial layer is formed above the substrate, wherein the stacked structure includes one or more channel stacks stacked in sequence in a longitudinal direction, wherein the channel stack includes a second sacrificial layer and a channel layer located on the second sacrificial layer, and a gate structure spanning the stacked structure is formed on the substrate, wherein the gate structure covers a portion of the top and a portion of the sidewalls of the stacked structure, and after the gate structure is formed, the first sacrificial layer is removed to form a first groove surrounded by the bottom of the stacked structure, the sidewalls of the first doped layer, and the top of the substrate in the short channel device region, and a first insulating layer is formed in the first groove. Compared with the existing solution of forming a sacrificial layer in the substrate of the long channel device region and the short channel device region and then removing the sacrificial layer to form an insulating layer, the embodiment of the present invention omits the steps of forming a first sacrificial layer in the long channel device region and then removing the first sacrificial layer to form a first insulating layer, thereby avoiding the probability of sacrificial layer residue in the long channel device region, and thus reducing the probability of generating a parasitic transistor in the long channel device region, which will affect the threshold voltage and increase the parasitic resistance and capacitance. At the same time, by forming the first insulating layer in the short channel device region, the risk of leakage through the substrate between adjacent source and drain doping layers in the short channel device region and between subsequently formed device gate structures can also be reduced, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 to Figure 2 is a structural schematic diagram corresponding to a method for forming a semiconductor structure;

[0026] Figure 3 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0027] Figures 4 to 20 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0028] The performance of the current semiconductor structure needs to be improved. The reasons why the performance needs to be improved are analyzed in combination with a method for forming a semiconductor structure.

[0029] Figure 1 to Figure 2 The present invention is a structural schematic diagram corresponding to a method for forming a semiconductor structure.

[0030] refer to Figure 1A substrate 11 is provided, the substrate 11 includes a short channel device region 10A and a long channel device region 10B adjacent thereto, a first sacrificial layer 12 is formed on the top of the substrate 11, a stacked structure 20 is formed on the top of the first sacrificial layer 12, the stacked structure 20 includes one or more channel stacks 16 stacked in sequence in a longitudinal direction, the channel stack 16 includes a second sacrificial layer 13 and a channel layer 15 located on the second sacrificial layer 13, and a gate structure (not shown) is formed on the substrate 11 to cross the stacked structure 20

[0031] refer to Figure 2 , remove the first sacrificial layer 12.

[0032] Research has found that the channel length L of the long channel device area 10B is relatively long. In the process of removing the first sacrificial layer 12, due to the limitation of the etching efficiency of the raw materials used in the etching process, the first sacrificial layer 12 in the long channel device area 10B cannot be completely removed, which increases the probability of the first sacrificial layer 12 remaining on the top surface of the substrate 11, and increases the probability of generating a parasitic transistor in the long channel device area 10B. The parasitic transistor will affect the threshold voltage and increase the parasitic resistance and capacitance, thereby affecting the performance of the semiconductor structure.

[0033] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a short channel device region and a long channel device region adjacent thereto; forming a first doped layer in the substrate in the long channel device region, and the top surface of the first doped layer is flush with the top surface of the substrate; forming a first sacrificial layer in the substrate in the short channel device region, and the top surface of the first sacrificial layer is flush with the top surface of the first doped layer; forming a stacked structure covering the first doped layer and the first sacrificial layer above the substrate, the stacked structure comprising one or more channel stacks stacked in sequence in the longitudinal direction, the channel stack comprising a second sacrificial layer and a channel layer located on the second sacrificial layer. ; forming a gate structure across the stacked structure on the substrate, the gate structure covering part of the top and part of the sidewalls of the stacked structure; after forming the gate structure, removing the first sacrificial layer to form a first groove surrounded by the bottom of the stacked structure, the sidewalls of the first doped layer, and the top of the substrate in the short channel device area; forming a first insulating layer in the first groove; after forming the first insulating layer, forming a second groove in the long channel device area in the stacked structure on both sides of the gate structure, and forming a second groove in the short channel device area, the second groove exposing the stacked structure; forming a source-drain doped layer in the second groove, the source-drain doped layer covering the top surface of the first doped layer and the top surface of the first insulating layer.

[0034] The embodiment of the present invention omits the steps of forming a first sacrificial layer in the long channel device region and then removing the first sacrificial layer to form a first insulating layer, thereby avoiding the probability of sacrificial layer residue in the long channel device region, and reducing the probability of generating parasitic transistors in the long channel device region. The parasitic transistors will affect the threshold voltage and increase the parasitic resistance and capacitance. At the same time, by forming the first insulating layer in the short channel device region, the risk of leakage through the substrate between adjacent source and drain doping layers in the short channel device region and between subsequently formed device gate structures can also be reduced, thereby improving the performance of the semiconductor structure.

[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] Figure 3 It is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0037] The semiconductor structure includes: a substrate (not marked), including a short channel device region 200A and a long channel device region 200B adjacent thereto; a first doped layer 203, located in the substrate of the long channel device region 200B, and the top surface of the first doped layer 203 is flush with the top surface of the substrate; a first insulating layer 228, located in the substrate of the short channel device region 200A, and the top surface of the first insulating layer 228 is flush with the top surface of the first doped layer 203; a channel structure layer 298, suspended on the substrate, and the channel structure layer 298 includes one or more channel layers 221 spaced apart in the longitudinal direction; a device gate structure 226, located on the substrate and spanning the channel structure layer 298; a source-drain doped layer 232, located in the channel structure layer 298 on both sides of the device gate structure 226, and the source-drain doped layer 232 covers the top surface of the first doped layer 203 and the top surface of the first insulating layer 228.

[0038] It should be noted that, in the process of forming the semiconductor structure, the present embodiment omits the steps of forming a first sacrificial layer in the long channel device area 200B and then removing the first sacrificial layer to form a first insulating layer 228, thereby avoiding the probability of the first sacrificial layer remaining in the long channel device area 200B, and thus reducing the probability of generating a parasitic transistor in the long channel device area 200B, which will affect the threshold voltage and increase the parasitic resistance and capacitance. At the same time, by forming the first insulating layer 228 in the short channel device area 200A, the risk of leakage through the substrate between adjacent source and drain doping layers 232 of the short channel device area 200A and between the device gate structures 226 can also be reduced, thereby improving the performance of the semiconductor structure.

[0039] The substrate is used to provide a process platform for setting up gate-all-around (GAA) transistors.

[0040] In this embodiment, the substrate is a three-dimensional substrate, and the substrate includes a substrate 200 and a protruding portion 201 protruding from the substrate 200 .

[0041] In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0042] The protrusion 201 exposes a portion of the substrate 200 , thereby providing a process basis for the subsequent formation of an isolation layer.

[0043] In this embodiment, the material of the protrusion 201 is the same as that of the substrate 200, and the material of the protrusion 201 is silicon. In other embodiments, the material of the protrusion may also be a semiconductor material suitable for forming a fin, such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the protrusion may also be different from that of the substrate.

[0044] The first doped layer 203 is used as a well region of the long channel device region 200B, so that the threshold voltage of the transistor can be adjusted and some common problems in semiconductor structures, such as latch-up effect and other reliability problems, can be solved.

[0045] As an example, when the semiconductor structure is PMOS, the doping ions in the first doping layer 203 are one or both of P and As, and when the semiconductor structure is NMOS, the doping ions in the first doping layer 203 are B.

[0046] In this embodiment, the short channel device region 200A refers to a device region with a short conductive channel, and the long channel device region 200B refers to a region with a long conductive channel.

[0047] Specifically, since the conductive channel of the long channel device area 200B is longer, the probability of leakage between adjacent devices through the substrate is very small. In the formation process of the semiconductor structure, the steps of forming a first sacrificial layer in the long channel device area 200B and then removing the first sacrificial layer to form a first insulating layer 228 are omitted, thereby avoiding the probability of the first sacrificial layer remaining in the long channel device area 200B.

[0048] In this embodiment, the semiconductor structure further includes: a protection layer 216 located between the bottom of the device gate structure 226 and the top of the first doping layer 203 , and between the bottom of the device gate structure 226 and the top of the first insulating layer 228 .

[0049] Specifically, in the process of forming the semiconductor structure, the protection layer 216 protects the channel structure layer 298 and reduces the probability of the channel structure layer 298 being etched and removed.

[0050] In this embodiment, the material of the protection layer 216 includes silicon.

[0051] Specifically, the channel structure layer 298 is used to provide a conductive channel for the transistor.

[0052] In this embodiment, the channel structure layer 298 includes a plurality of spaced channel layers 221, and the stacking direction of the plurality of stacked channel layers 221 is perpendicular to the surface of the substrate 200. In this embodiment, the number of the channel layers 221 is two.

[0053] In other embodiments, the number of channel layers is not limited to two.

[0054] In this embodiment, the material of the channel structure layer 298 is the same as that of the protrusion 201 , and the material of the channel structure layer 298 is Si.

[0055] Specifically, by setting the first insulating layer 228 in the short channel device region 200A, the risk of leakage through the substrate between the source and drain doping layers 232 subsequently formed in the short channel device region 200A and between the device gate structures 226 subsequently formed can be reduced, thereby improving the performance of the semiconductor structure.

[0056] As an example, the material of the first insulating layer 228 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0057] Silicon oxide, silicon nitride and silicon oxynitride are all dielectric materials and have electrical insulating properties.

[0058] It should be noted that the thickness of the first insulating layer 228 along the normal direction of the substrate surface should not be too large or too small. If the thickness of the first insulating layer 228 is too large, it is easy to affect the heat dissipation effect of the substrate when the semiconductor structure is in a working state, thereby affecting the performance of the semiconductor structure; if the thickness of the first insulating layer 228 is too small, it means that the electrical isolation effect of the first insulating layer 228 on the source-drain doping layer 232 of the short channel device area 200A and the device gate structure 226 is reduced, increasing the risk of leakage in the semiconductor structure. For this reason, in this embodiment, along the normal direction of the substrate surface, the thickness of the first insulating layer 228 is 10 nanometers to 30 nanometers.

[0059] Specifically, the source-drain doping layer 232 is used as the source region and the drain region of the transistor.

[0060] Among them, when the fully enclosed gate transistor is a P-type MOS transistor, the material of the stress layer is Si or SiGe, and the doped ions in the source and drain doping layer 232 are P-type ions; when the fully enclosed gate transistor is an N-type MOS transistor, the material of the stress layer is Si or SiC, and the doped ions in the source and drain doping layer 232 are N-type ions.

[0061] It should be noted that the source-drain doped layer 232 covers the top surface of the first doped layer 203 and the top surface of the first insulating layer 228, so that the source-drain doped layer 232 is in contact with the first doped layer 203 and the first insulating layer 228, which means that the source-drain doped layer 232 is not in contact with the substrate, thereby reducing the risk of leakage through the substrate between the source-drain doped layers 232 and the subsequently formed device gate structure 226.

[0062] In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 234 located on the top of the source-drain doped layer 232 and covering the sidewalls of the device gate structure 226 .

[0063] The interlayer dielectric layer 234 is used to achieve electrical isolation between adjacent devices.

[0064] In this embodiment, the material of the interlayer dielectric layer 234 is silicon oxide.

[0065] The device gate structure 226 is used to control the opening and closing of the conductive channel when the device is working.

[0066] Specifically, the device gate structure 226 is a metal gate structure.

[0067] In this embodiment, the device gate structure 226 includes a gate dielectric layer (not shown) surrounding and covering the channel layer 221 , and a gate electrode layer (not shown) covering the gate dielectric layer.

[0068] In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0069] Specifically, the gate dielectric layer includes a gate oxide layer surrounding and covering the top, sidewalls and bottom of the channel layer 221, and a high-k gate dielectric layer conformally covering the gate oxide layer. The material of the high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide.

[0070] The gate electrode layer is used for subsequent electrical connection with an external structure. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may also include only the work function layer.

[0071] Figures 4 to 20 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0072] refer to Figure 4 , providing a substrate (not shown), the substrate including a short channel device region 100A and a long channel device region 100B adjacent thereto.

[0073] The substrate is used to provide a process platform for forming a gate-all-around (GAA) transistor.

[0074] In this embodiment, the substrate is a three-dimensional substrate, and the substrate includes a substrate 100 and a protruding portion 101 protruding from the substrate 100 .

[0075] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0076] The protrusion 101 exposes a portion of the substrate 100 , thereby providing a process basis for subsequently forming an isolation layer.

[0077] In this embodiment, the material of the protrusion 101 is the same as that of the substrate 100, and the material of the protrusion 101 is silicon. In other embodiments, the material of the protrusion may also be a semiconductor material suitable for forming a fin, such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the protrusion may also be different from that of the substrate.

[0078] In this embodiment, the short channel device region 100A refers to a device region with a short conductive channel, and the long channel device region 100B refers to a region with a long conductive channel.

[0079] refer to Figures 5 and 6 , a first doping layer 103 is formed in the substrate of the long channel device region 100B, and a top surface of the first doping layer 103 is flush with a top surface of the substrate.

[0080] The first doped layer 103 is used as a well region of the long channel device region 100B, so as to adjust the threshold voltage of the transistor and solve some common problems in semiconductor structures, such as latch-up effect and other reliability problems.

[0081] In this embodiment, the long channel device region 100B refers to a region where the conductive channel is long.

[0082] Specifically, since the conductive channel of the long channel device area 100B is longer, the probability of leakage between adjacent devices through the substrate is very small. In the formation process of the semiconductor structure, by omitting the steps of forming a first sacrificial layer in the long channel device area 100B and then removing the first sacrificial layer to form a first insulating layer, the probability of the first sacrificial layer remaining in the long channel device area 100B is avoided, thereby reducing the probability of generating a parasitic transistor in the long channel device area, which will affect the threshold voltage and increase the parasitic resistance and capacitance.

[0083] In this embodiment, the step of forming the first doping layer 103 includes: forming a first mask layer 102 on the top of the substrate of the short channel device area 100A, the first mask layer 102 exposing the top surface of the substrate of the long channel device area 100B; performing a doping treatment on the substrate of the long channel device area 100B, and forming an ion doping layer (not marked) in the substrate of the long channel device area 100B, and the ion doping layer is used as the first doping layer 103.

[0084] Specifically, the first mask layer 102 protects the substrate of the short channel device region 100A, reducing the probability of doped ions entering the short channel device region 100A during the doping process of the substrate of the long channel device region 100B, thereby increasing the risk of leakage through the substrate between the source and drain doping layers subsequently formed in the short channel device region 100A and between the device gate structures subsequently formed.

[0085] In this embodiment, the material of the first mask layer 102 includes one or more of photoresist, silicon oxide and silicon nitride.

[0086] Specifically, by performing a doping process on the substrate of the long channel device region 100B, a first doping layer 103 is formed in the substrate of the long channel device region 100B, thereby overcoming the risk of sacrificial layer residue in the long channel device region 100B.

[0087] As an example, the process of performing doping treatment on the substrate of the long channel device region 100B includes an ion implantation process.

[0088] It should be noted that the ion implantation process has the characteristics of fast process rate and high process controllability. The ion implantation process is used to dope the substrate of the long channel device area 100B, which can accurately control the formation position of the ion doping layer and the depth of the ion doping layer in the substrate.

[0089] As an example, when the semiconductor structure is PMOS, the doping ions in the first doping layer 103 are one or both of P and As; when the semiconductor structure is NMOS, the doping ions in the first doping layer 103 are B.

[0090] It should also be noted that after forming the first doping layer 103 , the method for forming the semiconductor structure further includes: removing the first mask layer 102 .

[0091] Specifically, the process of removing the first mask layer 102 includes a wet etching process or an ashing process.

[0092] Continue to refer Figure 6 After the substrate of the long channel device region 100B is doped, the method further includes: heat treating the ion doping layer.

[0093] Specifically, the ion-doped layer is heat-treated to repair lattice defects caused by the doping treatment, thereby achieving the effect of activating the doped ions.

[0094] In this embodiment, the process of heat treating the ion-doped layer includes an annealing process.

[0095] Specifically, the annealing process has the characteristics of low process cost and high controllability of annealing temperature. The annealing process is used to perform heat treatment on the ion-doped layer, which can repair the lattice defects caused by the doping treatment.

[0096] refer to Figures 7 to 10 , a first sacrificial layer 110 is formed in the substrate of the short channel device region 100A, and a top surface of the first sacrificial layer 110 is flush with a top surface of the first doped layer 103 .

[0097] It should be noted that, compared with the existing solution of forming the first sacrificial layer 110 in the substrate of the long channel device region 100B and the short channel device region 100A and then removing the first sacrificial layer 110 to form the first insulating layer, the embodiment of the present invention omits the steps of forming the first sacrificial layer 110 in the long channel device region 100B and then removing the first sacrificial layer 110 to form the first insulating layer, thereby avoiding the probability of the first sacrificial layer 110 remaining in the long channel device region, and thus reducing the probability of generating a parasitic transistor in the long channel device region 100B. The tube will affect the threshold voltage and increase the parasitic resistance and capacitance. At the same time, by forming the first sacrificial layer 110 only in the short channel device area 100A, the formation area of ​​the first sacrificial layer 110 in the short channel device area 100A is used as the area for subsequently forming the first insulating layer. By forming the first insulating layer in the short channel device area 100A, the risk of leakage through the substrate between adjacent source and drain doping layers in the short channel device area 100A and between device gate structures formed subsequently can also be reduced, thereby improving the performance of the semiconductor structure.

[0098] It should also be noted that the first sacrificial layer 110 occupies a space position in advance for the first insulating layer to be formed subsequently.

[0099] It should also be noted that after the first doped layer 103 is formed, the first sacrificial layer 110 is formed, which reduces the probability of doped ions entering the first sacrificial layer 110 during the formation of the first doped layer 103, so that the etching rate of the first sacrificial layer 110 is not increased. In the subsequent process of removing the first sacrificial layer 110, the process difficulty of removing the first sacrificial layer 110 is reduced, which means that the probability of the first sacrificial layer 110 remaining in the short channel device area 100A is reduced.

[0100] In this embodiment, the step of forming the first sacrificial layer 110 includes: forming a second mask layer 106 on the top of the substrate of the long channel device area 100B, the second mask layer 106 exposing the top surface of the substrate of the short channel device area 100A; using the second mask layer 106 as a mask to remove a portion of the thickness of the substrate of the short channel device area 100A; forming a first sacrificial material layer 108 on the top surface of the substrate of the short channel device area 100A; using the top surface of the substrate of the long channel device area 100B as a stop position, flattening the first sacrificial material layer 108 and the second mask layer 106 that are higher than the top surface of the substrate of the long channel device area 100B, and using the remaining first sacrificial material layer 108 as the first sacrificial layer 110.

[0101] The second mask layer 106 protects the long channel device region 100B, thereby reducing the probability of causing damage to the film layer of the long channel device region 100B during the process of forming the first sacrificial layer 110 .

[0102] In this embodiment, the material of the second mask layer 106 includes one or more of photoresist, silicon oxide and silicon nitride.

[0103] In this embodiment, the process of forming the first sacrificial material layer 108 includes an epitaxial process.

[0104] As an example, the material of the first sacrificial layer 110 includes Si 1-x Ge x , wherein X represents the content of Ge element in SiGe, and the range of X is 40% to 60%.

[0105] It should be noted that there is an etching selectivity ratio between the material SiGe selected for the first sacrificial layer 110 and the material selected for forming the channel layer subsequently, which reduces the probability of the channel layer being etched and removed during the subsequent removal of the first sacrificial layer 110 .

[0106] It should also be noted that the content of Ge in the material SiGe used for the first sacrificial layer 110 is different from the content of Ge in the material used for the second sacrificial layer formed subsequently, which means that there is an etching selectivity ratio between the first sacrificial layer 110 and the second sacrificial layer. In the subsequent process of removing the first sacrificial layer 110, the probability of the second sacrificial layer being etched away can be reduced.

[0107] Specifically, the content of Ge in SiGe should not be too high or too low. If the content of Ge in SiGe is too high or too low, it is easy to cause the etching rate of the first sacrificial layer 110 to be close to the etching rate of the second sacrificial layer. Accordingly, in the subsequent process of removing the first sacrificial layer 110, the probability of the second sacrificial layer being etched and removed is also increased. For this reason, in this embodiment, the material of the first sacrificial layer 110 includes Si 1-x Ge x , wherein X represents the content of Ge element in SiGe, and the range of X is 40% to 60%.

[0108] It should be noted that the thickness of the first sacrificial layer 110 should not be too large or too small along the normal direction of the substrate surface. If the thickness of the first sacrificial layer 110 is too large, it is easy to cause too much first insulating layer to be formed in the substrate later, which affects the heat dissipation effect of the substrate when the semiconductor structure is in a working state, thereby affecting the performance of the semiconductor structure; if the thickness of the first sacrificial layer 110 is not too small, it means that the thickness of the first insulating layer formed later is too small, which easily reduces the electrical isolation effect of the first insulating layer on the source and drain doping layers formed later in the short channel device area 100A, and between the device gate structures formed later, thereby increasing the risk of leakage in the semiconductor structure. For this reason, in this embodiment, along the normal direction of the substrate surface, the thickness of the first sacrificial layer 110 is 10 nanometers to 30 nanometers.

[0109] refer to Fig.11 After forming the first sacrificial layer 110 and the first doped layer 103 , and before subsequently forming the stacked structure, the method for forming the semiconductor structure further includes: forming a protective layer 116 on top of the first sacrificial layer 110 and the first doped layer 103 .

[0110] The protection layer 116 is used to protect the second sacrificial layer formed subsequently, and can reduce the probability of the second sacrificial layer being etched and removed during the subsequent removal of the first sacrificial layer 110 .

[0111] In this embodiment, the material of the protection layer 116 includes silicon.

[0112] Specifically, there is an etching selectivity ratio between silicon and germanium silicon selected as the material of the first sacrificial layer 110. In the subsequent process of removing the first sacrificial layer 110, the protective layer 116 can protect the bottom of the subsequently formed second sacrificial layer, reducing the probability of the second sacrificial layer being etched and removed.

[0113] It should be noted that the thickness of the protective layer 116 along the normal direction of the substrate surface should not be too large or too small. If the thickness of the protective layer 116 is too large, it is easy to cause the overall height of the semiconductor structure to be too large, which does not meet the process size requirements; if the thickness of the protective layer 116 is too small, it is easy to cause the protective effect of the protective layer 116 on the bottom of the second sacrificial layer formed subsequently to decrease, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, along the normal direction of the substrate surface, the thickness of the protective layer 116 is 1 nanometer to 5 nanometers.

[0114] refer to Fig.12 A stacked structure (not shown) covering the first doped layer 103 and the first sacrificial layer 110 is formed above the substrate. The stacked structure includes one or more channel stacks 122 stacked in sequence in the longitudinal direction. The channel stack 122 includes a second sacrificial layer 120 and a channel layer 121 located on the second sacrificial layer 120.

[0115] Specifically, the stacked structure is used to provide a conductive channel for a transistor.

[0116] In this embodiment, the stacked structure includes one or more channel stacks 122 stacked in sequence in the longitudinal direction. The channel stack 122 includes a second sacrificial layer 120 and a channel layer 121 located on the second sacrificial layer 120 .

[0117] In this embodiment, the channel stack 122 is located on the top of the protruding portion 101 , and the extending direction of the channel stack 122 is the same as the extending direction of the protruding portion 101 .

[0118] In this embodiment, there are multiple channel stacks 122 , and the stacking direction of the multiple stacked channel stacks 122 is perpendicular to the surface of the substrate 100 .

[0119] Each channel stack 122 includes a second sacrificial layer 120 and a channel layer 121 located on the second sacrificial layer 120. The channel stack 122 provides a process basis for the subsequent formation of the suspended and spaced channel layer 121. Specifically, the second sacrificial layer 120 supports the channel layer 121, thereby providing a process basis for the subsequent realization of the spaced and suspended arrangement of the channel layer 121, and also occupies a spatial position for the subsequent formation of the device gate structure. The channel layer 121 is used to provide a conductive channel that fully surrounds the gate transistor.

[0120] In this embodiment, the material of the channel layer 121 is Si, and the material of the second sacrificial layer 120 is SiGe. In the subsequent process of removing the second sacrificial layer 120, the etching selectivity of SiGe and Si is relatively high, so by setting the material of the second sacrificial layer 120 to SiGe and the material of the channel layer 121 to Si, the effect of the removal process of the second sacrificial layer 120 on the channel layer 121 can be effectively reduced, thereby improving the quality of the channel layer 121, and further facilitating the improvement of device performance. In other embodiments, when forming a PMOS transistor, in order to improve the performance of the PMOS transistor, SiGe channel technology can be used, the material of the channel layer is SiGe, and the material of the second sacrificial layer is Si.

[0121] In this embodiment, the number of the channel stacks 122 is two. In other embodiments, the number of the channel stacks may be other numbers.

[0122] In this embodiment, an isolation layer (not shown) is further formed on the substrate 100 at the side of the protrusion 101 , and the isolation layer exposes the channel stack 122 .

[0123] The isolation layer is used to isolate adjacent protrusions 101 .

[0124] In this embodiment, the material of the isolation layer is silicon oxide.

[0125] refer to Fig.13 A gate structure 126 is formed on the substrate across the stacked structure, and the gate structure 126 covers a portion of the top and a portion of the sidewall of the stacked structure.

[0126] In this embodiment, the gate structure 126 is a dummy gate structure, and the gate structure 126 occupies a space position for a gate structure of a device to be formed subsequently.

[0127] In this embodiment, the gate structure 126 includes a dummy gate layer, and the material of the dummy gate layer includes polysilicon.

[0128] In this embodiment, the steps of forming the gate structure 126 include: forming a gate material layer (not shown) on the channel stack 122; forming a gate mask layer (not shown) on the gate material layer; using the gate mask layer as a mask, removing the gate material layer exposed by the gate mask layer, and the remaining gate material layer located on the channel stack 122 serves as the gate structure 126.

[0129] The gate mask layer is used as an etching mask when forming the gate structure 126 , and the gate mask layer can also protect the top of the gate structure 126 in subsequent processes.

[0130] In this embodiment, the material of the gate mask layer is silicon nitride.

[0131] refer to Fig.14After forming the gate structure 126, the first sacrificial layer 110 is removed to form a first groove 128 surrounded by the bottom of the stacked structure, the sidewall of the first doped layer 103, and the top of the substrate of the short channel device region 100A.

[0132] Specifically, the first sacrificial layer 110 is removed to form a first groove 128 , which provides a space for subsequently forming a first insulating layer in the first groove 128 .

[0133] In this embodiment, in the step of removing the first sacrificial layer 110 , an etching selectivity ratio exists between the first sacrificial layer 110 and the protection layer 116 .

[0134] It should be noted that there is an etching selectivity ratio between the first sacrificial layer 110 and the protective layer 116, so that in the process of removing the first sacrificial layer 110, the protective layer 116 is not easily etched away, which means that the protective layer 116 can protect the second sacrificial layer 120, reducing the probability of the second sacrificial layer 120 being mistakenly etched.

[0135] In this embodiment, the process of removing the first sacrificial layer 110 includes a wet etching process or a dry etching process.

[0136] In the wet etching process, the wet etching solution includes H2O2, HNO3, CH3COOH, and HF solution.

[0137] In the dry etching process, the dry etching includes HCl gas etching and ICP etching, and the etching gas includes H / F / Cl / N-based gas.

[0138] It should be noted that the wet etching process is an isotropic etching process, which can laterally etch the first sacrificial layer 110 in a direction parallel to the substrate surface, thereby achieving the probability of completely removing the first sacrificial layer 110 in the short channel device area, reducing the probability of the first sacrificial layer 110 remaining in the short channel device area 100A, thereby improving the performance of the semiconductor structure.

[0139] refer to Fig.15 , a first insulating layer 196 is formed in the first groove 128 .

[0140] Specifically, by forming a first insulating layer 196 in the first groove 128 of the short channel device area 100A, the risk of leakage through the substrate between the source and drain doping layers subsequently formed in the short channel device area 100A and between the device gate structures subsequently formed can be reduced, thereby improving the performance of the semiconductor structure.

[0141] As an example, the material of the first insulating layer 196 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0142] Silicon oxide, silicon nitride and silicon oxynitride are all dielectric materials and have electrical insulating properties.

[0143] It should be noted that the thickness of the first insulating layer 196 along the normal direction of the substrate surface should not be too large or too small. If the thickness of the first insulating layer 196 is too large, it is easy to affect the heat dissipation effect of the substrate when the semiconductor structure is in a working state, thereby affecting the performance of the semiconductor structure; if the thickness of the first insulating layer 196 is too small, it means that the first insulating layer 196 has a reduced effect on the electrical isolation between the source and drain doping layers subsequently formed in the short channel device area 100A, and between the device gate structures subsequently formed, thereby increasing the risk of leakage in the semiconductor structure. For this reason, in this embodiment, along the normal direction of the substrate surface, the thickness of the first insulating layer 196 is 10 nanometers to 30 nanometers.

[0144] refer to Fig.16 After forming the first insulating layer 196 , a second groove 130 is formed in the long channel device region 100B in the stacked structure on both sides of the gate structure 126 , and a second groove 130 is formed in the short channel device region 100A, and the second groove 130 exposes the stacked structure.

[0145] The second groove 130 provides a space for the subsequent formation of source and drain doping layers.

[0146] In this embodiment, the process of forming the second groove 130 includes a dry etching process.

[0147] Specifically, the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has better profile controllability, which is beneficial to improving the profile quality of the second groove 130. In addition, the selected anisotropic dry etching process is beneficial to achieving a higher etching selectivity, thereby reducing the probability of causing mis-etching to other film layers.

[0148] It should be noted that, in this embodiment, the step of forming the second groove 130 also includes removing the protection layer 116 on both sides of the gate structure 126 .

[0149] The protective layer 116 on both sides of the gate structure 126 is removed to expose the top surfaces of the first doped layer 103 and the first insulating layer 196 , so that the subsequently formed source and drain doped layers can cover the top surfaces of the first doped layer 103 and the first insulating layer 196 , thereby reducing the probability of leakage of the subsequently formed source and drain doped layers through the protective layer 116 .

[0150] refer to Fig.17 A source-drain doped layer 132 is formed in the second groove 130 , and the source-drain doped layer 132 covers the top surface of the first doped layer 103 and the top surface of the first insulating layer 196 .

[0151] In this embodiment, the process of forming the source-drain doped layer 132 in the second groove 130 includes an epitaxial process.

[0152] Among them, when the fully enclosed gate transistor is a P-type MOS transistor, the material of the stress layer is Si or SiGe, and the doped ions in the source and drain doping layer 132 are P-type ions; when the fully enclosed gate transistor is an N-type MOS transistor, the material of the stress layer is Si or SiC, and the doped ions in the source and drain doping layer 132 are N-type ions.

[0153] It should be noted that the source-drain doped layer 132 covers the top surface of the first doped layer 103 and the top surface of the first insulating layer 196, so that the source-drain doped layer 132 is in contact with the first doped layer 103 and the first insulating layer 196, which means that the source-drain doped layer 132 is not in contact with the substrate, thereby reducing the risk of leakage through the substrate between the source-drain doped layers 132 and between the subsequently formed device gate structures.

[0154] refer to Fig.18 After forming the source-drain doping layer 132 , the forming method further includes: forming an interlayer dielectric layer 134 on the top of the source-drain doping layer 132 , wherein the interlayer dielectric layer 134 covers the sidewalls of the gate structure 126 .

[0155] The interlayer dielectric layer 134 is used to achieve electrical isolation between adjacent devices.

[0156] In this embodiment, the material of the interlayer dielectric layer 134 is silicon oxide.

[0157] In this embodiment, the step of forming the interlayer dielectric layer 134 includes: forming a dielectric material layer (not shown) on the substrate of the side wall of the gate structure 126, and the dielectric material layer also covers the top of the gate structure 126; removing the dielectric material layer above the top of the gate structure 126, and the remaining dielectric material layer serves as the interlayer dielectric layer 134.

[0158] refer to Fig.19 , the gate structure 126 is removed, and a gate opening 140 is formed in the interlayer dielectric layer 134 .

[0159] Specifically, the gate opening 140 provides a process window for the subsequent formation and removal of the second sacrificial layer, and also provides a spatial position for the subsequent formation of a device gate structure.

[0160] In this embodiment, the process of removing the gate structure 126 includes a dry etching process.

[0161] In this embodiment, before removing the gate structure 126 , the method for forming a semiconductor structure further includes: removing the gate mask layer.

[0162] The gate mask layer is removed to expose the top of the gate structure 126 in preparation for removing the gate structure 126 .

[0163] Continue to refer Fig.19 After forming the gate opening 140 , the second sacrificial layer 120 is removed.

[0164] Specifically, removing the second sacrificial layer 120 provides a space for subsequently forming a device gate structure.

[0165] In this embodiment, a wet etching process is used to remove the second sacrificial layer 120. In the wet etching process, the wet etching solution includes H2O2, HNO3, CH3COOH, and HF solution.

[0166] In other embodiments, a dry etching process may be used to remove the second sacrificial layer. In the dry etching process, the dry etching includes HCl gas etching and ICP etching, and the etching gas includes H / F / Cl / N-based gas.

[0167] The second sacrificial layer 120 is removed after the source-drain doped layer 132 is formed. Therefore, after removing the second sacrificial layer 120, along the extension direction of the protrusion 101, both ends of the channel layer 121 are connected to the source-drain doped layer 132 and suspended in the gate opening 140, thereby providing a basis for the subsequent device gate structure to surround the channel layer 121.

[0168] After the second sacrificial layer 120 is removed, the channel layers 121 are arranged at intervals, and the remaining channel layers 121 constitute a channel structure layer, which is located on the protrusion 101 and is arranged at intervals from the protrusion 101 .

[0169] refer to Fig. 20 A device gate structure 136 is formed in the gate opening 140 , and the device gate structure 136 includes a gate dielectric layer (not shown) surrounding and covering the channel layer 121 , and a gate electrode layer (not shown) covering the gate dielectric layer.

[0170] The device gate structure 136 is used to control the opening and closing of the conductive channel when the device is working.

[0171] Specifically, the device gate structure 136 is a metal gate structure.

[0172] In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0173] Specifically, the gate dielectric layer includes a gate oxide layer surrounding and covering the top, sidewalls and bottom of the channel layer 121, and a high-k gate dielectric layer conformally covering the gate oxide layer. The material of the high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide.

[0174] It should be noted that the gate dielectric layer also conformally covers a portion of the top of the isolation layer.

[0175] The gate electrode layer is used for subsequent electrical connection with an external structure. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may also include only the work function layer.

[0176] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, comprising a short channel device region and a long channel device region adjacent thereto; A first doped layer is located in the substrate of the long channel device region, and a top surface of the first doped layer is flush with a top surface of the substrate; A first insulating layer, located in the substrate of the short channel device region, wherein a top surface of the first insulating layer is flush with a top surface of the first doping layer; A channel structure layer is suspended on the substrate, and the channel structure includes one or more channel layers spaced apart in the longitudinal direction; A device gate structure, located on the substrate and spanning the channel structure layer; The source-drain doped layers are located in the channel structure layer on both sides of the device gate structure, and the source-drain doped layers cover the top surface of the first doped layer and the top surface of the first insulating layer.

2. The semiconductor structure according to claim 1, wherein: The doping ions in the first doping layer include one or more of P ions, As ions and B ions.

3. The semiconductor structure according to claim 1, wherein: The material of the first insulating layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

4. The semiconductor structure according to claim 1, wherein: Along the normal direction of the substrate surface, the thickness of the first insulating layer is 10 nanometers to 30 nanometers.

5. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes a protection layer located between the bottom of the device gate structure and the top of the first doping layer, and between the bottom of the device gate structure and the top of the first insulating layer.

6. The semiconductor structure according to claim 1, wherein: The device gate structure comprises a gate dielectric layer surrounding and covering the channel layer, and a gate electrode layer covering the gate dielectric layer; The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

7. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a short channel device region and a long channel device region adjacent thereto; forming a first doped layer in the substrate of the long channel device region, wherein a top surface of the first doped layer is flush with a top surface of the substrate; forming a first sacrificial layer in the substrate of the short channel device region, wherein a top surface of the first sacrificial layer is flush with a top surface of the first doped layer; forming a stacked structure covering the first doped layer and the first sacrificial layer above the substrate, the stacked structure comprising one or more channel stacks stacked in sequence in a longitudinal direction, the channel stack comprising a second sacrificial layer and a channel layer located on the second sacrificial layer; forming a gate structure across the stacked structure on the substrate, wherein the gate structure covers a portion of the top and a portion of the sidewall of the stacked structure; After forming the gate structure, removing the first sacrificial layer to form a first groove surrounded by the bottom of the stacked structure, the sidewall of the first doped layer, and the top of the substrate of the short channel device region; forming a first insulating layer in the first groove; After forming the first insulating layer, forming a second groove located in the long channel device region and a second groove located in the short channel device region in the stacked structure on both sides of the gate structure, wherein the second groove exposes the stacked structure; A source-drain doped layer is formed in the second groove, and the source-drain doped layer covers a top surface of the first doped layer and a top surface of the first insulating layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: The step of forming the first doping layer includes: forming a first mask layer on the top of the substrate of the short channel device area, the first mask layer exposing the top surface of the substrate of the long channel device area; performing doping treatment on the substrate of the long channel device area to form an ion doping layer in the substrate of the long channel device area, the ion doping layer is used as the first doping layer; removing the first mask layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: The process of performing doping treatment on the substrate of the long channel device region includes an ion implantation process.

10. The method for forming a semiconductor structure according to claim 9, wherein: The parameters of the ion implantation process include: the implanted ions include one or more of P ions, As ions and B ions.

11. The method for forming a semiconductor structure according to claim 7, wherein: After forming the first doping layer, the first sacrificial layer is formed.

12. The method for forming a semiconductor structure according to claim 7 or 11, characterized in that: The step of forming the first sacrificial layer includes: forming a second mask layer on the top of the substrate of the long channel device area, the second mask layer exposing the top surface of the substrate of the short channel device area; using the second mask layer as a mask to remove a portion of the thickness of the substrate of the short channel device area; forming a first sacrificial material layer on the top surface of the substrate of the short channel device area; using the top surface of the substrate of the long channel device area as a stop position, flattening the first sacrificial material layer and the second mask layer that are higher than the top surface of the substrate of the long channel device area, and using the remaining first sacrificial material layer as the first sacrificial layer.

13. The method for forming a semiconductor structure according to claim 7, wherein: The material of the first sacrificial layer includes Si 1-x Ge x , wherein X represents the content of Ge element in SiGe, and the range of X is 40% to 60%.

14. The method for forming a semiconductor structure according to claim 7, wherein: Along the normal direction of the substrate surface, the thickness of the first sacrificial layer is 10 nanometers to 30 nanometers.

15. The method for forming a semiconductor structure according to claim 7, wherein: After forming the first sacrificial layer and the first doped layer and before forming the stacked structure, the method for forming the semiconductor structure further includes: forming a protective layer on top of the first sacrificial layer and the first doped layer; In the step of removing the first sacrificial layer, an etching selectivity ratio exists between the first sacrificial layer and the protective layer; The step of forming the second groove also includes removing the protection layer on both sides of the gate structure.

16. The method for forming a semiconductor structure according to claim 15, wherein: The material of the protection layer includes silicon.

17. The method for forming a semiconductor structure according to claim 15, wherein: Along the normal direction of the substrate surface, the thickness of the protective layer is 1 nanometer to 5 nanometers.

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