Metal oxide semiconductor field effect transistor, manufacturing method thereof, and electronic device

Abstract

The present invention discloses a metal oxide semiconductor field effect transistor (MOSFET), a method for preparing the same, and an electronic device. A trench is dug in both the N+ substrate and the N-type low-doped semiconductor layer to expose the N-type drift layer. A high-concentration N-type impurity-doped N+ drain region is formed on the side of the N-type drift layer near the N+ substrate, and the drain conductive layer fills the trench. This significantly reduces the resistance of the N+ substrate, and the N+ substrate can be maintained relatively thick without thinning the N+ substrate. Compared to existing methods of thinning the N+ substrate, the present invention reduces the risk of fragmentation and maintains the mechanical strength of the wafer. The drain conductive layer of the present invention directly contacts the N-type low-doped semiconductor layer, which facilitates the extraction of holes from the interface between the drain conductive layer and the N-type low-doped semiconductor layer when the body diode of the MOSFET is turned on, reducing the hole density within the N-type drift layer and thus reducing the reverse recovery charge and reverse recovery current of the device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a metal oxide semiconductor field effect transistor, a preparation method thereof, and an electronic device. Background Art

[0002] Bridge circuits, such as half-bridge circuits and full-bridge circuits, are widely used due to their simple circuit structure and simple drive. In bridge circuits, diodes are often required or the body diode of a MOSFET is used to freewheel the current in the inductive load. Since the body diode in the MOSFET is a PiN diode, there are a large number of free carriers in the drift region when the body diode is turned on. Although this helps to reduce the conduction voltage drop of the body diode, it will lead to higher reverse recovery charge and reverse recovery current, which not only leads to higher power consumption and limits the increase in device frequency, but also affects the long-term reliability of the device. In addition, in SiC-based MOSFETs, the holes when the body diode is turned on will produce a bipolar degeneration effect. Therefore, it is necessary to reduce the reverse recovery charge of the MOSFET body diode and improve the reverse recovery characteristics.

[0003] MOSFETs typically have a vertical structure. For vertical power devices, a thicker substrate leads to higher substrate resistance. Reducing the substrate thickness can reduce substrate resistance and improve heat dissipation. Substrate thinning techniques are often used to grind the substrate to a specified thickness. However, an excessively thin substrate not only means longer processing time and higher process costs, but is also prone to fragmentation. Summary of the Invention

[0004] The embodiments of the present disclosure provide a metal oxide semiconductor field effect transistor, a preparation method thereof, and an electronic device for reducing the reverse recovery charge and reverse recovery current of the device. Furthermore, while reducing the on-resistance of the device, the device can still maintain a thicker substrate, and the device is less likely to be fragmented.

[0005] The present disclosure provides a metal oxide semiconductor field effect transistor, a method for manufacturing the same, and an electronic device. The specific scheme is as follows:

[0006] In one aspect, an embodiment of the present disclosure provides a metal oxide semiconductor field effect transistor, comprising:

[0007] An N+ substrate including a first trench extending through a thickness thereof;

[0008] An N-type low-doped semiconductor layer is located on one side of the N+ substrate, wherein the N-type low-doped semiconductor layer includes a second trench extending through the thickness thereof, and the first trench and the second trench overlap;

[0009] An N-type drift layer is located on a side of the N-type low-doped semiconductor layer away from the N+ substrate;

[0010] an N+ drain region located in the N-type drift layer and on a side of the N-type drift layer close to the N+ substrate, wherein the N+ drain region covers the second trench;

[0011] A drain conductive layer covers a side of the N+ substrate away from the N-type drift layer and fills the first trench and the second trench until it contacts the N+ drain region.

[0012] In some embodiments, in the metal oxide semiconductor field effect transistor provided by the embodiments of the present disclosure, the N+ drain region also covers a portion of the N-type low-doped semiconductor layer.

[0013] In some embodiments, in the metal oxide semiconductor field effect transistor provided by the embodiments of the present disclosure, the N-type low-doped semiconductor layer is an N-type buffer layer.

[0014] In some embodiments, in the metal oxide semiconductor field effect transistor provided by the embodiments of the present disclosure, a side of the N+ drain region close to the N+ substrate contacts a side of the N-type buffer layer away from the N+ substrate.

[0015] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, the N-type drift layer has a groove that penetrates part of its thickness on a side close to the N+ substrate and corresponding to the second trench, the groove and the second trench overlap, and the N-type drift layer is provided between the N+ drain region and the N-type buffer layer.

[0016] In some embodiments, in the metal oxide semiconductor field effect transistor provided by the embodiments of the present disclosure, the N-type low-doped semiconductor layer and the N-type drift layer are an integrated structure.

[0017] In some embodiments, the metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure further includes: two P-type well regions located in the N-type drift layer and close to a side of the N-type drift layer away from the N+ substrate, and an N+ source region and a P+ source region located in the P-type well region and close to a side of the N-type drift layer away from the N+ substrate; wherein the N+ source region and the P+ source region are laterally arranged and contact each other, and the P+ source region is disposed close to a side of the N-type drift layer, and the P-type well region covers the sides of the P+ source region and the N+ source region close to the N+ substrate and covers the side of the N+ source region away from the P+ source region;

[0018] The present invention also includes: a gate dielectric layer located on a side of the N-type drift layer away from the N+ substrate, a gate conductive layer located on a side of the gate dielectric layer away from the N+ substrate, and an isolation dielectric layer located on a side of the gate conductive layer away from the N+ substrate; wherein the gate dielectric layer is in contact with the N-type drift layer, the P-type well region, and the N+ source region, and the isolation dielectric layer wraps around the gate conductive layer and is in contact with the gate dielectric layer;

[0019] It also includes a source conductive layer located on the side of the isolation dielectric layer, the N+ source region and the P+ source region away from the N+ substrate. The source conductive layer wraps the isolation dielectric layer and contacts the N+ source region and the P+ source region.

[0020] On the other hand, the present disclosure also provides a method for preparing a metal oxide semiconductor field effect transistor, which is used to prepare the metal oxide semiconductor field effect transistor provided in the present disclosure. The preparation method includes:

[0021] Epitaxially forming an N-type low-doped semiconductor layer and an N-type drift layer on one side of the N+ substrate;

[0022] Etching the N+ substrate and the N-type low-doped semiconductor layer to form a first trench penetrating the thickness of the N+ substrate and a second trench penetrating the thickness of the N-type low-doped semiconductor layer, so as to expose the N-type drift layer;

[0023] Implanting N-type impurities into the exposed side of the N-type drift layer close to the N+ substrate to form an N+ drain region;

[0024] A drain conductive layer is formed on a side of the N+ substrate away from the N-type drift layer, and the drain conductive layer fills the first trench and the second trench until it contacts the N+ drain region.

[0025] In some embodiments, in the above-mentioned preparation method provided in the embodiments of the present disclosure, when etching the N+ substrate and the N-type low-doped semiconductor layer to form a first trench extending through the thickness of the N+ substrate and a second trench extending through the thickness of the N-type low-doped semiconductor layer, the method further includes:

[0026] A groove is formed by over-etching into the N-type drift layer.

[0027] In some embodiments, in the above-mentioned preparation method provided by the embodiments of the present disclosure, after epitaxially forming the N-type low-doped semiconductor layer and the N-type drift layer on one side of the N+ substrate, and before etching the N+ substrate and the N-type low-doped semiconductor layer, the method further includes: forming a P-type well region, an N+ source region, and a P+ source region on a side of the N-type drift layer away from the N+ substrate by implanting corresponding N-type or P-type impurities;

[0028] After implanting N-type impurities into the exposed N-type drift layer on a side close to the N+ substrate to form an N+ drain region, and before forming a drain conductive layer on a side of the N+ substrate away from the N-type drift layer, the method further includes:

[0029] forming a gate dielectric layer on a side of the N-type drift layer away from the N+ substrate;

[0030] forming a gate conductive layer on a side of the gate dielectric layer away from the N+ substrate;

[0031] forming an isolation dielectric layer on a side of the gate conductive layer away from the N+ substrate;

[0032] A source conductive layer is formed on a side of the isolation dielectric layer, the N+ source region, and the P+ source region away from the N+ substrate.

[0033] On the other hand, an embodiment of the present disclosure further provides an electronic device, comprising the above-mentioned metal oxide semiconductor field effect transistor provided by an embodiment of the present disclosure.

[0034] The beneficial effects of the present disclosure are as follows:

[0035] The present disclosure provides a metal oxide semiconductor field effect transistor, a method for manufacturing the same, and an electronic device. A trench is dug in both the N+ substrate and the N-type low-doped semiconductor layer to expose the N-type drift layer. An N+ drain region doped with a high concentration of N-type impurities is formed on the side of the exposed N-type drift layer near the N+ substrate. The N+ drain region can reduce on-resistance and improve withstand voltage performance. Furthermore, the drain conductive layer fills the trench, so that the drain conductive layer contacts the side of the N+ substrate at the first trench position, the side of the N-type low-doped semiconductor layer at the second trench position, and the side of the N+ drain region near the N+ substrate. Therefore, the metal oxide semiconductor field effect transistor provided by the present disclosure can significantly reduce the resistance of the N+ substrate and can maintain a relatively thick N+ substrate without thinning the N+ substrate. Compared to the prior art method of thinning the N+ substrate, the present disclosure reduces the risk of fragmentation and maintains the mechanical strength of the wafer. At the same time, the drain conductive layer disclosed in the present invention can be in direct contact with the N-type low-doped semiconductor layer, which is beneficial for holes to be extracted from the contact surface between the drain conductive layer and the N-type low-doped semiconductor layer when the body diode of the metal oxide semiconductor field effect transistor is turned on, thereby reducing the hole density in the N-type drift layer, and is beneficial for reducing the reverse recovery charge and reverse recovery current of the metal oxide semiconductor field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic structural diagram of a metal oxide semiconductor field effect transistor provided in an embodiment of the present disclosure;

[0037] Figure 2 A schematic diagram of another structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present disclosure;

[0038] Figure 3 A schematic diagram of another structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present disclosure;

[0039] Figure 4A A schematic diagram of the forward current distribution of the metal oxide semiconductor field effect transistor provided in an embodiment of the present disclosure;

[0040] Figure 4B Schematic diagram of the forward current distribution of a conventional metal oxide semiconductor field effect transistor;

[0041] Figure 5A A schematic diagram of reverse conduction current distribution of a metal oxide semiconductor field effect transistor provided in an embodiment of the present disclosure;

[0042] Figure 5B Schematic diagram of reverse current distribution of a conventional metal oxide semiconductor field effect transistor;

[0043] Figure 6 A flow chart of a method for preparing a metal oxide semiconductor field effect transistor according to an embodiment of the present disclosure;

[0044] Figure 7 A flow chart of another method for preparing a metal oxide semiconductor field effect transistor according to an embodiment of the present disclosure;

[0045] Figure 8A for Figure 1 A schematic diagram of the structure of a metal oxide semiconductor field effect transistor during the preparation process is shown;

[0046] Figure 8B for Figure 1 Another structural schematic diagram of a metal oxide semiconductor field effect transistor during the preparation process is shown;

[0047] Figure 8C for Figure 1 Another structural schematic diagram of a metal oxide semiconductor field effect transistor during the preparation process is shown;

[0048] Figure 8D for Figure 1 Another structural schematic diagram of a metal oxide semiconductor field effect transistor during the preparation process is shown;

[0049] Figure 8E for Figure 1 Another structural schematic diagram of a metal oxide semiconductor field effect transistor during the preparation process is shown. DETAILED DESCRIPTION

[0050] To further clarify the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below in conjunction with the accompanying drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In this disclosure, exemplary embodiments are described with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes shown in the drawings are to be expected, for example, as a result of manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape resulting from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features; a sharp angle illustrated may be rounded, etc. Therefore, the regions shown in the drawings are schematic in nature, and their sizes and shapes do not represent the exact shapes of the illustrated regions or are not true to scale. They are intended solely to illustrate the present disclosure. Throughout, identical or similar reference numerals denote identical or similar elements or elements having identical or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0051] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0052] In the following description, when an element or layer is referred to as being “on” or “connected to” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as being “disposed on one side of” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there are no intermediate elements or intermediate layers. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0053] The present disclosure provides a metal oxide semiconductor field effect transistor, such as Figure 1 Shown, including:

[0054] N+ substrate 1, N+ substrate 1 includes a first trench U1 running through the thickness thereof;

[0055] An N-type low-doped semiconductor layer 2 is located on one side of the N+ substrate 1. The N-type low-doped semiconductor layer 2 includes a second trench U2 running through the thickness thereof. The first trench U1 and the second trench U2 overlap.

[0056] An N-type drift layer 3 is located on a side of the N-type low-doped semiconductor layer 2 away from the N+ substrate 1;

[0057] An N+ drain region 4 is located in the N-type drift layer 3 and on a side of the N-type drift layer 3 close to the N+ substrate 1 . The N+ drain region 4 covers the second trench U2 .

[0058] The drain conductive layer 5 covers the side of the N+ substrate 1 away from the N-type drift layer 3 and fills the first trench U1 and the second trench U2 until it contacts the N+ drain region 4 .

[0059] In the metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, trenches are dug in both the N+ substrate and the N-type low-doped semiconductor layer, exposing the N-type drift layer. An N+ drain region doped with a high concentration of N-type impurities is formed on the side of the exposed N-type drift layer near the N+ substrate. The N+ drain region can reduce on-resistance and improve withstand voltage performance. Furthermore, the drain conductive layer fills the trenches, so that the drain conductive layer contacts the side of the N+ substrate at the first trench position, the side of the N-type low-doped semiconductor layer at the second trench position, and the side of the N+ drain region near the N+ substrate. Therefore, the metal oxide semiconductor field effect transistor provided in the present disclosure can significantly reduce the resistance of the N+ substrate, and can maintain a relatively thick N+ substrate without thinning the N+ substrate. Compared to the prior art method of thinning the N+ substrate, the present disclosure reduces the risk of fragmentation and maintains the mechanical strength of the wafer. At the same time, the drain conductive layer disclosed in the present invention is in direct contact with the N-type low-doped semiconductor layer, which is beneficial for holes to be extracted from the contact surface between the drain conductive layer and the N-type low-doped semiconductor layer when the body diode of the metal oxide semiconductor field effect transistor is turned on, thereby reducing the hole density in the N-type drift layer, and is beneficial for reducing the reverse recovery charge and reverse recovery current of the metal oxide semiconductor field effect transistor.

[0060] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 1-Figure 3 As shown, the N+ drain region 4 can be formed by ion implantation of high-concentration N-type impurities in the N-type drift layer exposed in the first trench U1 and the second trench U2. Due to the influence of the ion implantation process, the N+ drain region 4 will also cover part of the N-type low-doped semiconductor layer 2, that is, the N+ drain region 4 cannot completely cover the N-type low-doped semiconductor layer 2, and the side of the N-type drift layer 3 close to the N+ substrate 1 needs to be in contact with the side of the N-type low-doped semiconductor layer 2 away from the N+ substrate 1.

[0061] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 1-Figure 3 As shown, the first trench U1 and the second trench U2 can be formed by one etching process, and the cross-sectional shape of the entire trench formed by the first trench U1 and the second trench U2 along the thickness direction of the N+ substrate 1 can be rectangular, but is certainly not limited thereto.

[0062] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 1 As shown, the N-type low-doped semiconductor layer 2 may be an N-type buffer layer, and the side of the N+ drain region 4 close to the N+ substrate 1 contacts the side of the N-type buffer layer (i.e., the N-type low-doped semiconductor layer 2) away from the N+ substrate 1. That is, when etching the N+ substrate and the N-type low-doped semiconductor layer 2, the etching reaches the interface between the N-type buffer layer and the N-type drift layer 3.

[0063] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 1 As shown, it also includes: two P-type well regions 6 located in the N-type drift layer 3 and close to the side of the N-type drift layer 3 away from the N+ substrate 1, and an N+ source region 7 and a P+ source region 8 located in the P-type well region 6 and close to the side of the N-type drift layer 3 away from the N+ substrate 1; wherein, the N+ source region 7 and the P+ source region 8 are arranged laterally and contact each other, and the P+ source region 8 is arranged close to the side of the N-type drift layer 3, and the P-type well region 6 covers the side of the P+ source region 8 and the N+ source region 7 close to the N+ substrate 1 and covers the side of the N+ source region 7 away from the P+ source region 8; specifically, as shown Figure 1 As shown, the P-type well region 6 , the N+ source region 7 and the P+ source region 8 are all formed by ion implantation on a side of the N-type drift layer 3 away from the N+ substrate 1 .

[0064] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 1 As shown, it also includes: a gate dielectric layer 9 located on the side of the N-type drift layer 3 away from the N+ substrate 1, a gate conductive layer 10 located on the side of the gate dielectric layer 9 away from the N+ substrate 1, and an isolation dielectric layer 11 located on the side of the gate conductive layer 10 away from the N+ substrate 1; wherein, the gate dielectric layer 9 is in contact with the N-type drift layer 3, the P-type well region 6 and the N+ source region 7, and the isolation dielectric layer 11 wraps the gate conductive layer 10 and is in contact with the gate dielectric layer 9; specifically, the materials of the gate dielectric layer 9 and the isolation dielectric layer 11 can be SiO2, HfO2, Al2O3, Si3N4, etc.

[0065] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 1 As shown, the gate structure composed of the gate dielectric layer 9, the gate conductive layer 10 and the isolation dielectric layer 11 is a planar gate, and can certainly be a trench gate, which is not limited in the present disclosure.

[0066] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 1 As shown, it also includes a source conductive layer 12 located on the side of the isolation dielectric layer 11, the N+ source region 7 and the P+ source region 8 away from the N+ substrate 1. The source conductive layer 12 wraps the isolation dielectric layer 11 and contacts the N+ source region 7 and the P+ source region 8.

[0067] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 1As shown, the side of the source conductive layer 12 away from the N+ substrate 1 is a flat surface, and the side of the drain conductive layer 5 away from the N+ substrate 1 is a flat surface, which is beneficial to improving device performance.

[0068] Specifically, if Figure 1 As shown, the P-type well region 6, N+ source region 7, P+ source region 8, and source conductive layer 12 constitute the source region of the device. The gate dielectric layer 9, gate conductive layer 10, and isolation dielectric layer 11 constitute the gate region of the device. The N-type drift layer 3 serves as the drift region of the device. The N+ substrate 1, N-type buffer layer (i.e., N-type low-doped semiconductor layer 2), N+ drain region 4, and drain conductive layer 5 constitute the drain region of the device. The cell structure of the device includes the aforementioned source region, gate region, drift region, and drain region. A single cell may include multiple P-type well regions 6, N+ source regions 7, P+ source regions 8, and source conductive layers 12.

[0069] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, the source conductive layer and the drain conductive layer can be made of materials such as metal; the gate conductive layer can be made of one or more materials such as doped polysilicon and metal.

[0070] by Figure 1 Taking the metal oxide semiconductor field effect transistor shown in FIG. 1 as an example, the forward conduction and reverse conduction current distributions of the metal oxide semiconductor field effect transistor of the present invention and the conventional metal oxide semiconductor field effect transistor are compared. The difference between the conventional structure and the structure of the present invention is that the N+ substrate 1 and the N-type buffer layer (i.e., the N-type low-doped semiconductor layer 2) in the conventional structure are not grooved, and the N+ drain region 4 is not formed in the N-type drift layer 3. Figure 4A and Figure 4B As shown, Figure 4A Schematic diagram of the forward conduction current distribution of the structure disclosed in this invention. Figure 4B This is a schematic diagram of the forward conduction current distribution of a conventional structure. The arrows indicate the current path. As can be seen from the figure, the forward current of the conventional structure needs to completely pass through the substrate N+ substrate 1 and the N-type buffer layer from the drain conductive layer 5. Therefore, the device on-resistance is closely related to the resistance of the N+ substrate 1 and the N-type buffer layer. Reducing this resistance is often achieved by thinning the thickness of the N+ substrate 1. However, if the N+ substrate 1 is too thin, it is easy to cause fragmentation. However, most of the forward current of the structure disclosed in the present invention is from the drain conductive layer 5 through the N+ drain region 4 to the N-type drift layer 3. Since the doping concentration of the N+ drain region 4 is high and it is at least 2 orders of magnitude thinner than the N+ substrate 1, the high parasitic resistance caused by the thick N+ substrate 1 and the N-type buffer layer is greatly reduced, thereby reducing the on-resistance of the device. Figure 5A and Figure 5B As shown, Figure 5A Schematic diagram of reverse conduction current distribution of the disclosed structure. Figure 5B This is a schematic diagram of the reverse current distribution in a conventional structure, with arrows indicating current paths. As can be seen from the figure, the hole current conduction path in conventional structures must pass through the N+ substrate 1. Due to the high doping concentration and thickness of the N+ substrate 1, holes have difficulty passing through the N+ substrate 1 to reach the drain conductive layer 5. Consequently, a large number of holes are stored in the N-type drift layer 3, resulting in a high hole concentration in the N-type drift layer 3 and, consequently, a large reverse recovery charge during the reverse recovery process. In contrast, in the structure disclosed herein, the N+ drain region 4 is thinner, making it easier for holes to pass through it and enter the drain conductive layer 5. Furthermore, holes can also enter the drain conductive layer 5 via the N-type buffer layer, which has a lower doping concentration. Consequently, the hole concentration in the N-type drift layer 3 of the disclosed structure is lower, reducing the reverse recovery charge during the reverse recovery process.

[0071] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 2 As shown, the N-type low-doped semiconductor layer 2 can be an N-type buffer layer, and the N-type drift layer 3 is close to the N+ substrate 1 and has a groove U3 that runs through part of its thickness on the side corresponding to the second trench U2. The groove U3 overlaps with the second trench U2, and there is an N-type drift layer 3 between the N+ drain region 4 and the N-type buffer layer (that is, the N-type low-doped semiconductor layer 2). Figure 2 When etching the N+ substrate 1 and the N-type buffer layer, the structure shown in FIG. 1 can be overetched to form a groove U3 inside the N-type drift layer 3, and then ion implantation is performed on the side of the N-type drift layer 3 exposed at the groove U3 near the N+ substrate 1 to form an N+ drain region 4, which is consistent with the present disclosure. Figure 1 Compared to the structure shown, Figure 2 The structure shown is overetched to the inside of the N-type drift layer 3, so that the drain conductive layer 5 is directly in contact with the lower-doped N-type drift layer 3. Therefore, when the body diode of the device is turned on, the hole concentration stored in the N-type drift layer 3 is lower than that in the N-type drift layer 3. Figure 1 The structure shown can be lowered to further reduce the reverse recovery charge during the reverse recovery process.

[0072] It should be noted that Figure 2 The structure shown and Figure 1 Compared with the structure shown in FIG, except that when etching the N+ substrate 1 and the N-type buffer layer, the groove U3 is formed inside the N-type drift layer 3, the rest of the structure is the same. For details, please refer to the above description. Figure 1 Description of the structure shown.

[0073] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 3As shown, the N-type low-doped semiconductor layer 2 and the N-type drift layer 3 can be an integrated structure, that is, the N-type drift layer 3 is directly epitaxially formed on one side of the N+ substrate 1. When the N+ substrate 1 is etched, the second trench U2 is formed inside the N-type drift layer 3. Then, ion implantation is performed on the side of the N-type drift layer 3 exposed at the position of the second trench U2 close to the N+ substrate 1 to form an N+ drain region 4. Figure 3 The structure shown is Figure 1 Compared to the structure shown, Figure 3 The structure shown in FIG2 removes the N-type buffer layer, which can reduce one epitaxial growth. Moreover, since the drain conductive layer 5 is in direct contact with the lower-doped N-type drift layer 3, the hole concentration stored in the N-type drift layer 3 is lower than that in the N-type drift layer 3 when the body diode of the device is turned on. Figure 1 The structure shown can be lowered to further reduce the reverse recovery charge during the reverse recovery process.

[0074] It should be noted that Figure 3 The structure shown and Figure 1 Compared with the structure shown in FIG, except that the N-type buffer layer is removed and the second trench U2 is formed by directly etching the N+ substrate 1 to the inside of the N-type drift layer 3, the rest of the structure is the same. For details, please refer to the above description. Figure 1 Description of the structure shown.

[0075] In some embodiments, the material of the N+ substrate in the present disclosure can be single crystal silicon, silicon carbide or gallium nitride, that is, the metal oxide semiconductor field effect transistor provided in the embodiment of the present disclosure can be based on semiconductor materials such as single crystal silicon, silicon carbide or gallium nitride, and can be prepared through processes such as epitaxy and ion implantation.

[0076] In some embodiments, in the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure, as Figure 1-Figure 3 As shown, the gate structure and the source conductive layer 12 can be called the front structure of the metal oxide semiconductor field effect transistor, and the drain conductive layer 5 can be called the back structure of the metal oxide semiconductor field effect transistor. The front structure of the device and the drain conductive layer 5 may not be in a one-to-one correspondence. For example, one drain conductive layer 5 may correspond to multiple repeated front structures.

[0077] It should be noted that the thickness of each region, the type of doped ions, and the ion doping concentration in the metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure can be designed as needed.

[0078] Based on the same inventive concept, an embodiment of the present disclosure provides a method for preparing the above-mentioned metal oxide semiconductor field effect transistor. Since the principle of solving the problem by the preparation method is similar to the principle of solving the problem by the above-mentioned metal oxide semiconductor field effect transistor, the implementation of the preparation method provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned metal oxide semiconductor field effect transistor provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0079] In some embodiments, the method for preparing the metal oxide semiconductor field effect transistor provided in the embodiments of the present disclosure is as follows: Figure 6 As shown, this may include:

[0080] S601, epitaxially forming an N-type low-doped semiconductor layer and an N-type drift layer on one side of the N+ substrate;

[0081] S602, etching the N+ substrate and the N-type low-doped semiconductor layer to form a first trench penetrating the N+ substrate and a second trench penetrating the N-type low-doped semiconductor layer to expose the N-type drift layer;

[0082] S603, implanting N-type impurities into the exposed N-type drift layer near the N+ substrate to form an N+ drain region;

[0083] S604 , forming a drain conductive layer on a side of the N+ substrate away from the N-type drift layer, wherein the drain conductive layer fills the first trench and the second trench until it contacts the N+ drain region.

[0084] The method for preparing the above-mentioned metal oxide semiconductor field effect transistor provided in the embodiment of the present disclosure is to expose the N-type drift layer by trenching the N+ substrate and the N-type low-doped semiconductor layer, and then ion-implanting a high concentration of N-type impurities into the exposed N-type drift layer to form an N+ drain region, and then forming a drain conductive layer on the side of the N+ substrate away from the N-type drift layer. Through this method, the resistance of the N+ substrate can be completely eliminated, and a relatively thick N+ substrate can still be maintained to maintain the mechanical strength of the wafer. At the same time, the contact between the drain conductive layer and the lower-doped N-type low-doped semiconductor layer is conducive to the extraction of holes from this point when the body diode of the device is turned on, reducing the hole density in the N-type drift layer and reducing the reverse recovery charge.

[0085] In some embodiments, in the above-mentioned preparation method provided in the embodiment of the present disclosure, after performing step S601 to epitaxially form an N-type low-doped semiconductor layer and an N-type drift layer on one side of the N+ substrate, and before performing step S602 to etch the N+ substrate and the N-type low-doped semiconductor layer, as shown in FIG. Figure 7 As shown, the method further includes: S701, forming a P-type well region, an N+ source region, and a P+ source region by implanting corresponding N-type or P-type impurities on a side of the N-type drift layer away from the N+ substrate;

[0086] After performing step S603 to implant N-type impurities into the exposed N-type drift layer close to the N+ substrate to form an N+ drain region, and before performing step S604 to form a drain conductive layer on the side of the N+ substrate away from the N-type drift layer, Figure 7 As shown, it also includes:

[0087] S702, forming a gate dielectric layer on a side of the N-type drift layer away from the N+ substrate;

[0088] S703, forming a gate conductive layer on a side of the gate dielectric layer away from the N+ substrate;

[0089] S704, forming an isolation dielectric layer on a side of the gate conductive layer away from the N+ substrate;

[0090] S705 , forming a source conductive layer on a side of the isolation dielectric layer, the N+ source region, and the P+ source region away from the N+ substrate.

[0091] In order to better understand the above preparation method provided in the embodiment of the present disclosure, the present disclosure is based on Figure 1 Taking the metal oxide semiconductor field effect transistor shown in the figure as an example, the preparation process of the metal oxide semiconductor field effect transistor is described in detail.

[0092] In some embodiments, Figure 1 The preparation process of the metal oxide semiconductor field effect transistor may specifically include the following steps:

[0093] (1) Figure 8A As shown, an N+ substrate 1 is provided, and an N-type low-doped semiconductor layer 2 (ie, an N-type buffer layer) and an N-type drift layer 3 are epitaxially formed on one side of the N+ substrate 1 .

[0094] (2) Figure 8B As shown, a P-type well region 6 , an N+ source region 7 and a P+ source region 8 are formed on the side of the N-type drift layer 3 away from the N+ substrate 1 by implanting corresponding N-type or P-type impurities.

[0095] (3) Figure 8C As shown, a hard mask 20 is formed on a side of the N+ substrate 1 away from the N-type drift layer 3, and then selective etching is performed. The N+ substrate 1 and the N-type low-doped semiconductor layer 2 (i.e., the N-type buffer layer) are etched using a dry etching method, and the etching is stopped at the interface between the N-type low-doped semiconductor layer 2 (i.e., the N-type buffer layer) and the N-type drift layer 3 to form a first trench U1 penetrating the N+ substrate 1 and a second trench U2 penetrating the N-type buffer layer 2 to expose the N-type drift layer 3.

[0096] (4) Figure 8DAs shown, the hard mask is maintained, and N-type impurities (indicated by arrows) are implanted into the exposed N-type drift layer 3 near the N+ substrate 1 to form an N+ drain region 4. Subsequently, the hard mask 20 is stripped off. An annealing process is then performed to activate the implanted ions and repair lattice damage.

[0097] (5) Figure 8E As shown, a gate dielectric layer 9 is formed on the side of the N-type drift layer 3 away from the N+ substrate 1, a gate conductive layer 10 is formed on the side of the gate dielectric layer 9 away from the N+ substrate 1, an isolation dielectric layer 11 is formed on the side of the gate conductive layer 10 away from the N+ substrate 1, and a source conductive layer 12 is formed on the side of the isolation dielectric 11, the N+ source region 7 and the P+ source region 8 away from the N+ substrate 1.

[0098] (6) Figure 1 As shown, a drain conductive layer 5 is formed on a layer of the N+ substrate 1 away from the N-type drift layer 3 by sputtering. The drain conductive layer 5 fills the first trench U1 and the second trench U2 until it contacts the N+ drain region 4 .

[0099] Through the above steps (1)-(6) Figure 1 The metal oxide semiconductor field effect transistor is shown.

[0100] Need to explain yes, Figure 2 The preparation method of the metal oxide semiconductor field effect transistor shown is Figure 1 The preparation methods of the structures shown are basically the same, except that: Figure 2 When the structure shown in FIG. 1 is formed, in performing the above step (3), when etching the N+ substrate 1 and the N-type low-doped semiconductor layer 2 to form a first trench U1 penetrating the N+ substrate 1 and a second trench U2 penetrating the N-type low-doped semiconductor layer 2, the N-type drift layer 3 is simultaneously overetched to form a groove U3.

[0101] Need to explain yes, Figure 3 The preparation method of the metal oxide semiconductor field effect transistor shown is Figure 1 The preparation methods of the structures shown are basically the same, except that: Figure 3 In the structure shown, when performing the above step (1), the N-type drift layer 3 is epitaxially formed only on one side of the N+ substrate 1, and when performing the above step (3), the N-type drift layer 3 is also etched when etching the N+ substrate 1 to form the second trench U2.

[0102] It should be noted that in the above-mentioned preparation method provided in the embodiment of the present disclosure, the patterning process involved in forming each layer structure may include not only part or all of the process steps such as deposition, photoresist coating, masking, exposure, development, etching, photoresist stripping, etc., but may also include other process steps, which are subject to the formation of the desired patterned pattern in the actual production process and are not limited here. For example, a post-baking process may be included after development and before etching. Among them, the deposition process may be chemical vapor deposition, plasma enhanced chemical vapor deposition or physical vapor deposition, which are not limited here; the mask plate used in the masking process may be a half-tone mask plate (Half Tone Mask), a single slit diffraction mask plate (Single Slit Mask) or a gray tone mask plate (Gray Tone Mask), which are not limited here; etching may be dry etching or wet etching, which are not limited here.

[0103] Based on the same inventive concept, embodiments of the present disclosure provide an electronic device including the aforementioned metal oxide semiconductor field effect transistor provided in embodiments of the present disclosure. Because the principles underlying the problem solved by the electronic device are similar to those underlying the metal oxide semiconductor field effect transistor, the implementation of the electronic device provided in embodiments of the present disclosure can be referenced to the implementation of the metal oxide semiconductor field effect transistor provided in embodiments of the present disclosure, and any repetitions will not be repeated.

[0104] In some embodiments, the electronic devices provided by the embodiments of the present disclosure may include, but are not limited to, radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, and household appliances. Of course, in addition to metal oxide semiconductor field-effect transistors, the electronic devices provided by the present disclosure may also include other structures. For example, when the electronic device is a radar, it may also include structures such as a transmitter, antenna, and receiver; when the electronic device is a mixer, it may also include structures such as input ports, output ports, and so on.

[0105] The present disclosure provides a metal oxide semiconductor field effect transistor, a method for manufacturing the same, and an electronic device. A trench is dug in both the N+ substrate and the N-type low-doped semiconductor layer to expose the N-type drift layer. An N+ drain region doped with a high concentration of N-type impurities is formed on the side of the exposed N-type drift layer near the N+ substrate. The N+ drain region can reduce on-resistance and improve withstand voltage performance. Furthermore, the drain conductive layer fills the trench, so that the drain conductive layer contacts the side of the N+ substrate at the first trench position, the side of the N-type low-doped semiconductor layer at the second trench position, and the side of the N+ drain region near the N+ substrate. Therefore, the metal oxide semiconductor field effect transistor provided by the present disclosure can significantly reduce the resistance of the N+ substrate and can maintain a relatively thick N+ substrate without thinning the N+ substrate. Compared to the prior art method of thinning the N+ substrate, the present disclosure reduces the risk of fragmentation and maintains the mechanical strength of the wafer. At the same time, the drain conductive layer disclosed in the present invention is in direct contact with the N-type low-doped semiconductor layer, which is beneficial for holes to be extracted from the contact surface between the drain conductive layer and the N-type low-doped semiconductor layer when the body diode of the metal oxide semiconductor field effect transistor is turned on, thereby reducing the hole density in the N-type drift layer, and is beneficial for reducing the reverse recovery charge and reverse recovery current of the metal oxide semiconductor field effect transistor.

[0106] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0107] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A metal oxide semiconductor field effect transistor, characterized in that: include: An N+ substrate including a first trench extending through a thickness thereof; An N-type low-doped semiconductor layer is located on one side of the N+ substrate, wherein the N-type low-doped semiconductor layer includes a second trench extending through the thickness thereof, and the first trench and the second trench overlap; An N-type drift layer is located on a side of the N-type low-doped semiconductor layer away from the N+ substrate; an N+ drain region located in the N-type drift layer and on a side of the N-type drift layer close to the N+ substrate, wherein the N+ drain region covers the second trench; A drain conductive layer covers the side of the N+ substrate away from the N-type drift layer and fills the first trench and the second trench until they are in contact with the N+ drain region; the drain conductive layer is in contact with the side of the N-type low-doped semiconductor layer at the position of the second trench.

2. The metal oxide semiconductor field effect transistor according to claim 1, wherein The N+ drain region also covers a portion of the N-type low-doped semiconductor layer.

3. The metal oxide semiconductor field effect transistor according to claim 2, wherein: The N-type low-doped semiconductor layer is an N-type buffer layer.

4. The metal oxide semiconductor field effect transistor according to claim 3, wherein A side of the N+ drain region close to the N+ substrate contacts a side of the N-type buffer layer away from the N+ substrate.

5. The metal oxide semiconductor field effect transistor according to claim 3, wherein: The N-type drift layer has a groove running through part of its thickness on a side close to the N+ substrate and corresponding to the second trench. The groove overlaps with the second trench. The N-type drift layer is located between the N+ drain region and the N-type buffer layer.

6. The metal oxide semiconductor field effect transistor according to claim 2, wherein: The N-type low-doped semiconductor layer and the N-type drift layer are an integrated structure.

7. The metal oxide semiconductor field effect transistor according to any one of claims 1 to 6, characterized in that: Also includes: Two P-type well regions located in the N-type drift layer and adjacent to a side of the N-type drift layer away from the N+ substrate, and an N+ source region and a P+ source region located in the P-type well region and adjacent to a side of the N-type drift layer away from the N+ substrate; wherein the N+ source region and the P+ source region are laterally arranged and in contact with each other, and the P+ source region is disposed adjacent to a side of the N-type drift layer, and the P-type well region covers a side of the P+ source region and the N+ source region adjacent to the N+ substrate, as well as a side of the N+ source region away from the P+ source region; The present invention also includes: a gate dielectric layer located on a side of the N-type drift layer away from the N+ substrate, a gate conductive layer located on a side of the gate dielectric layer away from the N+ substrate, and an isolation dielectric layer located on a side of the gate conductive layer away from the N+ substrate; wherein the gate dielectric layer is in contact with the N-type drift layer, the P-type well region, and the N+ source region, and the isolation dielectric layer wraps around the gate conductive layer and is in contact with the gate dielectric layer; It also includes a source conductive layer located on the side of the isolation dielectric layer, the N+ source region and the P+ source region away from the N+ substrate. The source conductive layer wraps the isolation dielectric layer and contacts the N+ source region and the P+ source region.

8. A method for preparing a metal oxide semiconductor field effect transistor, characterized in that: For preparing the metal oxide semiconductor field effect transistor according to any one of claims 1 to 7, the preparation method comprises: Epitaxially forming an N-type low-doped semiconductor layer and an N-type drift layer on one side of the N+ substrate; Etching the N+ substrate and the N-type low-doped semiconductor layer to form a first trench penetrating the thickness of the N+ substrate and a second trench penetrating the thickness of the N-type low-doped semiconductor layer, so as to expose the N-type drift layer; Implanting N-type impurities into the exposed side of the N-type drift layer close to the N+ substrate to form an N+ drain region; A drain conductive layer is formed on a side of the N+ substrate away from the N-type drift layer, and the drain conductive layer fills the first trench and the second trench until it contacts the N+ drain region.

9. The preparation method according to claim 8, wherein When etching the N+ substrate and the N-type low-doped semiconductor layer to form a first trench penetrating the thickness of the N+ substrate and a second trench penetrating the thickness of the N-type low-doped semiconductor layer, the method further includes: A groove is formed by over-etching into the N-type drift layer.

10. The preparation method according to claim 8, characterized in that After epitaxially forming an N-type low-doped semiconductor layer and an N-type drift layer on one side of the N+ substrate, and before etching the N+ substrate and the N-type low-doped semiconductor layer, the method further comprises: forming a P-type well region, an N+ source region, and a P+ source region on a side of the N-type drift layer away from the N+ substrate by implanting corresponding N-type or P-type impurities; After implanting N-type impurities into the exposed N-type drift layer on a side close to the N+ substrate to form an N+ drain region, and before forming a drain conductive layer on a side of the N+ substrate away from the N-type drift layer, the method further includes: forming a gate dielectric layer on a side of the N-type drift layer away from the N+ substrate; forming a gate conductive layer on a side of the gate dielectric layer away from the N+ substrate; forming an isolation dielectric layer on a side of the gate conductive layer away from the N+ substrate; A source conductive layer is formed on a side of the isolation dielectric layer, the N+ source region, and the P+ source region away from the N+ substrate.

11. An electronic device, characterized in that: The method comprises the metal oxide semiconductor field effect transistor according to any one of claims 1 to 7.

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