SGT device with low conduction impedance and preparation method thereof

Abstract

The invention discloses a low-conduction-impedance SGT device and a preparation method thereof, and the device comprises a substrate, an epitaxial layer formed above the substrate, a drain electrode formed below the substrate, a dielectric layer formed above the epitaxial layer, a source electrode formed above the dielectric layer, and parallel groove groups which are recessed downwards in the epitaxial layer. The first grid electrode is formed in each groove in a deposition mode, the original grid electrode is formed above the first grid electrode in a deposition mode, and a second grid electrode which partially stretches across the groove group and is connected with the original grid electrode in the groove group is formed between at least one adjacent groove group in the groove group. According to the invention, the vertical groove is further introduced between the original parallel grooves, and the groove gate structure crossing the two adjacent grooves is formed in the vertical groove, so that the channel density of the whole device is further improved, and the purpose of further reducing the characteristic impedance is achieved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductors, and in particular relates to a SGT device with low on-resistance and a preparation method thereof. Background Art

[0002] Shielded gate trench power MOSFET is also called insulated gate field effect transistor, or SGT-MOS for short, which is an abbreviation of Split Gate Trench-MOSFET. The SGT-MOS series products adopt the shielded gate deep trench (Split Gate Trench) technology with charge balancing function, which comprehensively improves the switching characteristics and conduction characteristics of the device, and reduces the characteristic on-resistance (Rsp) and gate charge (Qg) of the device. Insulated gate field effect transistors are widely used in various power systems because of their advantages such as fast switching speed, low power consumption, easy gate drive, low drive power, high input impedance and good frequency response. SGT-MOS is widely used in medium and low voltage power systems because of its excellent specific on-resistance and switch conduction figure of merit. SGT-MOS uses the shielded gate to modulate the longitudinal electric field distribution in the epitaxial layer by lateral depletion of the epitaxial layer, thereby improving the avalanche characteristics of the device.

[0003] At present, in order to reduce the characteristic impedance, SGT devices will increase the channel density. There are two main methods to increase the channel density: one is to reduce the size of the device cell, and the other is to shorten the channel length. However, due to material factors and process capabilities, these two methods are limited and cannot further significantly improve the device channel density. Summary of the invention

[0004] The object of the present invention is to provide a low on-resistance SGT device and a preparation method thereof which further improves channel density and reduces impedance.

[0005] The present invention provides a low on-resistance SGT device, comprising a substrate, an epitaxial layer formed above the substrate and a drain formed below the substrate, a dielectric layer formed above the epitaxial layer, and a source formed above the dielectric layer, a plurality of parallel groove groups formed by etching depressions downward on the epitaxial layer, a first gate deposited in each groove and an original gate deposited above the first gate, a second gate partially spanning the group of grooves and connected to the original gates in the group of grooves is formed between at least one group of adjacent grooves in the groove group, the second gate is deposited integrally with the original gate to form a total gate, and the total gate is isolated from the first gate.

[0006] As a further improvement of the present invention, a second gate that partially spans and connects the group of grooves is formed between the N+1th row of grooves and the adjacent N+2th row of grooves in the groove group, or a second gate that partially spans and connects the group of grooves is formed between the 2N+1th row of grooves and the adjacent 2N+2th row of grooves in the groove group, where N is a natural number.

[0007] As a further improvement of the present invention, the SGT device with low on-resistance includes a doping layer formed by doping on the substrate, the doping layer is interposed between adjacent trenches, and the thickness of the doping layer is consistent with the thickness of the second gate.

[0008] As a further improvement of the present invention, the second gate separates the doped layers between the adjacent N+1th row of grooves and the N+2th row of grooves or separates the doped layers between the adjacent 2N+1th row of grooves and the 2N+2th row of grooves to form a row of rectangular areas.

[0009] As a further improvement of the present invention, when a second gate that partially spans and connects the group of grooves is formed between the N+1th row of grooves and its adjacent N+2th row of grooves in the groove group, a row of rectangular doped layers formed between the N+1th row of grooves and the N+2th row of grooves and a row of rectangular doped layers formed between the N+2th row of grooves and the N+3th row of grooves are arranged at intervals along the cross-connection direction of the second gate.

[0010] As a further improvement of the present invention, when a second gate that partially spans and connects the group of grooves is formed between the 2N+1 row of grooves and the adjacent 2N+2 row of grooves in the groove group, a row of rectangular doped layers formed between the 2N+1 row of grooves and the 2N+2 row of grooves and a row of rectangular doped layers formed between the 2N+3 row of grooves and the 2N+4 row of grooves are arranged in a collinear manner or at intervals along the cross-connection direction of the second gate.

[0011] The present invention also provides a method for preparing a SGT device with low on-resistance, comprising the following steps: S1, preparing a substrate, growing an epitaxial layer on the upper surface of the substrate, depositing a hard mask on the upper surface of the epitaxial layer, and etching downward on the hard mask to form a plurality of parallel groove groups; S2, selecting a group of adjacent grooves in the groove group, and etching the common groove wall portion in the middle of the group of grooves downward to form a recessed area; S3, forming a dielectric layer on the inner wall surface of the trench, depositing polysilicon in the trench after rapid annealing, etching the polysilicon beyond the upper surface position of the recessed area back to below the upper surface position of the recessed area to form a first gate, and etching and depositing again on the inner wall surface of the trench and above the first gate to form a dielectric layer; S4, depositing polysilicon on the upper surface of the dielectric layer above the first gate to form a total gate, implanting impurities downward into the trench wall region that has not been etched downward for doping, and then depositing a dielectric layer above the entire device; S5. Etching oxide in the doped area to form a through hole, depositing metal in the through hole to form an electrode, depositing a passivation layer, and etching to form a source and gate contact area, thinning the substrate, and forming a drain under the substrate.

[0012] As a further improvement of the present invention, the plane height of the lower surface of the recessed area is between the upper surface of the groove wall and the bottom of the groove.

[0013] As a further improvement of the present invention, the dielectric layer isolates the first gate, the second gate, the trench sidewall, and the source from each other.

[0014] As a further improvement of the present invention, the total gate includes a second gate that partially spans the N+1th row of grooves and the adjacent N+2th row of grooves, and an original gate that is separately formed between the N+1th row of grooves and the adjacent N+2th row of grooves, or includes a second gate that partially spans the 2N+1th row of grooves and the adjacent 2N+2th row of grooves, and an original gate that is separately formed between the 2N+1th row of grooves and the adjacent 2N+2th row of grooves.

[0015] Beneficial Effects of the Invention The present invention introduces an additional trench structure between two adjacent trenches, further introduces a vertical trench in the middle of the original parallel trenches, and forms a trench gate structure spanning two adjacent trenches in the vertical trench, thereby further improving the channel density of the entire device and achieving the purpose of further reducing the characteristic impedance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic cross-sectional diagram of each level of the SGT device in the prior art; Figure 2 It is a schematic cross-sectional diagram of each layer of a low on-resistance SGT device of the present invention; Figure 3 is along Figure 2 A schematic diagram of a design structure of the total grid after horizontal sectioning toward A in the middle direction; Figure 4 is along Figure 2 A schematic diagram of another design structure of the main grid after horizontal sectioning toward A in the middle direction; Figure 5 is along Figure 4 Schematic diagram of the shape of the groove wall after longitudinal sectioning toward B; Figure 6 It is a simplified schematic diagram of several total gate structures in the present invention; Figure 7 The present invention is a flow chart of a method for preparing a low on-resistance SGT device. DETAILED DESCRIPTION

[0017] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the examples of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the examples of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all embodiments. The embodiments of the present invention and all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present invention.

[0018] like Figure 1 As shown, it is a schematic cross-sectional view of the internal structure of an existing SGT device, which includes a drain 101, a substrate 102, an epitaxial layer 103, a dielectric layer 104, and a source 105 from bottom to top, wherein a plurality of parallel trenches 106 are formed by etching from top to bottom in the epitaxial layer, a shielding gate 107 is deposited at the bottom of the trench, and an original gate 108 is deposited above the trench. Impurities are injected into the upper region between the trenches near the gate to form two doping layers 109, and the source electrode 110 is deeply buried in the doping layer, while the gate and the shielding gate, the gate and the source, and the gate, the shielding gate and the substrate are isolated by the dielectric layer. It is difficult to make further breakthroughs after the density of the channel reaches a critical value under this structure.

[0019] In order to further increase the channel density and reduce the characteristic impedance, this embodiment provides a low on-resistance SGT device, such as Figure 2-6 As shown, it includes a substrate 201, an epitaxial layer 202 formed on the substrate 201 and a drain 203 formed below the substrate 201, a dielectric layer 204 formed on the epitaxial layer 202, and a source 205 formed on the dielectric layer 204, a plurality of parallel groove groups 206 formed by being recessed downward on the epitaxial layer 202, a first gate 207 deposited in each groove and an original gate 108 deposited above the first gate 207, a second gate 208 partially spanning the group of grooves and connected to the original gate in the group of grooves is formed between at least one group of adjacent grooves in the groove group, the second gate 208 is deposited integrally with the original gate 108 to form a total gate, and the total gate is isolated from the first gate 207.

[0020] Through the above structural design, in addition to the existing longitudinally parallel arranged groove groups, transverse grooves are added between any selected adjacent group of grooves, so that the gate portion area originally independently formed in the middle of each groove forms a connection spanning two adjacent grooves.

[0021] Of course, not all adjacent trenches can be connected with transverse trenches. As a preferred design scheme of the first overall gate in the present invention, Figure 4 , a second gate partially spanning and connecting the group of grooves is formed between the 2N+1th row of grooves and the adjacent 2N+2th row of grooves in the groove group, where N is a natural number. Specifically, the first row and the second row of grooves are selected from left to right as the first group of adjacent grooves, a transverse groove is added between the first group of grooves, and a gate partially spanning the first and second rows of grooves is formed in the transverse grooves, and then the third and fourth rows of grooves are selected as the second group of adjacent grooves, and a gate partially spanning the third and fourth rows of grooves is formed in the transverse grooves, and so on.

[0022] As a second preferred design scheme of the overall gate in the present invention, Figure 3 , you can also choose to form a second gate that partially spans and connects the group of grooves between the N+1th row of grooves and the adjacent N+2th row of grooves, where N is a natural number. Specifically, the first row and the second row of grooves are selected from left to right as the first group of adjacent grooves, and a transverse groove is added between the first group of grooves. Then, a gate that partially spans the first and second rows of grooves is formed in the transverse grooves. Then, the second and third rows of grooves are selected as the second group of adjacent grooves, and then a gate that partially spans the second and third rows of grooves is formed in the transverse grooves, and so on. However, in this design, the transverse gates in the first and second rows and the transverse gates in the second and third rows cannot be collinear in arrangement, and need to be staggered from each other, otherwise a gate structure spanning the first, second, and third rows will be directly formed. Obviously, this is not the original intention of this design.

[0023] However, in specific design application scenarios, it is not necessarily limited to the above design methods, such as Figure 6 , the figure shows three feasible design methods, where the vertical line is a simplified schematic diagram of the original gate arrangement, and the horizontal line is a simplified schematic diagram of the second gate arrangement.

[0024] The low on-resistance SGT device includes a doping layer 209 formed by doping on the substrate, the doping layer 209 is between adjacent trenches, and the thickness of the doping layer 209 is consistent with the thickness of the second gate 208. In order to maintain the best conduction characteristics, in the doping process, P-type impurities are firstly injected above the substrate adjacent to the trenches to form a P-type body region, and then N-type impurities are injected to form an N-type heavy parameter active region. The thickness of the doping region formed by the two dopings is basically consistent with the thickness of the second gate, so that the best conduction performance can be achieved.

[0025] In this embodiment, since the second gate 208 is partially across, as shown in Figure 2-6, the adjacent shared side wall in the middle is only partially etched downward, and the unetched area still forms a doped layer for contacting and connecting with the source. Therefore, although the density of the channel is increased, the contact density between the source and the doped layer is still retained in essence.

[0026] In the first preferred design of the overall gate, Figure 4 , the second gate 208 forms a row of rectangular areas 211 by spacing the doping layers between the adjacent 2N+1 row of grooves and the 2N+2 row of grooves. In order to further optimize the conduction characteristics and characteristic impedance of the entire device, the row of rectangular doping layers formed between the 2N+1 row of grooves and the 2N+2 row of grooves and the row of rectangular doping layers formed between the 2N+3 row of grooves and the 2N+4 row of grooves are arranged at intervals along the cross-connection direction of the second gate. Of course, in specific application designs, the reserved doping layer area is not necessarily rectangular, but can also be other shapes, and is not a row, but can be a whole area with a certain percentage reserved as a whole. In addition, it is not necessary to be arranged at intervals, and can also be arranged in a colinear manner, and this is not the only limitation.

[0027] In the second preferred design of the overall gate, Figure 3 The second gate 208 forms a row of rectangular areas 211 by spacing the doping layers between the adjacent N+1th row of grooves and the N+2th row of grooves. The row of rectangular doping layers formed between the N+1th row of grooves and the N+2th row of grooves and the row of rectangular doping layers formed between the N+2th row of grooves and the N+3th row of grooves are arranged at intervals along the horizontal connection direction of the second gate. The design here is to avoid direct contact and connection between the horizontal gate between the N+1th row of grooves and the N+2th row of grooves and the gate between the N+2th row of grooves and the N+3th row of grooves to directly form a gate spanning three rows of grooves. Obviously, this situation cannot maximize the groove density and is not the original intention of this design.

[0028] In order to better illustrate the technical effect of the present invention, this embodiment also provides a method for preparing a SGT device with low on-resistance, such as Figure 7 As shown, the following steps are included: S1. Prepare a substrate, grow an epitaxial layer on the upper surface of the substrate, deposit a hard mask on the upper surface of the epitaxial layer, and etch downward on the hard mask to form a plurality of parallel grooves.

[0029] This step is a mature process step. The several rows of parallel grooves formed by etching are usually U-shaped grooves, which will not be described in detail here.

[0030] S2, selecting a group of adjacent grooves in the groove group, and etching the common groove wall portion in the middle of the group of grooves downward to form a recessed area 212.

[0031] For example, in the preferred design of the first total gate in this embodiment, the first and second rows of grooves are selected from left to right as the first group of adjacent grooves, and the groove wall shared by this group of grooves is used as the object to be further etched, and partially etched downward to form a recessed area, and the plane height of the lower surface of the recessed area is between the upper surface of the groove wall and the bottom of the groove. In the specific etching process, there can be multiple recessed areas here, and each recessed area is not connected. At the same time, the third and fourth rows of grooves are selected as the second group of adjacent grooves, and the groove wall shared by this group of grooves is used as the object to be further etched, and partially etched downward to form a recessed area, and so on.

[0032] Taking the second preferred design scheme of the total gate in this embodiment as an example, the first row and the second row of grooves are selected from left to right as the first group of adjacent grooves, and the groove wall shared by this group of grooves is used as the object to be further etched, and partially etched downward to form a recessed area, and the plane height of the lower surface of the recessed area is between the upper surface of the groove wall and the bottom of the groove. At the same time, the second row and the third row of grooves are selected as the second group of adjacent grooves, and the groove wall shared by this group of grooves is used as the object to be further etched, and partially etched downward to form a recessed area, and so on. However, in this scheme, the recessed area etched downward by the groove wall shared by the first and second rows of grooves cannot be colinear with the recessed area etched downward by the groove wall shared by the second and third rows of grooves, or there is a lateral overlap area, and the etching needs to be staggered, otherwise the lateral second gate will partially directly form a straight line directly across multiple grooves, which is obviously not conducive to maximizing the channel density.

[0033] In this embodiment, the recessed area selected to be etched downward again can be completed at one time, and it is only necessary to pre-design the position of the recessed area.

[0034] S3, forming a dielectric layer on the inner wall surface of the trench, depositing polysilicon in the trench after rapid annealing, etching the polysilicon beyond the upper surface position of the recessed area back to below the upper surface position of the recessed area to form a first gate, and etching and depositing again on the inner wall surface of the trench and above the first gate to form a dielectric layer; In order to isolate the gate, the introduction of a dielectric layer is a necessary process step. Generally, an oxide layer and a dielectric layer are formed by Thermal (thermal oxidation process) and CVD (chemical vapor deposition). This process is also a mature process and will not be described here. In SGT devices, in order to maximize the role of the first gate, that is, the shielding gate, it is preferred to be deposited deep in the lower part of the channel. Therefore, after depositing polysilicon, it is necessary to etch back so that the height of the shielding gate does not exceed the bottom horizontal plane of the recessed area. After the etching is completed, a dielectric oxide layer is added on the sidewalls of the trench and above the shielding gate for isolation. At this step, the surface of the recessed area and the sidewall surface between the 2N+1 row of trenches and the 2N+2 row of trenches have completed the isolation of the dielectric layer, and the trench walls that have not been etched down to form a recessed area have also completed the isolation of the dielectric layer.

[0035] S4, depositing polysilicon on the upper surface of the dielectric layer above the first gate to form a total gate, implanting impurities downward into the trench wall region that has not been etched downward for doping, and then depositing a dielectric layer above the entire device.

[0036] In this embodiment, the total gate includes a second gate that partially spans the N+1th row of grooves and the adjacent N+2th row of grooves, and an original gate that is separately formed between the N+1th row of grooves and the adjacent N+2th row of grooves, or includes a second gate that partially spans the 2N+1th row of grooves and the adjacent 2N+2th row of grooves, and an original gate that is separately formed between the 2N+1th row of grooves and the adjacent 2N+2th row of grooves.

[0037] The original gate is the gate of the SGT device that is entirely deposited in the groove in the prior art, and the second gate is a newly designed gate structure that is formed in the recessed area and partially spans the 2N+1 row of grooves and the 2N+2 row of grooves adjacent to it in the preferred design scheme of the first total gate in the present invention, or is a newly designed gate structure that is formed in the recessed area and partially spans the N+1 row of grooves and the N+2 row of grooves adjacent to it in the preferred design scheme of the second total gate.

[0038] The groove wall area that is not etched downwards includes the upper surface area of ​​the groove wall shared by the 2N+1 row of grooves and the adjacent 2N+2 row of grooves in the first preferred design of the total gate that is not etched downwards and the upper surface area of ​​the groove wall that is not shared by the 2N+1 row of grooves and the adjacent 2N+2 row of grooves on the other two sides, or the upper surface area of ​​the groove wall shared by the N+1 row of grooves and the adjacent N+2 row of grooves in the second preferred design of the total gate that is not etched downwards. The area is doped to form a doping layer, which is defined from another dimension as being between adjacent grooves, and the thickness of the doping layer is consistent with the thickness of the second gate. In order to maintain the best conduction characteristics, in the process of doping, P-type impurities are first injected above the adjacent substrate between the grooves to form a P-type body region, and then N-type impurities are injected to form an N-type re-parameterized active region. The thickness of the doping region formed by the two dopings is basically consistent with the thickness of the second gate, so that the best conduction performance can be achieved. After the doping is completed, a dielectric layer is deposited again on the entire upper surface of the device. At this time, the entire dielectric layer isolates the first gate, the main gate, the trench sidewall, and the source from each other.

[0039] S5. Etching oxide in the doped area to form a through hole, depositing metal in the through hole to form an electrode, depositing a passivation layer, and etching to form a source and gate contact area, thinning the substrate, and forming a drain under the substrate.

[0040] After step S4 is completed, the remaining process steps are conventional processes, that is, the electrode 210 is introduced, then the source is formed after passivation, and finally the substrate is thinned to the designed thickness and the drain is formed on the bottom surface, i.e., the back surface. At this point, the SGT device with low on-resistance provided by the present invention is prepared.

[0041] The present invention introduces an additional trench structure between two adjacent trenches, further introduces a vertical trench in the middle of the original parallel trenches, and forms a trench gate structure spanning two adjacent trenches in the vertical trench, thereby further improving the channel density of the entire device and achieving the purpose of further reducing the characteristic impedance.

[0042] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0043] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A low on-resistance SGT device, comprising a substrate, an epitaxial layer formed on the substrate, a drain formed below the substrate, a dielectric layer formed above the epitaxial layer, and a source formed above the dielectric layer, a plurality of parallel groove groups formed by etching depressions downward on the epitaxial layer, a first gate deposited in each groove, and an original gate deposited above the first gate, characterized in that: A second gate is formed between at least one adjacent group of grooves in the groove group, partially spanning the group of grooves and connected to the original gate in the group of grooves. The second gate is deposited integrally with the original gate to form a total gate, and the total gate is isolated from the first gate.

2. The low on-resistance SGT device according to claim 1, characterized in that: A second gate that partially spans and connects the group of grooves is formed between the N+1th row of grooves and its adjacent N+2th row of grooves in the groove group, or a second gate that partially spans and connects the group of grooves is formed between the 2N+1th row of grooves and its adjacent 2N+2th row of grooves in the groove group, where N is a natural number.

3. The SGT device with low on-resistance according to claim 2, characterized in that: The low on-resistance SGT device includes a doping layer formed by doping on a substrate, the doping layer is located between adjacent trenches, and the thickness of the doping layer is consistent with the thickness of the second gate.

4. The SGT device with low on-resistance according to claim 3, characterized in that: The second gate separates the doped layers between the adjacent N+1th row of grooves and the N+2th row of grooves or separates the doped layers between the adjacent 2N+1th row of grooves and the 2N+2th row of grooves to form a row of rectangular areas.

5. The SGT device with low on-resistance according to claim 4, characterized in that: When a second gate that partially spans and connects the group of grooves is formed between the N+1th row of grooves and its adjacent N+2th row of grooves in the groove group, a row of rectangular doped layers formed between the N+1th row of grooves and the N+2th row of grooves and a row of rectangular doped layers formed between the N+2th row of grooves and the N+3th row of grooves are arranged at intervals along the direction in which the second gate spans and connects.

6. The SGT device with low on-resistance according to claim 4, characterized in that: When a second gate that partially spans and connects the group of grooves is formed between the 2N+1 row of grooves and the adjacent 2N+2 row of grooves in the groove group, a row of rectangular doped layers formed between the 2N+1 row of grooves and the 2N+2 row of grooves and a row of rectangular doped layers formed between the 2N+3 row of grooves and the 2N+4 row of grooves are arranged in a collinear manner or at intervals along the cross-connection direction of the second gate.

7. A method for preparing a low on-resistance SGT device, characterized in that: The following steps are included: S1, preparing a substrate, growing an epitaxial layer on the upper surface of the substrate, depositing a hard mask on the upper surface of the epitaxial layer, and etching downward on the hard mask to form a plurality of parallel groove groups; S2, selecting a group of adjacent grooves in the groove group, and etching the common groove wall portion in the middle of the group of grooves downward to form a recessed area; S3, forming a dielectric layer on the inner wall surface of the trench, depositing polysilicon in the trench after rapid annealing, etching the polysilicon beyond the upper surface position of the recessed area back to below the upper surface position of the recessed area to form a first gate, and etching and depositing again on the inner wall surface of the trench and above the first gate to form a dielectric layer; S4, depositing polysilicon on the upper surface of the dielectric layer above the first gate to form a total gate, implanting impurities downward into the trench wall region that has not been etched downward for doping, and then depositing a dielectric layer above the entire device; S5. Etching oxide in the doped area to form a through hole, depositing metal in the through hole to form an electrode, depositing a passivation layer, and etching to form a source and gate contact area, thinning the substrate, and forming a drain under the substrate.

8. The method for preparing a low on-resistance SGT device according to claim 7, characterized in that: The plane height of the lower surface of the recessed area is between the upper surface of the groove wall and the bottom of the groove.

9. The method for preparing a low on-resistance SGT device according to claim 7, characterized in that: The dielectric layer isolates the first gate, the second gate, the trench sidewall, and the source from each other.

10. The method for preparing a low on-resistance SGT device according to claim 7, characterized in that: The total gate includes a second gate that partially spans the N+1th row of grooves and the adjacent N+2th row of grooves, and an original gate that is separately formed between the N+1th row of grooves and the adjacent N+2th row of grooves, or includes a second gate that partially spans the 2N+1th row of grooves and the adjacent 2N+2th row of grooves, and an original gate that is separately formed between the 2N+1th row of grooves and the adjacent 2N+2th row of grooves.

Images