Preparation method of flip stacked transistor, transistor, device and equipment

Abstract

The invention provides a preparation method of an inverted stacked transistor, a transistor, a device and equipment. The preparation method comprises the following steps: forming a first semiconductor structure and a second semiconductor structure which are sequentially stacked on a substrate; etching the first semiconductor structure and the second semiconductor structure in the source-drain region, and filling an insulating material in the first source-drain region corresponding to the first semiconductor structure to form a filling structure; a third semiconductor structure is formed based on the second semiconductor structure through the previous process, and the third semiconductor structure comprises a first source drain structure; reversing and removing the substrate and the filling structure to expose the first semiconductor structure, forming a fourth semiconductor structure based on the first semiconductor structure, the fourth semiconductor structure at least comprising a second source-drain structure; based on the third semiconductor structure and the fourth semiconductor structure, a first transistor and a second transistor are formed through multiple times of chip reversing respectively. According to the invention, the thermal budget of the whole device preparation process is improved through a multi-time wafer reversing mode.

Description

Technical Field

[0001] The present application relates to the field of integrated semiconductors, and in particular to a method for preparing a flip-chip stacked transistor, a transistor, a device and equipment. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] In the related art, the process of preparing stacked transistors adopts a monolithic solution or a sequential solution, both of which have the problem of high difficulty and complexity in the preparation process. Therefore, in order to simplify the process flow and reduce the difficulty of preparation, the preparation process of stacked transistors still needs to be improved. Summary of the invention

[0004] The present application provides a method for preparing a flip-chip stacked transistor, a transistor, a device and an apparatus, which can improve the thermal budget in the overall device preparation process.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a stacked transistor, the method comprising: forming a first semiconductor structure and a second semiconductor structure on a substrate, the first semiconductor structure being closer to the substrate relative to the second semiconductor structure; forming a first part of a first transistor based on the second semiconductor structure, the first part comprising a first source-drain structure; flipping the first part and exposing the first semiconductor structure; forming a second transistor based on the first semiconductor structure, the second transistor comprising at least a second source-drain structure and a gate structure; flipping the second transistor and exposing the first source-drain structure; forming a second part of the first transistor based on the first source-drain structure, the second part comprising at least a first source-drain metal.

[0006] In some possible embodiments, a second transistor is formed based on the first semiconductor structure, including: epitaxially growing a second source-drain structure on the first semiconductor structure; forming a gate structure based on the first semiconductor structure; depositing a metal material on the second source-drain structure to form a second source-drain metal; performing back-end interconnection on the second source-drain metal to form a metal interconnection layer of the second transistor; and forming a second part of the first transistor based on the first source-drain structure, including: depositing a metal material on the first source-drain structure to form a first source-drain metal; performing back-end interconnection on the first source-drain metal to form a metal interconnection layer of the first transistor.

[0007] In some possible embodiments, a second transistor is formed based on a first semiconductor structure, including: epitaxially growing a second source-drain structure on the first semiconductor structure; forming a gate structure based on the first semiconductor structure; forming a second part of the first transistor based on the first source-drain structure, including: depositing a metal material on the first source-drain structure to form a first source-drain metal; performing back-end interconnection on the first source-drain metal to form a metal interconnection layer of the first transistor; after forming the metal interconnection layer of the first transistor, the method further includes: flipping the first transistor and exposing the second source-drain structure; forming a second source-drain metal based on the second source-drain structure; performing back-end interconnection on the second source-drain metal to form a metal interconnection layer of the second transistor.

[0008] In some possible embodiments, before forming the first part of the first transistor based on the second semiconductor structure, the method also includes: forming an isolation structure on the substrate to expose the first semiconductor structure and the second semiconductor structure; depositing semiconductor material on the isolation structure to form a dummy gate structure surrounding the first semiconductor structure and the second semiconductor structure; forming a second transistor based on the first semiconductor structure, including: removing the dummy gate structure to form a first gate structure of the first transistor and a second gate structure of the second transistor, respectively.

[0009] In some possible embodiments, before forming the first part of the first transistor based on the second semiconductor structure, the method also includes: forming an isolation structure on the substrate to expose the first semiconductor structure and the second semiconductor structure; depositing semiconductor material on the isolation structure to form a first dummy gate structure surrounding the first semiconductor structure; forming a gate isolation structure on the first dummy gate structure; depositing semiconductor material on the gate isolation structure to form a second dummy gate structure surrounding the second semiconductor structure; forming a second transistor based on the first semiconductor structure, including: removing the first dummy gate structure to form a second gate structure; forming a second part of the first transistor based on the first source-drain structure, including: removing the second dummy gate structure to form the first gate structure of the first transistor.

[0010] In some possible embodiments, based on the second active structure, a first part of the first transistor is formed, including: etching the first semiconductor structure and the second semiconductor structure in the source and drain region, and filling the first source and drain region with an insulating material to form a filling structure, the source and drain region including a first source and drain region and a second source and drain region, the first source and drain region corresponding to the first semiconductor structure, and the second source and drain region corresponding to the second semiconductor structure; based on the second source and drain region, a first source and drain structure is formed.

[0011] In some possible implementations, exposing the first semiconductor structure includes: removing the substrate; and filling the structure by selectively etching the material to expose the first source and drain region and the first semiconductor structure.

[0012] In a second aspect, an embodiment of the present application provides a flip-chip stacked transistor, which is manufactured using a method as described in the first aspect and any of its embodiments, and includes: a first transistor; a second transistor, wherein the second semiconductor structure of the first transistor is self-aligned with the first semiconductor structure of the second transistor.

[0013] In a third aspect, an embodiment of the present application provides a semiconductor device, comprising: a flip-chip stacked transistor as described in the second aspect above.

[0014] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the third aspect above, wherein the semiconductor device is arranged on the circuit board.

[0015] The technical solution provided by this application may have the following beneficial effects:

[0016] In an embodiment of the present application, a first semiconductor structure and a second semiconductor structure stacked in sequence are formed on a substrate, the first semiconductor structure and the second semiconductor structure located in the source-drain region are etched, and an insulating material is filled in the first source-drain region corresponding to the first semiconductor structure to form a filling structure, and the filling structure covers the source-drain region of the back transistor; through a front-end process, a third semiconductor structure including a first source-drain structure is formed based on the second semiconductor structure, and then the substrate and the filling structure are reversed and removed to expose the first semiconductor structure; based on the first semiconductor structure, a fourth semiconductor structure including at least a second source-drain structure is formed, and then based on the third semiconductor structure and the fourth semiconductor structure, a first transistor (front transistor) and a second transistor (back transistor) are formed respectively. Therefore, the embodiment of the present application decomposes the preparation process of the flip-chip stacked transistor into multiple stages, and only a partial heat treatment is performed in each stage. In this way, the impact of a single heat treatment on the device will be reduced, thereby improving the overall thermal budget; and by changing the preparation order of the flip-chip stacked transistor device, the impact of the heat treatment on the device performance can be further reduced, thereby improving the thermal budget; further, since the filling structure is used to locate the source and drain regions where the back transistor is located, when preparing the back transistor, there is no need to select the area through photolithography, and the filling structure can be directly etched to open the source and drain regions corresponding to the back transistor, so that a back transistor that is completely self-aligned with the front transistor can be prepared.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] Figure 1 It is a schematic diagram of an implementation process of a method for preparing a flip-chip stacked transistor in an embodiment of the present application;

[0020] Figure 2 A schematic top view of a flip-chip stacked transistor in an embodiment of the present application;

[0021] FIG. 3A to FIG. 3J This is a schematic structural diagram of a flip-chip stack transistor in a first preparation process according to an embodiment of the present application;

[0022] Figure 3K A schematic diagram of a first structure of a flip-chip stack transistor according to an embodiment of the present application;

[0023] FIG. 4A to FIG. 4G This is a schematic structural diagram of a flip-chip stack transistor in a second preparation process according to an embodiment of the present application;

[0024] Figure 4H A second structural schematic diagram of a flip-chip stack transistor according to an embodiment of the present application;

[0025] FIG. 5A to FIG. 5I A schematic diagram of the structure of a flip-chip stack transistor in a third preparation process according to an embodiment of the present application;

[0026] Figure 5J A third structural schematic diagram of the flip-chip stack transistor according to an embodiment of the present application;

[0027] 6A to 6H It is a schematic structural diagram of a flip-chip stack transistor in a fourth preparation process according to an embodiment of the present application;

[0028] Fig.6I This is a fourth structural schematic diagram of the flip-chip stacked transistor according to an embodiment of the present application.

[0029] The above pictures:

[0030] 10. Flip-chip stacked transistor; 11. First transistor (front transistor); 111. First nanosheet structure; 112. First source-drain structure; 113. First interlayer dielectric layer; 114. First gate structure; 1141. First gate dielectric layer; 1142. First gate electrode layer; 115. First source-drain metal; 116. First metal interconnect layer; 12. Second transistor; 121. Second nanosheet structure; 122. Second source-drain structure; 123. Second interlayer dielectric layer; 124. Second gate structure; 1241. Second gate dielectric layer; 1242. Second gate electrode layer; 125. Second source-drain metal; 126. Second metal interconnect layer; 13. First insulating layer; 14. First carrier wafer; 15. Second insulating layer; 16. Second carrier wafer Wafer; 17, third insulating layer; 18, third carrier wafer; 20, substrate; 21, first sacrificial layer; 22, bottom stack layer; 23, second sacrificial layer; 24, top stack layer; 251, first semiconductor structure; 252, second semiconductor structure; 253, second intermediate sacrificial layer; 254, first intermediate sacrificial layer; 26, isolation structure; 27, pseudo-gate structure; 28, side wall; 29, MDI layer; 30, first inner side wall; 31, filling structure; 32, source-drain isolation structure; 34, second inner side wall; 35, second isolation layer; 36, first isolation layer; 37, oxide layer; 38, first pseudo-gate structure; 39, gate isolation structure; 40, second pseudo-gate structure; 41, second gate cut-off structure; 42, first gate cut-off structure. DETAILED DESCRIPTION

[0031] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0032] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot topic in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0033] In one embodiment, there are two schemes for the manufacturing process of stacked transistors, the first is a monolithic scheme, and the second is a sequential scheme.

[0034] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using substrate bonding technology. This determines that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied on to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

[0035] The second solution is based on substrate bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding the substrate on top of the already fabricated lower transistor, and the two transistors are stacked vertically. However, this solution requires strict temperature control during the thermal process of processing the upper transistor to avoid affecting the lower transistor and interconnects. The advantage of this solution is that thanks to substrate bonding, the device structure, channel crystal orientation and even channel material used by the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. This solution currently has the following technical challenges: (1) Preparation of high-quality upper transistor active layer; (2) Thinning and defect control of the upper bonding substrate; (3) There is an alignment error between the upper and lower transistors, which requires extremely high lithography accuracy.

[0036] From a common perspective, the technical difficulties of the above two solutions are: (1) the thermal stability of the bottom transistor when preparing the top transistor; (2) the performance of the top transistor under a low thermal budget; (3) the metal interconnection between transistors in the layers.

[0037] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a flip-chip stacked transistor, which can improve the thermal budget in the overall device preparation process.

[0038] In the embodiments of the present application, the flip-chip stacked transistor can be applied to semiconductor devices such as memory and processor.

[0039] In one embodiment, the flip-chip stacked transistor may include at least two transistors. Taking the first transistor and the second transistor as an example, the first transistor and the second transistor are stacked, the second semiconductor structure of the first transistor is self-aligned with the first semiconductor structure of the second transistor, and the first source-drain structure of the first transistor is self-aligned with the second source-drain structure of the second transistor in the vertical direction, so the first transistor and the second transistor are completely self-aligned.

[0040] In an embodiment of the present application, the first transistor and the second transistor in the flip-chip stacked transistor are transistors of the same type, such as any one of the following: a fin field effect transistor (FinFET), a gate-all-around field effect transistor (GAAFET) and a planar transistor.

[0041] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a flip-chip stacked transistor in an embodiment of the present application, such as Figure 1 As shown, the method for preparing the flip-chip stacked transistor includes the following steps.

[0042] Step S110: forming a first semiconductor structure and a second semiconductor structure stacked in sequence on a substrate structure.

[0043] In some embodiments, the implementation process of step S110 can be divided into the following three steps: providing a substrate; sequentially forming a sacrificial layer and a first material layer on the substrate; etching the sacrificial layer and the first material layer to form a first semiconductor structure and a second semiconductor structure, wherein the first material layer close to the substrate after etching serves as the first semiconductor structure, and the first material layer far from the substrate after etching serves as the second semiconductor structure.

[0044] By way of example, the substrate may be any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate.

[0045] After providing the substrate, semiconductor materials can be stacked on the substrate in sequence to form a sacrificial layer and a first material layer, and certain areas of the sacrificial layer and the first material layer can be etched to form a number of semiconductor structures standing on the substrate, and the semiconductor structure is the first material layer after etching. Among them, the material forming the sacrificial layer is different from the material forming the first material layer, so that the sacrificial layer can be removed later by material selectivity, and the role of the sacrificial layer will be described later. The etching process can be exemplified by at least one of dry etching, wet etching, reactive ion etching, etc.

[0046] Here, each semiconductor structure includes a first part (first semiconductor structure) and a second part (second semiconductor structure), and the first part is closer to the substrate than the second part, that is, the first material layer after etching is divided into two parts, the lower half close to the substrate is used as the first semiconductor structure, and the upper half away from the substrate is used as the second semiconductor structure.

[0047] In some embodiments, the first material layer may include a first semiconductor material, or the first material layer may include at least a first semiconductor material and a second semiconductor material alternately stacked in sequence along an arrangement direction of the semiconductor structure. For example, the first semiconductor material may be silicon, and the second semiconductor material may be silicon germanium.

[0048] It can be understood that the first material layer can be a single layer formed by depositing one material, or can be a stacked layer formed by alternately depositing two different materials.

[0049] In one example, when the flip-chip stacked transistor is a FinFET, the material forming the substrate may be silicon, the material forming the sacrificial layer may be silicon germanium, and the material forming the first material layer of the semiconductor structure may be silicon. The semiconductor structure here may also be referred to as an active structure. When the flip-chip stacked transistor is a GAAFET, the material forming the substrate may be silicon, the material forming the sacrificial layer may be silicon germanium, and the material forming the first material layer of the semiconductor structure may be silicon germanium and silicon deposited alternately. The silicon germanium material in the semiconductor structure may be removed subsequently to form an active structure. Among them, the germanium content in the silicon germanium material forming the sacrificial layer is different from the germanium content in the silicon germanium material forming the semiconductor structure (i.e., SiGe 1 is used to prepare the sacrificial layer, and SiGe 2 is used to prepare the semiconductor structure).

[0050] In some other embodiments, the present application can also prepare an isolation structure between a front transistor and a back transistor in a flip-chip stacked transistor. In this case, the aforementioned sacrificial layer can be referred to as a first sacrificial layer.

[0051] Based on this, in the case where the first material layer includes the first semiconductor material, the first semiconductor material can be deposited on the first sacrificial layer to form a bottom layer, an isolation material can be deposited on the bottom layer to form a second sacrificial layer, and the first semiconductor material can be deposited again on the second sacrificial layer to form a top layer. In the case where the first material layer includes the first semiconductor material and the second semiconductor material alternately stacked in sequence, the first semiconductor and the second semiconductor can be alternately deposited on the first sacrificial layer to form a bottom stacking layer, an isolation material can be deposited on the bottom stacking layer to form a second sacrificial layer, and the first semiconductor material and the second semiconductor material can be alternately deposited again on the second sacrificial layer to form a top stacking layer. After etching to form the semiconductor structure, the etched second sacrificial layer (second intermediate sacrificial layer) is located between the first semiconductor structure and the first semiconductor structure. By way of example, the isolation material forming the second sacrificial layer can be the same as the material forming the first sacrificial layer.

[0052] In some embodiments, after forming the semiconductor structure, an isolation structure may be formed on the substrate to expose the first semiconductor structure and the second semiconductor structure; and a semiconductor material may be deposited on the isolation structure to form a dummy gate structure surrounding the first semiconductor structure and the second semiconductor structure.

[0053] It is understandable that after forming the semiconductor structure, an insulating material may be deposited on the substrate and thinned so that the upper surface of the formed isolation structure is flush with the upper surface of the sacrificial layer to expose the semiconductor structure.

[0054] In one example, the isolation structure may be formed by shallow trench isolation (STI). For example, the insulating material forming the isolation structure may be any of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2) or silicon oxycarbide (SiCO). The thinning process may be a process such as chemical-mechanical planarization (CMP).

[0055] After the semiconductor structure is formed, a semiconductor material may be deposited on the semiconductor structure to form a dummy gate structure.

[0056] To distinguish the semiconductor material from the first semiconductor material and the second semiconductor material, the semiconductor material here is referred to as a third semiconductor material, where the third semiconductor material may be, for example, polysilicon (poly Si), amorphous silicon, or the like.

[0057] It is understandable that after forming the semiconductor structure and the isolation structure, the gate region can be opened by photolithography, and a third semiconductor material such as polysilicon can be deposited in the gate region as a pseudo-gate structure shared by the front transistor and the back transistor. That is, the present application defines the gate region of the front transistor and the back transistor in the flip-chip stacked transistor by the pseudo-gate structure, so that the self-alignment of the upper and lower transistors in the flip-chip stacked transistor can be achieved in the gate region. Among them, the height of the pseudo-gate structure is greater than the height of the semiconductor structure.

[0058] The above is to form a dummy gate structure shared by the front transistor and the back transistor. The present application can also form a dummy gate structure of the front transistor and a dummy gate structure of the back transistor separately.

[0059] In some embodiments, when forming a semiconductor structure, an isolation structure can be formed on the isolation structure to expose the first semiconductor structure and the second semiconductor structure; a semiconductor material can be deposited on the isolation structure to form a first dummy gate structure surrounding the first semiconductor structure; a gate isolation structure can be formed on the first dummy gate structure; and a semiconductor material can be deposited on the gate isolation structure to form a second dummy gate structure surrounding the second semiconductor structure.

[0060] That is, in the embodiment of the present application, after forming the isolation structure, a third semiconductor material such as polysilicon may be first deposited as a pseudo gate structure of the back transistor, and then an insulating material may be deposited on the pseudo gate structure of the back transistor to form a gate isolation structure, and then a third semiconductor material such as polysilicon may be deposited on the gate isolation structure as a pseudo gate structure of the front transistor. The gate isolation structure serves as isolation between the gate structure of the front transistor and the gate structure of the back transistor.

[0061] In some embodiments, before separately forming the pseudo gate structures of the front and back transistors, an oxide material may be deposited on the substrate to form an oxide layer, and the oxide layer covers the semiconductor structure. When depositing the oxide to form the oxide layer, a very thin film may be deposited on the surface of the substrate by atomic layer deposition (ALD).

[0062] After the oxide layer is formed, a first dummy gate structure, a gate isolation structure and a second dummy gate structure may be sequentially formed on the oxide layer.

[0063] In some embodiments, after forming the dummy gate structure, a spacer may be formed on both sides of the dummy gate structure. Accordingly, the spacer also includes a first spacer located on both sides of the first dummy gate structure and a second spacer located on both sides of the second dummy gate structure. For example, the spacer may have a single-layer structure, and the entire structure may be made of the same material, such as porous carbon silicon oxyhydride (SICOH).

[0064] Step S120: etching the first semiconductor structure and the second semiconductor structure in the source-drain region, and filling the first source-drain region corresponding to the first semiconductor structure with an insulating material to form a filling structure.

[0065] It can be understood that the semiconductor structure in the source and drain region can be etched, and the first semiconductor structure and the second semiconductor structure in the source and drain region can be removed. Since there is also an etched first sacrificial layer and an isolation structure located on both sides of the first sacrificial layer below the semiconductor structure and above the substrate, the etched first sacrificial layer and the isolation structure located in the source and drain region can also be removed here to completely expose the entire source and drain region. The source and drain region may include a first source and drain region corresponding to the first semiconductor and a second source and drain region corresponding to the second semiconductor. After the source and drain region is exposed, an insulating material may be filled in the first source and drain region corresponding to the first semiconductor to form a filling structure, so that the source and drain region of the back transistor can be defined by the filling structure to achieve self-alignment of the upper and lower transistors in the flip-chip stacked transistor in the source and drain region.

[0066] By way of example, the insulating material may be silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), or the like.

[0067] In addition, in some embodiments, before etching the semiconductor structure in the source and drain regions, the second intermediate sacrificial layer between the first semiconductor structure and the second semiconductor structure can be selectively removed to form a groove, and an insulating material is filled in the groove to form a middle dielectric isolation (MDI) layer. The MDI layer can serve as isolation between the front transistor and the back transistor.

[0068] In some embodiments, when the MDI layer is present, the filling structure may cover a portion of the MDI layer when the filling structure is formed.

[0069] In some embodiments, after forming the filling structure, a source-drain isolation structure may be further formed on the filling structure, where the source-drain isolation structure is used to isolate a first source-drain structure of the first transistor from a second source-drain structure of the second transistor.

[0070] It can be understood that after forming the filling structure, an insulating material may be deposited on the filling structure and thinned so that the upper surface of the formed source-drain isolation structure is flush with the upper surface of the MDI layer.

[0071] Step S130: forming a third semiconductor structure based on the second semiconductor structure through a front-end process.

[0072] In some embodiments, the third semiconductor structure includes a first source-drain structure formed in the second source-drain region.

[0073] It can be understood that after etching the semiconductor structure in the source-drain region, a source-drain groove will be formed, so source-drain epitaxial growth can be performed in the source-drain groove to form a first source-drain structure.

[0074] Exemplarily, strained materials such as silicon germanium or silicon carbide can be formed in the source and drain grooves by selective epitaxial growth to fill the source and drain grooves of the front transistor (first transistor), and then a first source and drain structure is formed on the strained material by a heavy doping process.

[0075] In some embodiments, after forming the first source-drain structure, an interlayer dielectric may be deposited on the first source-drain structure, and the interlayer dielectric may be thinned to the upper surface of the first source-drain structure to form a first interlayer dielectric layer. The interlayer dielectric may be SiO2, for example. Thus, the third semiconductor structure includes the first source-drain structure and the first interlayer dielectric layer.

[0076] For ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source electrode structure and / or the first drain electrode structure. In addition, the first source-drain metal, the second source-drain structure, the second source-drain metal, etc. mentioned later are similar to the first source-drain structure, where "source-drain" is an abbreviation for "source and / or drain".

[0077] Step S140: flipping the third semiconductor structure and removing the substrate and the filling structure to expose the first semiconductor structure.

[0078] That is, after a portion of the front transistor (the third semiconductor structure) is prepared in the embodiment of the present application, the wafer is flipped to prepare the back transistor.

[0079] In some embodiments, an insulating material (such as silicon oxide) can be deposited on the first interlayer dielectric layer to form a first insulating layer, and the first insulating layer can be bonded to the first carrier wafer, which is then flipped to place a substrate on top and removed.

[0080] After removing the substrate, the structure may be filled by selective etching of the material to expose the first source and drain region of the back side transistor.

[0081] It can be understood that since the filling structure covers the first source and drain region of the back transistor, when preparing the back transistor, the filling structure can be etched through the selectivity of the material to expose the first source and drain region. Since the filling structure is used to locate the source and drain region where the back transistor is located, when preparing the back transistor later, there is no need to select the region through photolithography, and the source and drain region can be directly opened through the selectivity of the material to prepare a back transistor that is completely self-aligned with the front transistor.

[0082] In some embodiments, after removing the substrate and before etching the filling structure, a semiconductor material may be filled in the gate region so that the upper surface of the formed dummy gate structure is flush with the upper surface of the sacrificial layer (first sacrificial layer).

[0083] It is understandable that, since the first sacrificial layer and the isolation structures on both sides of the first sacrificial layer still exist in the gate region of the back transistor, the isolation structure in the gate region can be removed after removing the substrate to expose the first sacrificial layer. Then, the etched gate region can be filled with materials such as polysilicon so that the formed dummy gate structure can completely define the gate region of the back transistor.

[0084] Step S150: forming a fourth semiconductor structure based on the first semiconductor structure.

[0085] In some embodiments, the third semiconductor structure may be a complete back side transistor (second transistor) or a part of the back side transistor. The following first introduces a scheme for forming the back side transistor.

[0086] In some embodiments, the implementation process of step S150 may be: epitaxially growing a second source-drain structure on the first source-drain region; forming a gate structure of a fourth semiconductor structure based on the first semiconductor structure; depositing metal material on the second source-drain structure to form a second source-drain metal; and performing back-end interconnection on the second source-drain metal through a back-end process to form a second metal interconnection layer.

[0087] It can be understood that after etching the filling structure in the first source-drain region, a source-drain groove will be formed, and thus source-drain epitaxial growth can be performed in the source-drain groove to form a second source-drain structure.

[0088] In some embodiments, after the second source-drain structure is formed, an interlayer dielectric may be deposited on the second source-drain structure, and the interlayer dielectric may be thinned to an upper surface of the second source-drain structure to form a second interlayer dielectric layer.

[0089] When forming the second interlayer dielectric layer, a portion of the second interlayer dielectric layer may be etched to expose the second source-drain structure, and then a metal material is deposited on the second source-drain structure to form a second source-drain metal.

[0090] In some embodiments, after forming the second source and drain metal, a back-end process may be performed to form a second metal interconnection layer.

[0091] It is understandable that the back-end process may be, for example, dielectric deposition between interconnects, metal line formation, lead pad formation, etc. Here, the interconnects and corresponding insulating dielectrics of the back-side transistors are made of high temperature resistant materials, such as metal tungsten (W), oxides, etc.

[0092] In the embodiment of the present application, the gate structure of the first transistor and the gate structure of the second transistor can be formed at the same time on the back side, and this solution is introduced below.

[0093] In the case of forming the dummy gate structure shared by the front transistor and the back transistor, the dummy gate structure can be removed to form a first gate structure of the first transistor and a second gate structure of the second transistor respectively.

[0094] It is understandable that after forming the second interlayer dielectric layer and before forming the second source and drain metal, the pseudo gate structure formed above can be removed by an etching process to obtain a gate groove, and a gate structure shared by the front and back sides can be formed at the gate groove. The gate structure can include a gate dielectric layer formed by depositing an insulating material at the gate groove, and a gate electrode layer formed by depositing a metal material on the gate dielectric layer. Then the gate structure can be etched back to the bottom of the back transistor, and the retained gate structure can be used as the first gate structure of the front transistor, and the second gate structure of the back transistor can be formed in the gate region of the exposed back transistor. Among them, the first gate structure includes a first gate dielectric layer and a first gate electrode layer, and the second gate structure includes a second gate dielectric layer and a second gate electrode layer.

[0095] For example, the gate dielectric layer may be composed of a silicon oxide layer and a hafnium oxide layer with a high K value, and the thicknesses of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor.

[0096] By way of example, the gate electrode layer may be composed of multiple layers of electrode materials, each layer of which includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0097] In the case where the flip-chip stacked transistor is a GAAFET, the first material layer of the formed semiconductor structure is alternately deposited silicon germanium and silicon, so when removing the pseudo-gate structure, the silicon germanium material in the semiconductor structure can be removed to form a nanosheet structure. The nanosheet structure includes a first nanosheet structure of the front transistor and a second nanosheet structure of the back transistor.

[0098] The embodiment of the present application can also form a second gate structure separately on the back side. When the first dummy gate structure, the gate isolation structure and the second dummy gate structure are formed as described above, the first dummy gate structure can be removed to form the second gate structure.

[0099] Furthermore, in some embodiments, before forming the second source-drain metal, a second isolation layer may be formed on the second gate structure and the second interlayer dielectric layer, and the second isolation layer is used to isolate the second transistor from the second metal interconnection layer.

[0100] It is understandable that an insulating material can be deposited on the second gate structure and the second interlayer dielectric layer to form a second isolation layer, which can also be called a pre-metal dielectric (PMD) layer. The PMD layer has the following two functions: (1) electrical isolation. The PMD layer electrically isolates the transistor device and the metal interconnect layer to prevent current from flowing in unnecessary paths and ensure the normal operation of the circuit; (2) physical protection. The PMD layer can block impurity sources such as movable particles (such as sodium ions) to prevent impurity sources from affecting the performance of transistor devices and protect the devices from the influence of the external environment. Among them, the insulating material forming the PMD layer can be SiO2, SiN and other materials.

[0101] The above is a solution for preparing the back side transistor at one time on the back side, so that the other part of the front side transistor can be prepared by flipping the wafer once later, that is, the embodiment of the present application can form a flip-chip stacked transistor by flipping the wafer twice. In this case, the fourth semiconductor structure includes a second source-drain structure, a second interlayer dielectric layer, a second gate structure, a second source-drain metal, and a second metal interconnect layer.

[0102] In some embodiments, the implementation process of step S150 may be: epitaxially growing a second source-drain structure in the first source-drain region; and forming a second gate structure of a fourth semiconductor structure based on the first semiconductor structure.

[0103] In some embodiments, based on the first semiconductor structure, the implementation process of forming the second gate structure may be: removing the first dummy gate structure to form the second gate structure.

[0104] When the flip-chip stacked transistor is a GAAFET, the first material layer of the formed semiconductor structure is alternately deposited silicon germanium and silicon. Therefore, when removing the first dummy gate structure, the silicon germanium material in the first semiconductor structure can be removed to form a second nanosheet structure.

[0105] In some embodiments, after forming the second source-drain structure and after forming the second gate structure, an interlayer dielectric may be deposited on the second source-drain structure to form a second interlayer dielectric layer.

[0106] After forming the second gate structure, an insulating material may be deposited on the second gate structure and the second interlayer dielectric layer to form a second isolation layer.

[0107] Therefore, the embodiment of the present application can also prepare a part of the back side transistor on the back side, and then flip the chip to prepare another part of the front side transistor, and then flip the chip again to prepare another part of the back side transistor, that is, the embodiment of the present application can also complete the flip stack transistor by flipping the chip three times. In this case, the fourth semiconductor structure includes a second source-drain structure, a second interlayer dielectric layer, and a second gate structure.

[0108] Step S160: Based on the third semiconductor structure and the fourth semiconductor structure, a first transistor and a second transistor are formed respectively.

[0109] In the embodiment of the present application, after the back side transistor or a part of the back side transistor is prepared, flipping is performed to prepare another part of the front side transistor.

[0110] In some embodiments, in the case of preparing a complete back-side transistor in the above step S150, the implementation process of forming the first transistor based on the third semiconductor structure can be: after forming the fourth semiconductor structure, the fourth semiconductor structure is flipped over and the third semiconductor structure is exposed; metal material is deposited on the first source and drain structure in the third semiconductor structure to form a first source and drain metal; and through a back-end process, back-end interconnection is performed on the first source and drain metal to form a first metal interconnection layer.

[0111] Therefore, the present application embodiment can decompose the preparation process of the flip-chip stacked transistor into multiple stages by flipping the chip twice, and only perform partial heat treatment in each stage. In this way, the impact of a single heat treatment on the device will be reduced, thereby improving the overall thermal budget. The two flip-chip preparations can also change the preparation order of the flip-chip stacked transistor device and the back-end interconnects, which can further reduce the impact of the heat treatment on the device performance, thereby improving the thermal budget.

[0112] In some embodiments, after forming the fourth semiconductor structure, an insulating material may be deposited on the fourth semiconductor structure to form a second insulating layer, and the second insulating layer may be bonded to the second carrier wafer and then flipped.

[0113] In some embodiments, after flipping the wafer, the first insulating layer and the first carrier layer may be removed to expose a portion of the fabricated front transistor (the third semiconductor structure).

[0114] It can be understood that after exposing the third semiconductor structure, metal material can be deposited on the first source and drain structure to form a first source and drain metal; and through a back-end process, back-end interconnection can be performed on the first source and drain metal to form a first metal interconnection layer of the first transistor.

[0115] In some embodiments, when there is a first interlayer dielectric layer, a portion of the first interlayer dielectric layer may be etched to expose the first source-drain structure, and then a metal material is deposited on the first source-drain structure to form a first source-drain metal.

[0116] In addition, in the case where only the second gate structure is formed on the back side, the second dummy gate structure formed above can also be removed to form the first gate structure.

[0117] When the flip-chip stacked transistor is a GAAFET, the first material layer of the formed semiconductor structure is alternately deposited silicon germanium and silicon. Therefore, when removing the second dummy gate structure, the silicon germanium material in the second semiconductor structure can be removed at the same time to form a first nanosheet structure.

[0118] Furthermore, in some embodiments, before forming the first source-drain metal, a first isolation layer may be formed on the first gate structure and the first interlayer dielectric layer, and the first isolation layer is used to isolate the first transistor from the first metal interconnection layer.

[0119] It can be understood that an insulating material may be deposited on the first gate structure and the first interlayer dielectric layer to form a first isolation layer, and the first isolation layer may also be referred to as a PMD layer.

[0120] In addition, in the case where only a portion of the back-side transistor is prepared in the above step S150, the implementation process of forming the first transistor based on the third semiconductor structure can be: after forming the fourth semiconductor structure, the fourth semiconductor structure is flipped over and the third semiconductor structure is exposed; metal material is deposited on the first source and drain structure in the third semiconductor structure to form a first source and drain metal; and back-end interconnection is performed on the first source and drain metal to form a first metal interconnection layer.

[0121] In some embodiments, based on the fourth semiconductor structure, the implementation process of forming the second transistor may be: after forming the first transistor, flipping the first transistor and exposing the fourth semiconductor structure; depositing metal material on the second source and drain structure in the fourth semiconductor structure to form a second source and drain metal; and performing back-end interconnection on the second source and drain metal through a back-end process to form a second metal interconnection layer.

[0122] It can be understood that after forming the first metal interconnection layer, a third insulating layer can be formed on the first metal interconnection layer and bonded to a third carrier wafer, and then flipped over and the second insulating layer and the second carrier wafer are removed to prepare another part of the back transistor.

[0123] The embodiment of the present application controls the thermal budget by flipping the wafer three times, which can achieve better thermal control than flipping the wafer twice.

[0124] In addition, in the embodiment of the present application, after forming the gate structure, a gate cut-off structure can be formed on both sides of the gate structure, and the gate cut-off structure is used to isolate the gate structure of the flip-chip stacked transistor from the gate structure of the adjacent flip-chip stacked transistor. Accordingly, the gate cut-off structure includes a first gate cut-off structure corresponding to the first gate structure and a second gate cut-off structure corresponding to the second gate structure.

[0125] In the embodiment of the present application, a first semiconductor structure and a second semiconductor structure are formed on a substrate, and based on the second semiconductor structure, a portion of the first transistor is first formed, and then the chip is flipped, and based on the first semiconductor structure, a second transistor is formed, and then the chip is flipped again to form another portion of the first transistor. Therefore, the embodiment of the present application can decompose the preparation process of the flip-chip stacked transistor into multiple stages by flipping the chip multiple times, and only part of the heat treatment is performed in each stage. In this way, the impact of a single heat treatment on the device will be reduced, thereby improving the overall thermal budget; and multiple flipping preparations can also change the preparation order of the flip-chip stacked transistor device. By optimizing the preparation order, the impact of the heat treatment on the device performance can be further reduced, thereby improving the thermal budget.

[0126] Furthermore, the solution of the embodiment of the present application can not only greatly improve the transistor inheritance density, but also take into account the consistency, defect density and alignment of the active areas of the front and back transistors; it uses fewer high aspect ratio processes and more compatible to achieve fully self-aligned flip-chip stacking of various forms of transistors; the flip-chip stacking transistor solution in the embodiment of the present application is compatible with the existing mainstream device architecture, and can achieve front and back stacking of planar transistors, FinFETs, GAA Nanosheets and even vertical transistors without the need for special process development for specific device architectures. It is highly flexible and has strong extensibility from the perspective of semiconductor process node iteration. The flip-chip transistor is very advanced in concept, has important industrial value, is highly practical, and has broad prospects for development.

[0127] The following describes the method for preparing the flip-chip stacked transistor provided in the embodiment of the present application by taking the active structure in the flip-chip stacked transistor as a nanosheet structure as an example. Figure 2 This is a top view schematic diagram of the flip-chip stacked transistor in the embodiment of the present application. It should be noted that, for ease of understanding, only the nanosheet structure, gate structure, and source-drain structure are shown in the top view. The AA' direction is the cross-sectional direction of the flip-chip stacked transistor along the gate structure; the BB' direction is the cross-sectional direction of the flip-chip stacked transistor along the source-drain structure; and the CC' direction is the cross-sectional direction of the flip-chip stacked transistor along the nanosheet structure.

[0128] The first preparation process is first introduced below, that is, the gate structure of the front transistor and the gate structure of the back transistor are formed at one time on a single side, and the flip-chip stacked transistor is formed by flipping twice. FIG. 3A to FIG. 3J This is a schematic diagram of the structure of the flip-chip stack transistor in the first preparation process according to an embodiment of the present application. Figure 3K This is a schematic diagram of a first structure of a flip-chip stacked transistor according to an embodiment of the present application.

[0129] Step 1: forming a first sacrificial layer 21 on the original substrate 20, forming a bottom stacking layer 22 on the first sacrificial layer 21, forming a second sacrificial layer 23 on the bottom stacking layer 22, and forming a top stacking layer 24 on the second sacrificial layer 23 (see Figure 3A (a) in the figure.

[0130] For example, a Si layer 20 may be provided, and SiGe 1 material may be deposited on the Si layer 20 to form a first sacrificial layer 21; then SiGe 2 material and Si material may be alternately deposited on the first sacrificial layer 21 to form a stacked layer of a preset thickness, which is a bottom stacked layer 22; then SiGe 1 material may be deposited on the bottom stacked layer 22 to form a second sacrificial layer 23; finally, SiGe 2 material and Si material may be alternately deposited on the second sacrificial layer 23 to form a stacked layer of a preset thickness, which is a top stacked layer 24. It should be noted that the SiGe 1 material and SiGe 2 material here are only exemplary descriptions, and other materials may actually be used.

[0131] Step 2: sequentially etch the top stack layer 24, the second sacrificial layer 23, the bottom stack layer 22, and the first sacrificial layer 21 until the substrate 20 to form a semiconductor structure (see Figure 3A (b) in the figure.

[0132] It can be understood that the first semiconductor structure 251 close to the substrate, the second semiconductor structure 252 far from the substrate, the second middle sacrificial layer 253 and the first middle sacrificial layer 254 can be formed by etching.

[0133] Step 3: Deposit an oxide material on the substrate 20 to form an isolation structure 26, and perform etching and CMP to the upper surface of the first intermediate sacrificial layer 254 (see Figure 3A (c) in the figure.

[0134] Step 4: The gate region is opened by photolithography, and polysilicon and other materials are deposited in the gate region to form a pseudo gate structure 27 shared by the front and back sides, and a sidewall (spacer) 28 is formed on both sides of the pseudo gate structure and the first semiconductor structure 251, the second semiconductor structure 252 and the second intermediate sacrificial layer 253 (see Figure 3B (a) in the figure.

[0135] By defining the gate regions of the front transistor and the back transistor in the flip-stack transistor through the pseudo-gate structure, self-alignment of the upper and lower transistors in the flip-stack transistor at the gate region can be achieved.

[0136] Step 5: Etch the sidewall 28 until the second intermediate sacrificial layer 253 to expose the second semiconductor structure 252 of the front transistor (see Figure 3B (b) in the figure.

[0137] Step 6: Etch the second semiconductor structure in the source and drain region of the front transistor (see Figure 3B (c) in the figure.

[0138] Step 7: Selectively etch the second intermediate sacrificial layer 253 between the semiconductor structures of the front and back transistors, and fill the etched grooves with insulating material to form an MDI layer 29 (see Figure 3C (a) in the figure.

[0139] Step 8: Laterally etch a portion of the SiGe2 material of the front transistor, fill with insulating material and etch again to form a first inner spacer 30 located on both sides of the SiGe2 of the front transistor (see Figure 3C (b) in the figure.

[0140] In some embodiments, the eighth step of forming the first inner sidewall may be performed simultaneously with the seventh step of forming the MDI layer.

[0141] Step 9: Anisotropic etching removes the spacer and the first semiconductor structure of the back transistor in the source and drain region (see Figure 3C (c) in the figure.

[0142] Step 10: Anisotropically etch the first intermediate sacrificial layer 254 and the isolation structure 26 in the source and drain regions (see Figure 3D (a) in the figure.

[0143] Step 11: Fill the source and drain regions with insulating material to form a filling structure 31 covering the source and drain regions of the back transistor (see Figure 3D (b) in the figure.

[0144] Step 12: Form a source-drain isolation structure 32 on the filling structure 31 (see Figure 3D (c) in the figure.

[0145] It should be noted that the source-drain isolation structure is formed on the filling structure here, and the embodiment of the present application can also etch the filling structure after the first flipping, and then form the source-drain isolation structure. Or after the first flipping, part of the filling structure is etched, and the remaining filling structure is used as the source-drain isolation structure.

[0146] Step 13: Form the first source-drain structure 112 of the front transistor (see Figure 3E (a) in the figure.

[0147] Step 14: Deposit an interlayer dielectric in the source and drain regions to form a first interlayer dielectric layer 113 (see Figure 3E (b) in the figure.

[0148] Step 15: Deposit insulating material on the first interlayer dielectric layer 113 to form a first insulating layer 13, and bond the first carrier wafer 14 to the first insulating layer 13 (see Figure 3E (c) in the figure.

[0149] Step 16: First flip, thinning and CMP removal of substrate 20 (see Figure 3F (a) in the figure.

[0150] Step 17: Selectively etch the isolation structure 26 in the gate region (see Figure 3F (b) in the figure.

[0151] Step 18: Fill the etched area with polysilicon or other materials to supplement the pseudo gate structure formed above (see Figure 3F (c) in the figure.

[0152] Step 19: Remove the filling structure 31 (see Figure 3G (a) in the figure.

[0153] Step 20: Laterally etch a portion of the SiGe2 material of the back transistor, fill it with insulating material and etch it to form a second inner sidewall 34 located on both sides of the SiGe2 of the back transistor (see Figure 3G (b) in the figure.

[0154] Step 21: Forming a second source-drain structure 122 and a second interlayer dielectric layer 123 of the back transistor (see Figure 3G (c) in the figure.

[0155] Step 22: Remove the dummy gate structure 27 (see Figure 3H (a) in the figure.

[0156] Step 23: Remove the SiGe2 material and the first intermediate sacrificial layer in the first semiconductor structure and the second semiconductor structure to form a first nanosheet structure 111 and a second nanosheet structure 121, and form a first gate structure 114 based on the first nanosheet structure 111 and a second gate structure 124 based on the second nanosheet structure 121 (see Figure 3H (b) in the figure.

[0157] It can be understood that an insulating material can be deposited on the surface of the first nanosheet structure 111 to form a first gate dielectric layer 1141, and a metal material can be deposited on the first gate dielectric layer 1141 in the gate region to form a first gate electrode layer 1142. The first gate dielectric layer 1141 and the first gate electrode layer 1142 constitute a first gate structure 114. An insulating material is deposited on the surface of the second nanosheet structure 121 to form a second gate dielectric layer 1241, and a metal material is deposited on the second gate dielectric layer 1241 in the gate region to form a second gate electrode layer 1242. The second gate dielectric layer 1241 and the second gate electrode layer 1242 constitute a second gate structure 124. Therefore, the gate structure of the front transistor and the gate structure of the back transistor in the embodiment of the present application are formed at the back at one time.

[0158] Step 24: Form a second isolation layer 35 on the second gate structure 124 and the second interlayer dielectric layer 123, and form a second source-drain metal 125 on the second source-drain structure 122 (see Figure 3H (c) in the figure.

[0159] Step 25: Perform back-end interconnection to form a second metal interconnection layer 126 (see Fig. 3I (a) in the figure.

[0160] Here, the back-end interconnection lines and corresponding insulating media of the back-side transistors are made of high-temperature resistant materials, such as W, oxide, etc.

[0161] Step 26: Deposit insulating material on the second metal interconnect layer 126 to form a second insulating layer 15, bond the second carrier wafer 16 to the second insulating layer 15, and perform a second flip (see Fig. 3I (b) in the figure.

[0162] Step 27: Thinning and CMP removal of the first insulating layer 13 and the first carrier wafer 14 (see Figure 3J (a) in the figure.

[0163] Step 28: Form a first isolation layer 36 on the first gate structure 114 and the first interlayer dielectric layer 113, and form a first source-drain metal 115 on the first source-drain structure 112 (see Figure 3J (b) in the figure.

[0164] Step 29: Perform back-end interconnection to form a first metal interconnection layer 116 (see Figure 3K ).

[0165] It should be noted that the embodiment of the present application may not form an MDI layer. In the case where the MDI layer is not formed, the second intermediate sacrificial layer 253 may be made of Si material. Moreover, the fifth step may etch the sidewall 28 to a position above the second intermediate sacrificial layer 253 and around the bottom of the second semiconductor structure 252. At this time, the sidewall 28 may play a role in limiting the growth of the source-drain structure of the first transistor.

[0166] The second preparation process is introduced below, that is, the gate structure of the front transistor and the gate structure of the back transistor are formed on both sides, and a flip-chip stacked transistor is formed by flipping the wafer twice. FIG. 4A to FIG. 4G This is a schematic diagram of the structure of the flip-chip stack transistor in the second preparation process according to an embodiment of the present application. Figure 4H This is a schematic diagram of a second structure of a flip-chip stack transistor according to an embodiment of the present application.

[0167] Step 1: forming a first sacrificial layer 21 on the original substrate 20, forming a bottom stacking layer 22 on the first sacrificial layer 21, forming a second sacrificial layer 23 on the bottom stacking layer 22, and forming a top stacking layer 24 on the second sacrificial layer 23 (see Figure 4A (a) in the figure.

[0168] For example, a Si layer 20 may be provided, and SiGe1 material may be deposited on the Si layer 20 to form a first sacrificial layer 21; then SiGe2 material and Si material may be alternately deposited on the first sacrificial layer 21 to form a stacked layer of a preset thickness, which is a bottom stacked layer 22; then SiGe1 material may be deposited on the bottom stacked layer 22 to form a second sacrificial layer 23; finally, SiGe2 material and Si material may be alternately deposited on the second sacrificial layer 23 to form a stacked layer of a preset thickness, which is a top stacked layer 24. It should be noted that the SiGe1 material here is only an exemplary description, and other materials may actually be used.

[0169] Step 2: sequentially etch the top stack layer 24, the second sacrificial layer 23, the bottom stack layer 22, and the first sacrificial layer 21 until the substrate 20 to form a semiconductor structure (see Figure 4A (b) in the figure.

[0170] It can be understood that the first semiconductor structure 251 close to the substrate, the second semiconductor structure 252 far from the substrate, the second middle sacrificial layer 253 and the first middle sacrificial layer 254 can be formed by etching.

[0171] Step 3: Deposit an oxide material on the substrate 20 to form an isolation structure 26, and perform etching and CMP to the upper surface of the first intermediate sacrificial layer 254 (see Figure 4A (c) in the figure.

[0172] Step 4: Form an oxide layer 37 on the substrate (see Figure 4B (a) in the figure.

[0173] It can be understood that the oxide layer 37 is a thin film deposited on the surfaces of the first semiconductor structure 251 , the second semiconductor structure 252 , and the second intermediate sacrificial layer 253 .

[0174] Step 5: depositing polysilicon or other materials on the oxide layer 37, and etching back to the top of the first semiconductor structure 251 to form a first dummy gate structure 38 surrounding the first semiconductor structure 251 (see Figure 4B (b) in the figure.

[0175] Step 6: Deposit an insulating material on the first dummy gate structure 38 and etch back to the bottom of the second semiconductor structure to form a gate isolation structure 39 (see Figure 4B (c) in the figure.

[0176] Step 7: Form a second dummy gate structure 40 surrounding the second semiconductor structure 252 on the gate isolation structure 39 (see Figure 4C (a) in the figure.

[0177] It can be understood that the height of the second dummy gate structure 40 is higher than the height of the second semiconductor structure 252 .

[0178] Step 8: Photolithography is performed to etch the pseudo gate structure on the front and back sides of the source and drain regions and the gate isolation structure in the middle, and deposition is performed to form the sidewall 28 (see Figure 4C (b) in the figure.

[0179] Step 9: Etch the sidewall 28 until the second intermediate sacrificial layer 253 to expose the second semiconductor structure 252 of the front transistor (see Figure 4C (c) in the figure.

[0180] Step 10: Etch the second semiconductor structure in the source and drain regions of the front transistor (see Figure 4D (a) in the figure.

[0181] Step 11: Selectively etch the second intermediate sacrificial layer 253 between the semiconductor structures of the front and back transistors, and fill the etched grooves with insulating material to form an MDI layer 29 (see Figure 4D (b) in the figure.

[0182] Step 12: Laterally etch a portion of the SiGe2 material of the front transistor, fill it with insulating material and etch it to form a first inner spacer 30 located on both sides of the SiGe2 of the front transistor (see Figure 4D (c) in the figure.

[0183] Step 13: Anisotropic etching removes the spacer and the first semiconductor structure in the source and drain regions of the back transistor (see Figure 4E (a) in the figure.

[0184] Step 14: Anisotropically etch the first intermediate sacrificial layer 254 and the isolation structure 26 in the source and drain regions (see Figure 4E (b) in the figure.

[0185] Step 15: Fill the source and drain regions with insulating material to form a filling structure 31 covering the source and drain regions of the back transistor (see Figure 4E (c) in the figure.

[0186] Step 16: Form a source-drain isolation structure 32 on the filling structure 31 (see Figure 4F (a) in the figure.

[0187] Step 17: Form the first source-drain structure 112 of the front transistor (see Figure 4F (b) in the figure.

[0188] Step 18: Deposit an interlayer dielectric in the source and drain regions to form a first interlayer dielectric layer 113 (see Figure 4F (c) in the figure.

[0189] Step 19: Deposit insulating material on the first interlayer dielectric layer 113 to form a first insulating layer 13, bond the first carrier wafer 14 to the first insulating layer 13, and perform the first flip (see Figure 4G (a) in the figure.

[0190] Step 20: Follow the standard process flow to form the backside transistor and the second metal interconnect layer 126 (see Figure 4G (b) in the figure.

[0191] It can be understood that the substrate 20 can be removed first, the isolation structure 26 of the gate area is selectively etched, and the etched area is filled with materials such as polysilicon to supplement the pseudo-gate structure formed above; the filling structure is removed, a part of the SiGe2 material of the back transistor is laterally etched, and the insulating material is filled and etched to form a second inner sidewall 34 located on both sides of the SiGe2 of the back transistor, forming a second source-drain structure 122 and a second interlayer dielectric layer 123 of the back transistor; then the first pseudo-gate structure 38 is removed, and the SiGe2 material in the first semiconductor structure is removed to form a second nanosheet structure 121, and a second gate structure 124 is formed based on the second nanosheet structure 121, a second isolation layer 35 is formed on the second gate structure 124 and the second interlayer dielectric layer 123, and a second source-drain metal 125 is formed on the second source-drain structure 122; back-end interconnection is performed to form a second metal interconnection layer 126.

[0192] In addition, in the embodiment of the present application, a second gate cutting structure 41 may be formed on both sides of the second gate structure 124 .

[0193] Step 21: Deposit insulating material on the second metal interconnect layer 126 to form a second insulating layer 15, bond the second carrier wafer 16 to the second insulating layer 15, and perform a second flip (see Figure 4G (c) in the figure.

[0194] Step 22: Follow the standard process flow to form the front transistor and the first metal interconnect layer 116 (see Figure 4H ).

[0195] It can be understood that the first insulating layer 13 and the first carrier wafer 14 are first thinned and removed by CMP, and then the second dummy gate structure 40 is removed, and the SiGe2 material in the second semiconductor structure is removed to form a first nanosheet structure 111, and a first gate structure 114 is formed based on the first nanosheet structure 111, a first isolation layer 36 is formed on the first gate structure 114 and the first interlayer dielectric layer 113, and a first source and drain metal 115 is formed on the first source and drain structure 112; and back-end interconnection is performed to form a first metal interconnection layer 116.

[0196] In addition, in the embodiment of the present application, a first gate cutting structure 42 may be formed on both sides of the first gate structure 114 .

[0197] The third preparation process is introduced below, that is, the gate structure of the front transistor and the gate structure of the back transistor are formed at one time on a single side, and a flip-chip stacked transistor is formed by flipping the wafer three times. FIG. 5A to FIG. 5I is a schematic diagram of the structure of the flip-chip stack transistor in the third preparation process according to an embodiment of the present application, Figure 5J This is a third structural schematic diagram of the flip-chip stack transistor according to an embodiment of the present application.

[0198] Step 1: forming a first sacrificial layer 21 on the original substrate 20, forming a bottom stacking layer 22 on the first sacrificial layer 21, forming a second sacrificial layer 23 on the bottom stacking layer 22, and forming a top stacking layer 24 on the second sacrificial layer 23 (see Figure 5A (a) in the figure.

[0199] For example, a Si layer 20 may be provided, and SiGe 1 material may be deposited on the Si layer 20 to form a first sacrificial layer 21; then SiGe 2 material and Si material may be alternately deposited on the first sacrificial layer 21 to form a stacked layer of a preset thickness, which is a bottom stacked layer 22; then SiGe 1 material may be deposited on the bottom stacked layer 22 to form a second sacrificial layer 23; finally, SiGe 2 material and Si material may be alternately deposited on the second sacrificial layer 23 to form a stacked layer of a preset thickness, which is a top stacked layer 24. It should be noted that the SiGe 1 material and SiGe 2 material here are only exemplary descriptions, and other materials may actually be used.

[0200] Step 2: sequentially etch the top stack layer 24, the second sacrificial layer 23, the bottom stack layer 22, and the first sacrificial layer 21 until the substrate 20 to form a semiconductor structure (see Figure 5A (b) in the figure.

[0201] It can be understood that the first semiconductor structure 251 close to the substrate, the second semiconductor structure 252 far from the substrate, the second middle sacrificial layer 253 and the first middle sacrificial layer 254 can be formed by etching.

[0202] Step 3: Deposit an oxide material on the substrate 20 to form an isolation structure 26, and perform etching and CMP to the upper surface of the first intermediate sacrificial layer 254 (see Figure 5A (c) in the figure.

[0203] Step 4: The gate region is opened by photolithography, and polysilicon and other materials are deposited in the gate region to form a pseudo gate structure 27 shared by the front and back sides, and a sidewall (spacer) 28 is formed on both sides of the pseudo gate structure and the first semiconductor structure 251, the second semiconductor structure 252 and the second intermediate sacrificial layer 253 (see Figure 5B (a) in the figure.

[0204] By defining the gate regions of the front transistor and the back transistor in the flip-stack transistor through the pseudo-gate structure, self-alignment of the upper and lower transistors in the flip-stack transistor at the gate region can be achieved.

[0205] Step 5: Etch the sidewall 28 until the second intermediate sacrificial layer 253 to expose the second semiconductor structure 252 of the front transistor (see Figure 5B (b) in the figure.

[0206] Step 6: Etch the second semiconductor structure in the source and drain region of the front transistor (see Figure 5B (c) in the figure.

[0207] Step 7: Selectively etch the second intermediate sacrificial layer 253 between the semiconductor structures of the front and back transistors, and fill the etched grooves with insulating material to form an MDI layer 29 (see Figure 5C (a) in the figure.

[0208] Step 8: Laterally etch a portion of the SiGe2 material of the front transistor, fill with insulating material and etch again to form a first inner spacer 30 located on both sides of the SiGe2 of the front transistor (see Figure 5C (b) in the figure.

[0209] In some embodiments, the eighth step of forming the first inner sidewall may be performed simultaneously with the seventh step of forming the MDI layer.

[0210] Step 9: Anisotropic etching removes the spacer and the first semiconductor structure of the back transistor in the source and drain region (see Figure 5C (c) in the figure.

[0211] Step 10: Anisotropically etch the first intermediate sacrificial layer 254 and the isolation structure 26 in the source and drain regions (see Figure 5D (a) in the figure.

[0212] Step 11: Fill the source and drain regions with insulating material to form a filling structure 31 covering the source and drain regions of the back transistor (see Figure 5D (b) in the figure.

[0213] Step 12: Form a source-drain isolation structure 32 on the filling structure 31 (see Figure 5D (c) in the figure.

[0214] It should be noted that the source-drain isolation structure is formed on the filling structure here, and the embodiment of the present application can also etch the filling structure after the first flipping, and then form the source-drain isolation structure. Or after the first flipping, part of the filling structure is etched, and the remaining filling structure is used as the source-drain isolation structure.

[0215] Step 13: Form the first source-drain structure 112 of the front transistor (see Figure 5E (a) in the figure.

[0216] Step 14: Deposit an interlayer dielectric in the source and drain regions to form a first interlayer dielectric layer 113 (see Figure 5E (b) in the figure.

[0217] Step 15: Deposit insulating material on the first interlayer dielectric layer 113 to form a first insulating layer 13, bond the first carrier wafer 14 to the first insulating layer 13, and perform the first flip (see Figure 5E (c) in the figure.

[0218] Step 16: Thinning and CMP removal of substrate 20 (see Fig. 5F (a) in the figure.

[0219] Step 17: Selectively etch the isolation structure 26 in the gate region (see Fig. 5F (b) in the figure.

[0220] Step 18: Fill the etched area with polysilicon or other materials to supplement the pseudo gate structure formed above (see Fig. 5F (c) in the figure.

[0221] Step 19: Remove the filling structure 31 (see Figure 5G (a) in the figure.

[0222] Step 20: Laterally etch a portion of the SiGe2 material of the back transistor, fill it with insulating material and etch it to form a second inner sidewall 34 located on both sides of the SiGe2 of the back transistor (see Figure 5G (b) in the figure.

[0223] Step 21: Forming a second source-drain structure 122 and a second interlayer dielectric layer 123 of the back transistor (see Figure 5G (c) in the figure.

[0224] Step 22: Remove the dummy gate structure 27 (see Figure 5H (a) in the figure.

[0225] Step 23: Remove the SiGe2 material and the first intermediate sacrificial layer in the first semiconductor structure and the second semiconductor structure to form a first nanosheet structure 111 and a second nanosheet structure 121, and form a first gate structure 114 based on the first nanosheet structure 111 and a second gate structure 124 based on the second nanosheet structure 121 (see Figure 5H (b) in the figure.

[0226] It can be understood that an insulating material can be deposited on the surface of the first nanosheet structure 111 to form a first gate dielectric layer 1141, and a metal material can be deposited on the first gate dielectric layer 1141 in the gate region to form a first gate electrode layer 1142. The first gate dielectric layer 1141 and the first gate electrode layer 1142 constitute a first gate structure 114. An insulating material is deposited on the surface of the second nanosheet structure 121 to form a second gate dielectric layer 1241, and a metal material is deposited on the second gate dielectric layer 1241 in the gate region to form a second gate electrode layer 1242. The second gate dielectric layer 1241 and the second gate electrode layer 1242 constitute a second gate structure 124. Therefore, the gate structure of the front transistor and the gate structure of the back transistor in the embodiment of the present application are formed at the back at one time.

[0227] Step 24: Deposit insulating material on the second gate structure 124 and the second interlayer dielectric layer 123 to form a second insulating layer 15, bond the second carrier wafer 16 to the second insulating layer 15, and perform a second flip (see Figure 5H (c) in the figure.

[0228] Step 25: Remove the first insulating layer 13 and the first carrier wafer 14, and then form the first isolation layer 36, the first source and drain metal 115 and the first metal interconnect layer 116 according to the standard process flow (see Fig.5I (a) in the figure.

[0229] Step 26: Deposit insulating material on the first metal interconnect layer 116 to form a third insulating layer 17, bond the third carrier wafer 18 to the third insulating layer 17, and perform a third flip (see Fig.5I (b) in the figure.

[0230] Step 27: Remove the second insulating layer 15 and the second carrier wafer 16, and then form the first isolation layer 36, the first source and drain metal 115 and the first metal interconnect layer 116 according to the standard process flow (see Figure 5J ).

[0231] The fourth preparation process is introduced below, that is, the gate structure of the front transistor and the gate structure of the back transistor are formed on both sides, and a flip-chip stacked transistor is formed by flipping the wafer three times. 6A to 6H is a schematic structural diagram of a flip-chip stack transistor in a fourth preparation process according to an embodiment of the present application, Fig.6I This is a fourth structural schematic diagram of the flip-chip stacked transistor according to an embodiment of the present application.

[0232] Step 1: forming a first sacrificial layer 21 on the original substrate 20, forming a bottom stacking layer 22 on the first sacrificial layer 21, forming a second sacrificial layer 23 on the bottom stacking layer 22, and forming a top stacking layer 24 on the second sacrificial layer 23 (see Fig. 6A (a) in the figure.

[0233] For example, a Si layer 20 may be provided, and SiGe1 material may be deposited on the Si layer 20 to form a first sacrificial layer 21; then SiGe2 material and Si material may be alternately deposited on the first sacrificial layer 21 to form a stacked layer of a preset thickness, which is a bottom stacked layer 22; then SiGe1 material may be deposited on the bottom stacked layer 22 to form a second sacrificial layer 23; finally, SiGe2 material and Si material may be alternately deposited on the second sacrificial layer 23 to form a stacked layer of a preset thickness, which is a top stacked layer 24. It should be noted that the SiGe1 material here is only an exemplary description, and other materials may actually be used.

[0234] Step 2: sequentially etch the top stack layer 24, the second sacrificial layer 23, the bottom stack layer 22, and the first sacrificial layer 21 until the substrate 20 to form a semiconductor structure (see Fig. 6A (b) in the figure.

[0235] It can be understood that the first semiconductor structure 251 close to the substrate, the second semiconductor structure 252 far from the substrate, the second middle sacrificial layer 253 and the first middle sacrificial layer 254 can be formed by etching.

[0236] Step 3: Deposit an oxide material on the substrate 20 to form an isolation structure 26, and perform etching and CMP to the upper surface of the first intermediate sacrificial layer 254 (see Fig. 6A (c) in the figure.

[0237] Step 4: Form an oxide layer 37 on the substrate (see Figure 6B (a) in the figure.

[0238] Step 5: depositing polysilicon or other materials on the oxide layer 37, and etching back to the top of the first semiconductor structure 251 to form a first dummy gate structure 38 surrounding the first semiconductor structure 251 (see Figure 6B (b) in the figure.

[0239] Step 6: Deposit an insulating material on the first dummy gate structure 38 and etch back to the bottom of the second semiconductor structure to form a gate isolation structure 39 (see Figure 6B (c) in the figure.

[0240] Step 7: Form a second dummy gate structure 40 surrounding the second semiconductor structure 252 on the gate isolation structure 39 (see Figure 6C (a) in the figure.

[0241] Step 8: Photolithography is performed to etch the pseudo gate structure on the front and back sides of the source and drain regions and the gate isolation structure in the middle, and deposition is performed to form the sidewall 28 (see Figure 6C (b) in the figure.

[0242] Step 9: Etch the sidewall 28 until the second intermediate sacrificial layer 253 to expose the second semiconductor structure 252 of the front transistor (see Figure 6C (c) in the figure.

[0243] Step 10: Etch the second semiconductor structure in the source and drain regions of the front transistor (see Fig.6D (a) in the figure.

[0244] Step 11: Selectively etch the second intermediate sacrificial layer 253 between the semiconductor structures of the front and back transistors, and fill the etched grooves with insulating material to form an MDI layer 29 (see Fig.6D (b) in the figure.

[0245] Step 12: Laterally etch a portion of the SiGe2 material of the front transistor, fill it with insulating material and etch it to form a first inner spacer 30 located on both sides of the SiGe2 of the front transistor (see Fig.6D (c) in the figure.

[0246] Step 13: Anisotropic etching removes the spacer and the first semiconductor structure in the source and drain regions of the back transistor (see Fig. 6E (a) in the figure.

[0247] Step 14: Anisotropically etch the first intermediate sacrificial layer 254 and the isolation structure 26 in the source and drain regions (see Fig. 6E (b) in the figure.

[0248] Step 15: Fill the source and drain regions with insulating material to form a filling structure 31 covering the source and drain regions of the back transistor (see Fig. 6E (c) in the figure.

[0249] Step 16: Form a source-drain isolation structure 32 on the filling structure 31 (see Fig. 6F (a) in the figure.

[0250] Step 17: Form the first source-drain structure 112 of the front transistor (see Fig. 6F (b) in the figure.

[0251] Step 18: Deposit an interlayer dielectric in the source and drain regions to form a first interlayer dielectric layer 113 (see Fig. 6F (c) in the figure.

[0252] Step 19: Deposit insulating material on the first interlayer dielectric layer 113 to form a first insulating layer 13, bond the first carrier wafer 14 to the first insulating layer 13, and perform the first flip (see Figure 6G (a) in the figure.

[0253] Step 20: Form the gate structure and gate cut-off structure of the back transistor according to the standard process flow (see Figure 6G (b) in the figure.

[0254] It can be understood that the substrate 20 can be removed first, the isolation structure 26 of the gate area can be selectively etched, and the etched area can be filled with materials such as polysilicon to supplement the pseudo gate structure formed above; the filling structure can be removed, a part of the SiGe2 material of the back transistor can be laterally etched, and the insulating material can be filled and etched to form a second inner sidewall 34 located on both sides of the SiGe2 of the back transistor to form a second source and drain structure 122 and a second interlayer dielectric layer 123 of the back transistor; then the first pseudo gate structure 38 can be removed, the SiGe2 material in the first semiconductor structure can be removed to form a second nanosheet structure 121, and a second gate structure 124 can be formed based on the second nanosheet structure 121; a second gate cut-off structure 41 can be formed on both sides of the second gate structure 124.

[0255] Step 21: Deposit insulating material on the gate structure and gate cut-off structure of the back transistor to form a second insulating layer 15, bond the second carrier wafer 16 to the second insulating layer 15, and perform a second flip (see Figure 6G (c) in the figure.

[0256] Step 22: Follow the standard process flow to form the first gate structure 114, the first source and drain metal 115 and the first metal interconnect layer 116 of the front transistor (see Figure 6H (a) in the figure.

[0257] It can be understood that the first insulating layer 13 and the first carrier wafer 14 are first thinned and removed by CMP, and then the second dummy gate structure 40 is removed, and the SiGe2 material in the second semiconductor structure is removed to form a first nanosheet structure 111, and a first gate structure 114 is formed based on the first nanosheet structure 111, a first gate cut-off structure 42 is formed on both sides of the first gate structure 114, a first isolation layer 36 is formed on the first gate structure 114 and the first interlayer dielectric layer 113, and a first source-drain metal 115 is formed on the first source-drain structure 112; and back-end interconnection is performed to form a first metal interconnection layer 116.

[0258] Step 23: Deposit insulating material on the first metal interconnect layer 116 to form a third insulating layer 17, bond the third carrier wafer 18 to the third insulating layer 17, and perform a third flip (see Figure 6H (b) in the figure.

[0259] Step 24: Remove the second insulating layer 15 and the second carrier wafer 16, and then form a second isolation layer 35, a second source and drain metal 125 and a second metal interconnect layer 126 according to a standard process flow (see Fig.6I ).

[0260] In an embodiment of the present application, the gate structure of the flip-chip stacked transistor can be formed at one time on the back side, or it can be formed separately on the front and back sides. There may be an isolation structure (i.e., a gate isolation structure) between the gate structure of the front transistor and the gate structure of the back transistor, or there may be no isolation structure. A gate cut-off structure may be formed on both sides of the gate structure, or there may be no gate cut-off structure. In the case of forming a gate cut-off structure, the gate cut-off structure may be formed at one time on the back side, or it may be formed at one time on the front side, or it may be formed separately on the front and back sides. There may be an isolation structure (i.e., a source-drain isolation structure) between the source-drain structure of the front transistor and the source-drain structure of the back transistor, or there may be no isolation structure. In the case of a source-drain isolation structure, the source-drain isolation structure may be formed on the front side or on the back side, and an isolation material may be deposited separately to form a source-drain isolation structure, or the filling structure retained after the etching part is used as a source-drain isolation structure. In the embodiment of the present application, the method for forming the gate structure is completely independent of the method for forming the source-drain region, and the various formation methods of the two may be arranged and combined, and the embodiment of the present application does not specifically limit this. In addition, the embodiment of the present application may form an MDI layer or may not form an MDI layer. When the MDI layer is not formed, in the first step of the above-mentioned various preparation processes, after forming the bottom stacking layer 22, the second sacrificial layer 23 is not formed, and the top stacking layer 24 can be directly formed on the bottom stacking layer 22.

[0261] Furthermore, the flip-chip stacked transistor provided in the embodiment of the present application can be detected using a detection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the embodiment of the present application can use TEM slicing to detect the structure of the flip-chip stacked transistor.

[0262] An embodiment of the present application provides a semiconductor device, including: a flip-chip stacked transistor as described in the above embodiment.

[0263] The embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device comprises the above flip-chip stacked transistor.

[0264] In the description of the embodiments of the present application, the description with reference to the terms "one embodiment", "an embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine the different embodiments or examples described in the present application and the features of the different embodiments or examples without contradiction.

[0265] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a flip-chip stacked transistor, characterized in that: include: Forming a first semiconductor structure and a second semiconductor structure stacked in sequence on a substrate; Etching the first semiconductor structure and the second semiconductor structure located in the source-drain region, and filling the first source-drain region corresponding to the first semiconductor structure with an insulating material to form a filling structure; Forming a third semiconductor structure based on the second semiconductor structure through a front-end process, wherein the third semiconductor structure includes a first source-drain structure formed in a second source-drain region, and the second source-drain region corresponds to the second semiconductor structure; Flipping the third semiconductor structure, and removing the substrate and the filling structure to expose the first semiconductor structure, wherein the first semiconductor structure includes the first source and drain regions; Based on the first semiconductor structure, forming a fourth semiconductor structure, wherein the fourth semiconductor structure at least includes a second source-drain structure formed in the first source-drain region; Based on the third semiconductor structure and the fourth semiconductor structure, a first transistor and a second transistor are formed respectively.

2. The method according to claim 1, characterized in that: The forming of a fourth semiconductor structure based on the first semiconductor structure comprises: epitaxially growing the second source-drain structure at the first source-drain region; The step of forming a first transistor based on the third semiconductor structure comprises: After forming the fourth semiconductor structure, flipping the fourth semiconductor structure and exposing the third semiconductor structure; Depositing a metal material on the first source-drain structure in the third semiconductor structure to form a first source-drain metal; Through a back-end process, back-end interconnection is performed on the first source-drain metal to form a first metal interconnection layer.

3. The method according to claim 2, characterized in that The forming of a second transistor based on the fourth semiconductor structure comprises: After forming the first transistor, flipping the first transistor and exposing the fourth semiconductor structure; Depositing a metal material on the second source-drain structure in the fourth semiconductor structure to form a second source-drain metal; Through a back-end process, back-end interconnection is performed on the second source / drain metal to form a second metal interconnection layer.

4. The method according to claim 1, characterized in that: The forming of a fourth semiconductor structure based on the first semiconductor structure comprises: epitaxially growing the second source-drain structure at the first source-drain region; Based on the first semiconductor structure, forming a gate structure of the fourth semiconductor structure; Depositing metal on the second source-drain structure to form a second source-drain metal; Performing back-end interconnection on the second source / drain metal through a back-end process to form a second metal interconnection layer; The step of forming a first transistor based on the third semiconductor structure comprises: After forming the fourth semiconductor structure, flipping the fourth semiconductor structure and exposing the third semiconductor structure; Depositing a metal material on the first source-drain structure in the third semiconductor structure to form a first source-drain metal; Through a back-end process, back-end interconnection is performed on the first source-drain metal to form a first metal interconnection layer.

5. The method according to claim 1, characterized in that Before etching the first semiconductor structure and the second semiconductor structure located in the source and drain regions, the method further includes: forming an isolation structure on a substrate to expose the first semiconductor structure and the second semiconductor structure; Depositing a semiconductor material on the isolation structure to form a dummy gate structure surrounding the first semiconductor structure and the second semiconductor structure; The forming of a fourth semiconductor structure based on the first semiconductor structure comprises: epitaxially growing the second source-drain structure at the first source-drain region; The dummy gate structure is removed to form a first gate structure of the third semiconductor structure and a second gate structure of the fourth semiconductor structure.

6. The method according to claim 1, characterized in that Before etching the first semiconductor structure and the second semiconductor structure located in the source and drain regions, the method further includes: forming an isolation structure on a substrate to expose the first semiconductor structure and the second semiconductor structure; depositing a semiconductor material on the isolation structure to form a first dummy gate structure surrounding the first semiconductor structure; forming a gate isolation structure on the first dummy gate structure; depositing a semiconductor material on the gate isolation structure to form a second dummy gate structure surrounding the second semiconductor structure; The forming of a fourth semiconductor structure based on the first semiconductor structure comprises: epitaxially growing the second source-drain structure at the first source-drain region; The first dummy gate structure is removed to form a second gate structure of the fourth semiconductor structure.

7. The method according to claim 6, characterized in that The step of forming a first transistor based on the third semiconductor structure comprises: After forming the fourth semiconductor structure, flipping the fourth semiconductor structure and exposing the third semiconductor structure; removing the second dummy gate structure to form a first gate structure of the first transistor; Depositing a metal material on the first source-drain structure in the third semiconductor structure to form a first source-drain metal; Through a back-end process, back-end interconnection is performed on the first source-drain metal to form a first metal interconnection layer.

8. A flip-chip stack transistor, prepared using the preparation method according to any one of claims 1 to 7, characterized in that: include: a first transistor; The second transistor, the first transistor and the second transistor are arranged back to back, the second semiconductor structure of the first transistor is self-aligned with the first semiconductor structure of the second transistor, and the first source-drain structure of the first transistor is self-aligned with the second source-drain structure of the second transistor in a vertical direction.

9. A semiconductor device, characterized in that: include: The flip-chip stack transistor as claimed in claim 8.

10. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 9, wherein the semiconductor device is arranged on the circuit board.

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